simple_thread.cc revision 8809 
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 *          Lisa Hsu
31 *          Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/fs_translating_port_proxy.hh"
51#include "mem/se_translating_port_proxy.hh"
52#include "params/BaseCPU.hh"
53#include "sim/full_system.hh"
54#include "sim/process.hh"
55#include "sim/serialize.hh"
56#include "sim/sim_exit.hh"
57#include "sim/system.hh"
58
59using namespace std;
60
61// constructor
62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
63                           TheISA::TLB *_itb, TheISA::TLB *_dtb)
64    : ThreadState(_cpu, _thread_num, _process), itb(_itb), dtb(_dtb)
65{
66    clearArchRegs();
67    tc = new ProxyThreadContext<SimpleThread>(this);
68}
69SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
70                           TheISA::TLB *_itb, TheISA::TLB *_dtb,
71                           bool use_kernel_stats)
72    : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb)
73{
74    tc = new ProxyThreadContext<SimpleThread>(this);
75
76    quiesceEvent = new EndQuiesceEvent(tc);
77
78    clearArchRegs();
79
80    if (baseCpu->params()->profile) {
81        profile = new FunctionProfile(system->kernelSymtab);
82        Callback *cb =
83            new MakeCallback<SimpleThread,
84            &SimpleThread::dumpFuncProfile>(this);
85        registerExitCallback(cb);
86    }
87
88    // let's fill with a dummy node for now so we don't get a segfault
89    // on the first cycle when there's no node available.
90    static ProfileNode dummyNode;
91    profileNode = &dummyNode;
92    profilePC = 3;
93
94    if (use_kernel_stats)
95        kernelStats = new TheISA::Kernel::Statistics(system);
96}
97
98SimpleThread::SimpleThread()
99    : ThreadState(NULL, -1, NULL)
100{
101    tc = new ProxyThreadContext<SimpleThread>(this);
102}
103
104SimpleThread::~SimpleThread()
105{
106    delete tc;
107}
108
109void
110SimpleThread::takeOverFrom(ThreadContext *oldContext)
111{
112    // some things should already be set up
113    if (FullSystem)
114        assert(system == oldContext->getSystemPtr());
115    assert(process == oldContext->getProcessPtr());
116
117    copyState(oldContext);
118    if (FullSystem) {
119        EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
120        if (quiesce) {
121            // Point the quiesce event's TC at this TC so that it wakes up
122            // the proper CPU.
123            quiesce->tc = tc;
124        }
125        if (quiesceEvent) {
126            quiesceEvent->tc = tc;
127        }
128
129        TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
130        if (stats) {
131            kernelStats = stats;
132        }
133    }
134
135    storeCondFailures = 0;
136
137    oldContext->setStatus(ThreadContext::Halted);
138}
139
140void
141SimpleThread::copyTC(ThreadContext *context)
142{
143    copyState(context);
144
145    if (FullSystem) {
146        EndQuiesceEvent *quiesce = context->getQuiesceEvent();
147        if (quiesce) {
148            quiesceEvent = quiesce;
149        }
150        TheISA::Kernel::Statistics *stats = context->getKernelStats();
151        if (stats) {
152            kernelStats = stats;
153        }
154    }
155}
156
157void
158SimpleThread::copyState(ThreadContext *oldContext)
159{
160    // copy over functional state
161    _status = oldContext->status();
162    copyArchRegs(oldContext);
163    if (FullSystem)
164        funcExeInst = oldContext->readFuncExeInst();
165
166    _threadId = oldContext->threadId();
167    _contextId = oldContext->contextId();
168}
169
170void
171SimpleThread::serialize(ostream &os)
172{
173    ThreadState::serialize(os);
174    SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
175    SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
176    _pcState.serialize(os);
177    // thread_num and cpu_id are deterministic from the config
178
179    //
180    // Now must serialize all the ISA dependent state
181    //
182    isa.serialize(baseCpu, os);
183}
184
185
186void
187SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
188{
189    ThreadState::unserialize(cp, section);
190    UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
191    UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
192    _pcState.unserialize(cp, section);
193    // thread_num and cpu_id are deterministic from the config
194
195    //
196    // Now must unserialize all the ISA dependent state
197    //
198    isa.unserialize(baseCpu, cp, section);
199}
200
201void
202SimpleThread::dumpFuncProfile()
203{
204    std::ostream *os = simout.create(csprintf("profile.%s.dat",
205                                              baseCpu->name()));
206    profile->dump(tc, *os);
207}
208
209void
210SimpleThread::activate(int delay)
211{
212    if (status() == ThreadContext::Active)
213        return;
214
215    lastActivate = curTick();
216
217//    if (status() == ThreadContext::Unallocated) {
218//      cpu->activateWhenReady(_threadId);
219//      return;
220//   }
221
222    _status = ThreadContext::Active;
223
224    // status() == Suspended
225    baseCpu->activateContext(_threadId, delay);
226}
227
228void
229SimpleThread::suspend()
230{
231    if (status() == ThreadContext::Suspended)
232        return;
233
234    lastActivate = curTick();
235    lastSuspend = curTick();
236    _status = ThreadContext::Suspended;
237    baseCpu->suspendContext(_threadId);
238}
239
240
241void
242SimpleThread::halt()
243{
244    if (status() == ThreadContext::Halted)
245        return;
246
247    _status = ThreadContext::Halted;
248    baseCpu->haltContext(_threadId);
249}
250
251
252void
253SimpleThread::regStats(const string &name)
254{
255    if (FullSystem && kernelStats)
256        kernelStats->regStats(name + ".kern");
257}
258
259void
260SimpleThread::copyArchRegs(ThreadContext *src_tc)
261{
262    TheISA::copyRegs(src_tc, tc);
263}
264
265