simple_thread.cc revision 8799:dac1e33e07b0
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 373565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 385529Snate@binkert.org#include "arch/stacktrace.hh" 398777Sgblack@eecs.umich.edu#include "arch/utility.hh" 401917SN/A#include "base/callback.hh" 411070SN/A#include "base/cprintf.hh" 421917SN/A#include "base/output.hh" 432188SN/A#include "base/trace.hh" 448777Sgblack@eecs.umich.edu#include "config/the_isa.hh" 458777Sgblack@eecs.umich.edu#include "cpu/base.hh" 461917SN/A#include "cpu/profile.hh" 472290SN/A#include "cpu/quiesce_event.hh" 488777Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh" 498777Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 508706Sandreas.hansson@arm.com#include "params/BaseCPU.hh" 518799Sgblack@eecs.umich.edu#include "mem/fs_translating_port_proxy.hh" 528809Sgblack@eecs.umich.edu#include "mem/se_translating_port_proxy.hh" 538793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 548777Sgblack@eecs.umich.edu#include "sim/process.hh" 551070SN/A#include "sim/serialize.hh" 561917SN/A#include "sim/sim_exit.hh" 572519SN/A#include "sim/process.hh" 582SN/A#include "sim/system.hh" 592SN/A 602SN/Ausing namespace std; 612SN/A 628820Sgblack@eecs.umich.edu// constructor 638820Sgblack@eecs.umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 648820Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb) 658820Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, _process), 668820Sgblack@eecs.umich.edu cpu(_cpu), itb(_itb), dtb(_dtb) 678766Sgblack@eecs.umich.edu{ 688766Sgblack@eecs.umich.edu clearArchRegs(); 698766Sgblack@eecs.umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 708766Sgblack@eecs.umich.edu} 712683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 726022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 732683Sktlim@umich.edu bool use_kernel_stats) 748809Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, NULL), 752SN/A cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) 762683Sktlim@umich.edu 772190SN/A{ 782680SN/A tc = new ProxyThreadContext<SimpleThread>(this); 792290SN/A 806316Sgblack@eecs.umich.edu quiesceEvent = new EndQuiesceEvent(tc); 811917SN/A 828735Sandreas.hanson@arm.com clearArchRegs(); 831982SN/A 841917SN/A if (cpu->params()->profile) { 852683Sktlim@umich.edu profile = new FunctionProfile(system->kernelSymtab); 862683Sktlim@umich.edu Callback *cb = 871917SN/A new MakeCallback<SimpleThread, 881917SN/A &SimpleThread::dumpFuncProfile>(this); 891917SN/A registerExitCallback(cb); 901917SN/A } 911917SN/A 921917SN/A // let's fill with a dummy node for now so we don't get a segfault 931917SN/A // on the first cycle when there's no node available. 941917SN/A static ProfileNode dummyNode; 952521SN/A profileNode = &dummyNode; 965482Snate@binkert.org profilePC = 3; 973548Sgblack@eecs.umich.edu 982SN/A if (use_kernel_stats) 992862Sktlim@umich.edu kernelStats = new TheISA::Kernel::Statistics(system); 1002864Sktlim@umich.edu} 1016331Sgblack@eecs.umich.edu 1022190SN/ASimpleThread::SimpleThread() 1032683Sktlim@umich.edu : ThreadState(NULL, -1, NULL) 1042190SN/A{ 1052190SN/A tc = new ProxyThreadContext<SimpleThread>(this); 1062683Sktlim@umich.edu} 1071070SN/A 1082680SN/ASimpleThread::~SimpleThread() 1091070SN/A{ 1101070SN/A delete tc; 1111917SN/A} 1122683Sktlim@umich.edu 113180SN/Avoid 114180SN/ASimpleThread::takeOverFrom(ThreadContext *oldContext) 1158793Sgblack@eecs.umich.edu{ 1168793Sgblack@eecs.umich.edu // some things should already be set up 1172235SN/A if (FullSystem) 118180SN/A assert(system == oldContext->getSystemPtr()); 1192862Sktlim@umich.edu assert(process == oldContext->getProcessPtr()); 1208793Sgblack@eecs.umich.edu 1218793Sgblack@eecs.umich.edu copyState(oldContext); 1228793Sgblack@eecs.umich.edu if (FullSystem) { 1238793Sgblack@eecs.umich.edu EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1248793Sgblack@eecs.umich.edu if (quiesce) { 1258793Sgblack@eecs.umich.edu // Point the quiesce event's TC at this TC so that it wakes up 1268793Sgblack@eecs.umich.edu // the proper CPU. 1278793Sgblack@eecs.umich.edu quiesce->tc = tc; 1288793Sgblack@eecs.umich.edu } 1298793Sgblack@eecs.umich.edu if (quiesceEvent) { 1308793Sgblack@eecs.umich.edu quiesceEvent->tc = tc; 1318793Sgblack@eecs.umich.edu } 1328793Sgblack@eecs.umich.edu 1338793Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1348793Sgblack@eecs.umich.edu if (stats) { 1352313SN/A kernelStats = stats; 136180SN/A } 137180SN/A } 138180SN/A 1396029Ssteve.reinhardt@amd.com storeCondFailures = 0; 140180SN/A 141180SN/A oldContext->setStatus(ThreadContext::Halted); 1422SN/A} 1432864Sktlim@umich.edu 1442864Sktlim@umich.eduvoid 1452864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1462864Sktlim@umich.edu{ 1478793Sgblack@eecs.umich.edu copyState(context); 1488793Sgblack@eecs.umich.edu 1498793Sgblack@eecs.umich.edu if (FullSystem) { 1508793Sgblack@eecs.umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1518793Sgblack@eecs.umich.edu if (quiesce) { 1528793Sgblack@eecs.umich.edu quiesceEvent = quiesce; 1538793Sgblack@eecs.umich.edu } 1548793Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1558793Sgblack@eecs.umich.edu if (stats) { 1562864Sktlim@umich.edu kernelStats = stats; 1572864Sktlim@umich.edu } 1582864Sktlim@umich.edu } 1592864Sktlim@umich.edu} 1602862Sktlim@umich.edu 1612862Sktlim@umich.eduvoid 1622862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1632862Sktlim@umich.edu{ 1642862Sktlim@umich.edu // copy over functional state 1658793Sgblack@eecs.umich.edu _status = oldContext->status(); 1668793Sgblack@eecs.umich.edu copyArchRegs(oldContext); 1675714Shsul@eecs.umich.edu if (FullSystem) 1685715Shsul@eecs.umich.edu funcExeInst = oldContext->readFuncExeInst(); 1695714Shsul@eecs.umich.edu 1702862Sktlim@umich.edu _threadId = oldContext->threadId(); 1712862Sktlim@umich.edu _contextId = oldContext->contextId(); 1722862Sktlim@umich.edu} 1732683Sktlim@umich.edu 174217SN/Avoid 1752862Sktlim@umich.eduSimpleThread::serialize(ostream &os) 1766315Sgblack@eecs.umich.edu{ 1776316Sgblack@eecs.umich.edu ThreadState::serialize(os); 1787720Sgblack@eecs.umich.edu SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 179223SN/A SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 1806677SBrad.Beckmann@amd.com _pcState.serialize(os); 1816677SBrad.Beckmann@amd.com // thread_num and cpu_id are deterministic from the config 1826677SBrad.Beckmann@amd.com 1836677SBrad.Beckmann@amd.com // 1848735Sandreas.hanson@arm.com // Now must serialize all the ISA dependent state 185217SN/A // 186217SN/A isa.serialize(cpu, os); 187217SN/A} 188217SN/A 1892683Sktlim@umich.edu 190217SN/Avoid 1912862Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 1926315Sgblack@eecs.umich.edu{ 1936316Sgblack@eecs.umich.edu ThreadState::unserialize(cp, section); 1947720Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 195223SN/A UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 1966677SBrad.Beckmann@amd.com _pcState.unserialize(cp, section); 1976677SBrad.Beckmann@amd.com // thread_num and cpu_id are deterministic from the config 1986677SBrad.Beckmann@amd.com 1996677SBrad.Beckmann@amd.com // 2008735Sandreas.hanson@arm.com // Now must unserialize all the ISA dependent state 201217SN/A // 202217SN/A isa.unserialize(cpu, cp, section); 2032683Sktlim@umich.edu} 2042683Sktlim@umich.edu 2052683Sktlim@umich.eduvoid 2068735Sandreas.hanson@arm.comSimpleThread::dumpFuncProfile() 2078735Sandreas.hanson@arm.com{ 2082683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2092683Sktlim@umich.edu profile->dump(tc, *os); 210217SN/A} 211217SN/A 2122683Sktlim@umich.eduvoid 2132SN/ASimpleThread::activate(int delay) 2142680SN/A{ 2152SN/A if (status() == ThreadContext::Active) 2162SN/A return; 2177823Ssteve.reinhardt@amd.com 2182188SN/A lastActivate = curTick(); 2194400Srdreslin@umich.edu 2205715Shsul@eecs.umich.edu// if (status() == ThreadContext::Unallocated) { 2215543Ssaidi@eecs.umich.edu// cpu->activateWhenReady(_threadId); 2224400Srdreslin@umich.edu// return; 2232290SN/A// } 2242680SN/A 2252290SN/A _status = ThreadContext::Active; 2262290SN/A 2278735Sandreas.hanson@arm.com // status() == Suspended 228393SN/A cpu->activateContext(_threadId, delay); 229393SN/A} 230393SN/A 2312683Sktlim@umich.eduvoid 232393SN/ASimpleThread::suspend() 2332680SN/A{ 234393SN/A if (status() == ThreadContext::Suspended) 235393SN/A return; 2367823Ssteve.reinhardt@amd.com 2377823Ssteve.reinhardt@amd.com lastActivate = curTick(); 2382680SN/A lastSuspend = curTick(); 2398735Sandreas.hanson@arm.com _status = ThreadContext::Suspended; 2402SN/A cpu->suspendContext(_threadId); 2412SN/A} 242393SN/A 243393SN/A 2442683Sktlim@umich.eduvoid 245393SN/ASimpleThread::halt() 2462680SN/A{ 247393SN/A if (status() == ThreadContext::Halted) 248393SN/A return; 2492680SN/A 2508735Sandreas.hanson@arm.com _status = ThreadContext::Halted; 251393SN/A cpu->haltContext(_threadId); 252393SN/A} 253393SN/A 254393SN/A 2552683Sktlim@umich.eduvoid 2562SN/ASimpleThread::regStats(const string &name) 2578793Sgblack@eecs.umich.edu{ 2582341SN/A if (FullSystem && kernelStats) 2592SN/A kernelStats->regStats(name + ".kern"); 260716SN/A} 261716SN/A 2622683Sktlim@umich.eduvoid 2632190SN/ASimpleThread::copyArchRegs(ThreadContext *src_tc) 2642680SN/A{ 2652190SN/A TheISA::copyRegs(src_tc, tc); 2662190SN/A} 267 268