simple_thread.cc revision 8793 
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 *          Lisa Hsu
31 *          Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/translating_port.hh"
51#include "mem/vport.hh"
52#include "params/BaseCPU.hh"
53#include "sim/full_system.hh"
54#include "sim/process.hh"
55#include "sim/serialize.hh"
56#include "sim/sim_exit.hh"
57#include "sim/system.hh"
58
59using namespace std;
60
61// constructor
62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
63                           TheISA::TLB *_itb, TheISA::TLB *_dtb)
64    : ThreadState(_cpu, _thread_num, _process),
65      cpu(_cpu), itb(_itb), dtb(_dtb)
66{
67    clearArchRegs();
68    tc = new ProxyThreadContext<SimpleThread>(this);
69}
70SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
71                           TheISA::TLB *_itb, TheISA::TLB *_dtb,
72                           bool use_kernel_stats)
73    : ThreadState(_cpu, _thread_num, NULL),
74      cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
75
76{
77    tc = new ProxyThreadContext<SimpleThread>(this);
78
79    quiesceEvent = new EndQuiesceEvent(tc);
80
81    clearArchRegs();
82
83    if (cpu->params()->profile) {
84        profile = new FunctionProfile(system->kernelSymtab);
85        Callback *cb =
86            new MakeCallback<SimpleThread,
87            &SimpleThread::dumpFuncProfile>(this);
88        registerExitCallback(cb);
89    }
90
91    // let's fill with a dummy node for now so we don't get a segfault
92    // on the first cycle when there's no node available.
93    static ProfileNode dummyNode;
94    profileNode = &dummyNode;
95    profilePC = 3;
96
97    if (use_kernel_stats)
98        kernelStats = new TheISA::Kernel::Statistics(system);
99}
100
101SimpleThread::SimpleThread()
102    : ThreadState(NULL, -1, NULL)
103{
104    tc = new ProxyThreadContext<SimpleThread>(this);
105}
106
107SimpleThread::~SimpleThread()
108{
109    delete physPort;
110    delete virtPort;
111    delete tc;
112}
113
114void
115SimpleThread::takeOverFrom(ThreadContext *oldContext)
116{
117    // some things should already be set up
118    if (FullSystem)
119        assert(system == oldContext->getSystemPtr());
120    assert(process == oldContext->getProcessPtr());
121
122    copyState(oldContext);
123    if (FullSystem) {
124        EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
125        if (quiesce) {
126            // Point the quiesce event's TC at this TC so that it wakes up
127            // the proper CPU.
128            quiesce->tc = tc;
129        }
130        if (quiesceEvent) {
131            quiesceEvent->tc = tc;
132        }
133
134        TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
135        if (stats) {
136            kernelStats = stats;
137        }
138    }
139
140    storeCondFailures = 0;
141
142    oldContext->setStatus(ThreadContext::Halted);
143}
144
145void
146SimpleThread::copyTC(ThreadContext *context)
147{
148    copyState(context);
149
150    if (FullSystem) {
151        EndQuiesceEvent *quiesce = context->getQuiesceEvent();
152        if (quiesce) {
153            quiesceEvent = quiesce;
154        }
155        TheISA::Kernel::Statistics *stats = context->getKernelStats();
156        if (stats) {
157            kernelStats = stats;
158        }
159    }
160}
161
162void
163SimpleThread::copyState(ThreadContext *oldContext)
164{
165    // copy over functional state
166    _status = oldContext->status();
167    copyArchRegs(oldContext);
168    if (FullSystem)
169        funcExeInst = oldContext->readFuncExeInst();
170
171    _threadId = oldContext->threadId();
172    _contextId = oldContext->contextId();
173}
174
175void
176SimpleThread::serialize(ostream &os)
177{
178    ThreadState::serialize(os);
179    SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
180    SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
181    _pcState.serialize(os);
182    // thread_num and cpu_id are deterministic from the config
183
184    //
185    // Now must serialize all the ISA dependent state
186    //
187    isa.serialize(cpu, os);
188}
189
190
191void
192SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
193{
194    ThreadState::unserialize(cp, section);
195    UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
196    UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
197    _pcState.unserialize(cp, section);
198    // thread_num and cpu_id are deterministic from the config
199
200    //
201    // Now must unserialize all the ISA dependent state
202    //
203    isa.unserialize(cpu, cp, section);
204}
205
206void
207SimpleThread::dumpFuncProfile()
208{
209    std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
210    profile->dump(tc, *os);
211}
212
213void
214SimpleThread::activate(int delay)
215{
216    if (status() == ThreadContext::Active)
217        return;
218
219    lastActivate = curTick();
220
221//    if (status() == ThreadContext::Unallocated) {
222//      cpu->activateWhenReady(_threadId);
223//      return;
224//   }
225
226    _status = ThreadContext::Active;
227
228    // status() == Suspended
229    cpu->activateContext(_threadId, delay);
230}
231
232void
233SimpleThread::suspend()
234{
235    if (status() == ThreadContext::Suspended)
236        return;
237
238    lastActivate = curTick();
239    lastSuspend = curTick();
240    _status = ThreadContext::Suspended;
241    cpu->suspendContext(_threadId);
242}
243
244
245void
246SimpleThread::halt()
247{
248    if (status() == ThreadContext::Halted)
249        return;
250
251    _status = ThreadContext::Halted;
252    cpu->haltContext(_threadId);
253}
254
255
256void
257SimpleThread::regStats(const string &name)
258{
259    if (FullSystem && kernelStats)
260        kernelStats->regStats(name + ".kern");
261}
262
263void
264SimpleThread::copyArchRegs(ThreadContext *src_tc)
265{
266    TheISA::copyRegs(src_tc, tc);
267}
268
269