simple_thread.cc revision 8777
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 * Lisa Hsu 31 * Kevin Lim 32 */ 33 34#include <string> 35 36#include "arch/isa_traits.hh" 37#include "arch/kernel_stats.hh" 38#include "arch/stacktrace.hh" 39#include "arch/utility.hh" 40#include "base/callback.hh" 41#include "base/cprintf.hh" 42#include "base/output.hh" 43#include "base/trace.hh" 44#include "config/the_isa.hh" 45#include "cpu/base.hh" 46#include "cpu/profile.hh" 47#include "cpu/quiesce_event.hh" 48#include "cpu/simple_thread.hh" 49#include "cpu/thread_context.hh" 50#include "mem/translating_port.hh" 51#include "mem/vport.hh" 52#include "params/BaseCPU.hh" 53#include "sim/process.hh" 54#include "sim/serialize.hh" 55#include "sim/sim_exit.hh" 56#include "sim/system.hh" 57 58using namespace std; 59 60// constructor 61#if !FULL_SYSTEM 62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 63 TheISA::TLB *_itb, TheISA::TLB *_dtb) 64 : ThreadState(_cpu, _thread_num, _process), 65 cpu(_cpu), itb(_itb), dtb(_dtb) 66{ 67 clearArchRegs(); 68 tc = new ProxyThreadContext<SimpleThread>(this); 69} 70#else 71SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 72 TheISA::TLB *_itb, TheISA::TLB *_dtb, 73 bool use_kernel_stats) 74 : ThreadState(_cpu, _thread_num, NULL), 75 cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) 76 77{ 78 tc = new ProxyThreadContext<SimpleThread>(this); 79 80 quiesceEvent = new EndQuiesceEvent(tc); 81 82 clearArchRegs(); 83 84 if (cpu->params()->profile) { 85 profile = new FunctionProfile(system->kernelSymtab); 86 Callback *cb = 87 new MakeCallback<SimpleThread, 88 &SimpleThread::dumpFuncProfile>(this); 89 registerExitCallback(cb); 90 } 91 92 // let's fill with a dummy node for now so we don't get a segfault 93 // on the first cycle when there's no node available. 94 static ProfileNode dummyNode; 95 profileNode = &dummyNode; 96 profilePC = 3; 97 98 if (use_kernel_stats) 99 kernelStats = new TheISA::Kernel::Statistics(system); 100} 101#endif 102 103SimpleThread::SimpleThread() 104 : ThreadState(NULL, -1, NULL) 105{ 106 tc = new ProxyThreadContext<SimpleThread>(this); 107} 108 109SimpleThread::~SimpleThread() 110{ 111 delete physPort; 112 delete virtPort; 113 delete tc; 114} 115 116void 117SimpleThread::takeOverFrom(ThreadContext *oldContext) 118{ 119 // some things should already be set up 120#if FULL_SYSTEM 121 assert(system == oldContext->getSystemPtr()); 122#endif 123 assert(process == oldContext->getProcessPtr()); 124 125 copyState(oldContext); 126#if FULL_SYSTEM 127 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 128 if (quiesce) { 129 // Point the quiesce event's TC at this TC so that it wakes up 130 // the proper CPU. 131 quiesce->tc = tc; 132 } 133 if (quiesceEvent) { 134 quiesceEvent->tc = tc; 135 } 136 137 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 138 if (stats) { 139 kernelStats = stats; 140 } 141#endif 142 143 storeCondFailures = 0; 144 145 oldContext->setStatus(ThreadContext::Halted); 146} 147 148void 149SimpleThread::copyTC(ThreadContext *context) 150{ 151 copyState(context); 152 153#if FULL_SYSTEM 154 EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 155 if (quiesce) { 156 quiesceEvent = quiesce; 157 } 158 TheISA::Kernel::Statistics *stats = context->getKernelStats(); 159 if (stats) { 160 kernelStats = stats; 161 } 162#endif 163} 164 165void 166SimpleThread::copyState(ThreadContext *oldContext) 167{ 168 // copy over functional state 169 _status = oldContext->status(); 170 copyArchRegs(oldContext); 171#if !FULL_SYSTEM 172 funcExeInst = oldContext->readFuncExeInst(); 173#endif 174 175 _threadId = oldContext->threadId(); 176 _contextId = oldContext->contextId(); 177} 178 179void 180SimpleThread::serialize(ostream &os) 181{ 182 ThreadState::serialize(os); 183 SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 184 SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 185 _pcState.serialize(os); 186 // thread_num and cpu_id are deterministic from the config 187 188 // 189 // Now must serialize all the ISA dependent state 190 // 191 isa.serialize(cpu, os); 192} 193 194 195void 196SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 197{ 198 ThreadState::unserialize(cp, section); 199 UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 200 UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 201 _pcState.unserialize(cp, section); 202 // thread_num and cpu_id are deterministic from the config 203 204 // 205 // Now must unserialize all the ISA dependent state 206 // 207 isa.unserialize(cpu, cp, section); 208} 209 210void 211SimpleThread::dumpFuncProfile() 212{ 213 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 214 profile->dump(tc, *os); 215} 216 217void 218SimpleThread::activate(int delay) 219{ 220 if (status() == ThreadContext::Active) 221 return; 222 223 lastActivate = curTick(); 224 225// if (status() == ThreadContext::Unallocated) { 226// cpu->activateWhenReady(_threadId); 227// return; 228// } 229 230 _status = ThreadContext::Active; 231 232 // status() == Suspended 233 cpu->activateContext(_threadId, delay); 234} 235 236void 237SimpleThread::suspend() 238{ 239 if (status() == ThreadContext::Suspended) 240 return; 241 242 lastActivate = curTick(); 243 lastSuspend = curTick(); 244/* 245#if FULL_SYSTEM 246 // Don't change the status from active if there are pending interrupts 247 if (cpu->checkInterrupts()) { 248 assert(status() == ThreadContext::Active); 249 return; 250 } 251#endif 252*/ 253 _status = ThreadContext::Suspended; 254 cpu->suspendContext(_threadId); 255} 256 257 258void 259SimpleThread::halt() 260{ 261 if (status() == ThreadContext::Halted) 262 return; 263 264 _status = ThreadContext::Halted; 265 cpu->haltContext(_threadId); 266} 267 268 269void 270SimpleThread::regStats(const string &name) 271{ 272#if FULL_SYSTEM 273 if (kernelStats) 274 kernelStats->regStats(name + ".kern"); 275#endif 276} 277 278void 279SimpleThread::copyArchRegs(ThreadContext *src_tc) 280{ 281 TheISA::copyRegs(src_tc, tc); 282} 283 284