simple_thread.cc revision 8767:e575781f71b8
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 * Lisa Hsu 31 * Kevin Lim 32 */ 33 34#include <string> 35 36#include "arch/isa_traits.hh" 37#include "arch/utility.hh" 38#include "config/the_isa.hh" 39#include "cpu/base.hh" 40#include "cpu/simple_thread.hh" 41#include "cpu/thread_context.hh" 42#include "mem/vport.hh" 43#include "params/BaseCPU.hh" 44#include "sim/process.hh" 45 46#if FULL_SYSTEM 47#include "arch/kernel_stats.hh" 48#include "arch/stacktrace.hh" 49#include "base/callback.hh" 50#include "base/cprintf.hh" 51#include "base/output.hh" 52#include "base/trace.hh" 53#include "cpu/profile.hh" 54#include "cpu/quiesce_event.hh" 55#include "sim/serialize.hh" 56#include "sim/sim_exit.hh" 57#else 58#include "mem/translating_port.hh" 59#include "sim/system.hh" 60#endif 61 62using namespace std; 63 64// constructor 65#if !FULL_SYSTEM 66SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 67 TheISA::TLB *_itb, TheISA::TLB *_dtb) 68 : ThreadState(_cpu, _thread_num, _process), 69 cpu(_cpu), itb(_itb), dtb(_dtb) 70{ 71 clearArchRegs(); 72 tc = new ProxyThreadContext<SimpleThread>(this); 73} 74#else 75SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 76 TheISA::TLB *_itb, TheISA::TLB *_dtb, 77 bool use_kernel_stats) 78 : ThreadState(_cpu, _thread_num, NULL), 79 cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) 80 81{ 82 tc = new ProxyThreadContext<SimpleThread>(this); 83 84 quiesceEvent = new EndQuiesceEvent(tc); 85 86 clearArchRegs(); 87 88 if (cpu->params()->profile) { 89 profile = new FunctionProfile(system->kernelSymtab); 90 Callback *cb = 91 new MakeCallback<SimpleThread, 92 &SimpleThread::dumpFuncProfile>(this); 93 registerExitCallback(cb); 94 } 95 96 // let's fill with a dummy node for now so we don't get a segfault 97 // on the first cycle when there's no node available. 98 static ProfileNode dummyNode; 99 profileNode = &dummyNode; 100 profilePC = 3; 101 102 if (use_kernel_stats) 103 kernelStats = new TheISA::Kernel::Statistics(system); 104} 105#endif 106 107SimpleThread::SimpleThread() 108 : ThreadState(NULL, -1, NULL) 109{ 110 tc = new ProxyThreadContext<SimpleThread>(this); 111} 112 113SimpleThread::~SimpleThread() 114{ 115 delete physPort; 116 delete virtPort; 117 delete tc; 118} 119 120void 121SimpleThread::takeOverFrom(ThreadContext *oldContext) 122{ 123 // some things should already be set up 124#if FULL_SYSTEM 125 assert(system == oldContext->getSystemPtr()); 126#endif 127 assert(process == oldContext->getProcessPtr()); 128 129 copyState(oldContext); 130#if FULL_SYSTEM 131 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 132 if (quiesce) { 133 // Point the quiesce event's TC at this TC so that it wakes up 134 // the proper CPU. 135 quiesce->tc = tc; 136 } 137 if (quiesceEvent) { 138 quiesceEvent->tc = tc; 139 } 140 141 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 142 if (stats) { 143 kernelStats = stats; 144 } 145#endif 146 147 storeCondFailures = 0; 148 149 oldContext->setStatus(ThreadContext::Halted); 150} 151 152void 153SimpleThread::copyTC(ThreadContext *context) 154{ 155 copyState(context); 156 157#if FULL_SYSTEM 158 EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 159 if (quiesce) { 160 quiesceEvent = quiesce; 161 } 162 TheISA::Kernel::Statistics *stats = context->getKernelStats(); 163 if (stats) { 164 kernelStats = stats; 165 } 166#endif 167} 168 169void 170SimpleThread::copyState(ThreadContext *oldContext) 171{ 172 // copy over functional state 173 _status = oldContext->status(); 174 copyArchRegs(oldContext); 175#if !FULL_SYSTEM 176 funcExeInst = oldContext->readFuncExeInst(); 177#endif 178 179 _threadId = oldContext->threadId(); 180 _contextId = oldContext->contextId(); 181} 182 183void 184SimpleThread::serialize(ostream &os) 185{ 186 ThreadState::serialize(os); 187 SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 188 SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 189 _pcState.serialize(os); 190 // thread_num and cpu_id are deterministic from the config 191 192 // 193 // Now must serialize all the ISA dependent state 194 // 195 isa.serialize(cpu, os); 196} 197 198 199void 200SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 201{ 202 ThreadState::unserialize(cp, section); 203 UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 204 UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 205 _pcState.unserialize(cp, section); 206 // thread_num and cpu_id are deterministic from the config 207 208 // 209 // Now must unserialize all the ISA dependent state 210 // 211 isa.unserialize(cpu, cp, section); 212} 213 214#if FULL_SYSTEM 215void 216SimpleThread::dumpFuncProfile() 217{ 218 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 219 profile->dump(tc, *os); 220} 221#endif 222 223void 224SimpleThread::activate(int delay) 225{ 226 if (status() == ThreadContext::Active) 227 return; 228 229 lastActivate = curTick(); 230 231// if (status() == ThreadContext::Unallocated) { 232// cpu->activateWhenReady(_threadId); 233// return; 234// } 235 236 _status = ThreadContext::Active; 237 238 // status() == Suspended 239 cpu->activateContext(_threadId, delay); 240} 241 242void 243SimpleThread::suspend() 244{ 245 if (status() == ThreadContext::Suspended) 246 return; 247 248 lastActivate = curTick(); 249 lastSuspend = curTick(); 250/* 251#if FULL_SYSTEM 252 // Don't change the status from active if there are pending interrupts 253 if (cpu->checkInterrupts()) { 254 assert(status() == ThreadContext::Active); 255 return; 256 } 257#endif 258*/ 259 _status = ThreadContext::Suspended; 260 cpu->suspendContext(_threadId); 261} 262 263 264void 265SimpleThread::halt() 266{ 267 if (status() == ThreadContext::Halted) 268 return; 269 270 _status = ThreadContext::Halted; 271 cpu->haltContext(_threadId); 272} 273 274 275void 276SimpleThread::regStats(const string &name) 277{ 278#if FULL_SYSTEM 279 if (kernelStats) 280 kernelStats->regStats(name + ".kern"); 281#endif 282} 283 284void 285SimpleThread::copyArchRegs(ThreadContext *src_tc) 286{ 287 TheISA::copyRegs(src_tc, tc); 288} 289 290