simple_thread.cc revision 8766:b0773af78423 
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 *          Lisa Hsu
31 *          Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/utility.hh"
38#include "config/the_isa.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/thread_context.hh"
42#include "mem/vport.hh"
43#include "params/BaseCPU.hh"
44
45#if FULL_SYSTEM
46#include "arch/kernel_stats.hh"
47#include "arch/stacktrace.hh"
48#include "base/callback.hh"
49#include "base/cprintf.hh"
50#include "base/output.hh"
51#include "base/trace.hh"
52#include "cpu/profile.hh"
53#include "cpu/quiesce_event.hh"
54#include "sim/serialize.hh"
55#include "sim/sim_exit.hh"
56#else
57#include "mem/translating_port.hh"
58#include "sim/process.hh"
59#include "sim/system.hh"
60#endif
61
62using namespace std;
63
64// constructor
65#if !FULL_SYSTEM
66SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
67                           TheISA::TLB *_itb, TheISA::TLB *_dtb)
68    : ThreadState(_cpu, _thread_num, _process),
69      cpu(_cpu), itb(_itb), dtb(_dtb)
70{
71    clearArchRegs();
72    tc = new ProxyThreadContext<SimpleThread>(this);
73}
74#else
75SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
76                           TheISA::TLB *_itb, TheISA::TLB *_dtb,
77                           bool use_kernel_stats)
78    : ThreadState(_cpu, _thread_num, NULL),
79      cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
80
81{
82    tc = new ProxyThreadContext<SimpleThread>(this);
83
84    quiesceEvent = new EndQuiesceEvent(tc);
85
86    clearArchRegs();
87
88    if (cpu->params()->profile) {
89        profile = new FunctionProfile(system->kernelSymtab);
90        Callback *cb =
91            new MakeCallback<SimpleThread,
92            &SimpleThread::dumpFuncProfile>(this);
93        registerExitCallback(cb);
94    }
95
96    // let's fill with a dummy node for now so we don't get a segfault
97    // on the first cycle when there's no node available.
98    static ProfileNode dummyNode;
99    profileNode = &dummyNode;
100    profilePC = 3;
101
102    if (use_kernel_stats)
103        kernelStats = new TheISA::Kernel::Statistics(system);
104}
105#endif
106
107SimpleThread::SimpleThread()
108    : ThreadState(NULL, -1, NULL)
109{
110    tc = new ProxyThreadContext<SimpleThread>(this);
111}
112
113SimpleThread::~SimpleThread()
114{
115    delete physPort;
116    delete virtPort;
117    delete tc;
118}
119
120void
121SimpleThread::takeOverFrom(ThreadContext *oldContext)
122{
123    // some things should already be set up
124#if FULL_SYSTEM
125    assert(system == oldContext->getSystemPtr());
126#else
127    assert(process == oldContext->getProcessPtr());
128#endif
129
130    copyState(oldContext);
131#if FULL_SYSTEM
132    EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
133    if (quiesce) {
134        // Point the quiesce event's TC at this TC so that it wakes up
135        // the proper CPU.
136        quiesce->tc = tc;
137    }
138    if (quiesceEvent) {
139        quiesceEvent->tc = tc;
140    }
141
142    TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
143    if (stats) {
144        kernelStats = stats;
145    }
146#endif
147
148    storeCondFailures = 0;
149
150    oldContext->setStatus(ThreadContext::Halted);
151}
152
153void
154SimpleThread::copyTC(ThreadContext *context)
155{
156    copyState(context);
157
158#if FULL_SYSTEM
159    EndQuiesceEvent *quiesce = context->getQuiesceEvent();
160    if (quiesce) {
161        quiesceEvent = quiesce;
162    }
163    TheISA::Kernel::Statistics *stats = context->getKernelStats();
164    if (stats) {
165        kernelStats = stats;
166    }
167#endif
168}
169
170void
171SimpleThread::copyState(ThreadContext *oldContext)
172{
173    // copy over functional state
174    _status = oldContext->status();
175    copyArchRegs(oldContext);
176#if !FULL_SYSTEM
177    funcExeInst = oldContext->readFuncExeInst();
178#endif
179
180    _threadId = oldContext->threadId();
181    _contextId = oldContext->contextId();
182}
183
184void
185SimpleThread::serialize(ostream &os)
186{
187    ThreadState::serialize(os);
188    SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
189    SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
190    _pcState.serialize(os);
191    // thread_num and cpu_id are deterministic from the config
192
193    //
194    // Now must serialize all the ISA dependent state
195    //
196    isa.serialize(cpu, os);
197}
198
199
200void
201SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
202{
203    ThreadState::unserialize(cp, section);
204    UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
205    UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
206    _pcState.unserialize(cp, section);
207    // thread_num and cpu_id are deterministic from the config
208
209    //
210    // Now must unserialize all the ISA dependent state
211    //
212    isa.unserialize(cpu, cp, section);
213}
214
215#if FULL_SYSTEM
216void
217SimpleThread::dumpFuncProfile()
218{
219    std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
220    profile->dump(tc, *os);
221}
222#endif
223
224void
225SimpleThread::activate(int delay)
226{
227    if (status() == ThreadContext::Active)
228        return;
229
230    lastActivate = curTick();
231
232//    if (status() == ThreadContext::Unallocated) {
233//      cpu->activateWhenReady(_threadId);
234//      return;
235//   }
236
237    _status = ThreadContext::Active;
238
239    // status() == Suspended
240    cpu->activateContext(_threadId, delay);
241}
242
243void
244SimpleThread::suspend()
245{
246    if (status() == ThreadContext::Suspended)
247        return;
248
249    lastActivate = curTick();
250    lastSuspend = curTick();
251/*
252#if FULL_SYSTEM
253    // Don't change the status from active if there are pending interrupts
254    if (cpu->checkInterrupts()) {
255        assert(status() == ThreadContext::Active);
256        return;
257    }
258#endif
259*/
260    _status = ThreadContext::Suspended;
261    cpu->suspendContext(_threadId);
262}
263
264
265void
266SimpleThread::halt()
267{
268    if (status() == ThreadContext::Halted)
269        return;
270
271    _status = ThreadContext::Halted;
272    cpu->haltContext(_threadId);
273}
274
275
276void
277SimpleThread::regStats(const string &name)
278{
279#if FULL_SYSTEM
280    if (kernelStats)
281        kernelStats->regStats(name + ".kern");
282#endif
283}
284
285void
286SimpleThread::copyArchRegs(ThreadContext *src_tc)
287{
288    TheISA::copyRegs(src_tc, tc);
289}
290
291