simple_thread.cc revision 7823:dac01f14f20f
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 * Lisa Hsu 31 * Kevin Lim 32 */ 33 34#include <string> 35 36#include "arch/isa_traits.hh" 37#include "arch/utility.hh" 38#include "config/the_isa.hh" 39#include "cpu/base.hh" 40#include "cpu/simple_thread.hh" 41#include "cpu/thread_context.hh" 42#include "params/BaseCPU.hh" 43 44#if FULL_SYSTEM 45#include "arch/kernel_stats.hh" 46#include "arch/stacktrace.hh" 47#include "base/callback.hh" 48#include "base/cprintf.hh" 49#include "base/output.hh" 50#include "base/trace.hh" 51#include "cpu/profile.hh" 52#include "cpu/quiesce_event.hh" 53#include "mem/vport.hh" 54#include "sim/serialize.hh" 55#include "sim/sim_exit.hh" 56#else 57#include "mem/translating_port.hh" 58#include "sim/process.hh" 59#include "sim/system.hh" 60#endif 61 62using namespace std; 63 64// constructor 65#if FULL_SYSTEM 66SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 67 TheISA::TLB *_itb, TheISA::TLB *_dtb, 68 bool use_kernel_stats) 69 : ThreadState(_cpu, _thread_num), 70 cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) 71 72{ 73 tc = new ProxyThreadContext<SimpleThread>(this); 74 75 quiesceEvent = new EndQuiesceEvent(tc); 76 77 clearArchRegs(); 78 79 if (cpu->params()->profile) { 80 profile = new FunctionProfile(system->kernelSymtab); 81 Callback *cb = 82 new MakeCallback<SimpleThread, 83 &SimpleThread::dumpFuncProfile>(this); 84 registerExitCallback(cb); 85 } 86 87 // let's fill with a dummy node for now so we don't get a segfault 88 // on the first cycle when there's no node available. 89 static ProfileNode dummyNode; 90 profileNode = &dummyNode; 91 profilePC = 3; 92 93 if (use_kernel_stats) 94 kernelStats = new TheISA::Kernel::Statistics(system); 95} 96#else 97SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 98 TheISA::TLB *_itb, TheISA::TLB *_dtb) 99 : ThreadState(_cpu, _thread_num, _process), 100 cpu(_cpu), itb(_itb), dtb(_dtb) 101{ 102 clearArchRegs(); 103 tc = new ProxyThreadContext<SimpleThread>(this); 104} 105 106#endif 107 108SimpleThread::SimpleThread() 109#if FULL_SYSTEM 110 : ThreadState(NULL, -1) 111#else 112 : ThreadState(NULL, -1, NULL) 113#endif 114{ 115 tc = new ProxyThreadContext<SimpleThread>(this); 116} 117 118SimpleThread::~SimpleThread() 119{ 120#if FULL_SYSTEM 121 delete physPort; 122 delete virtPort; 123#endif 124 delete tc; 125} 126 127void 128SimpleThread::takeOverFrom(ThreadContext *oldContext) 129{ 130 // some things should already be set up 131#if FULL_SYSTEM 132 assert(system == oldContext->getSystemPtr()); 133#else 134 assert(process == oldContext->getProcessPtr()); 135#endif 136 137 copyState(oldContext); 138#if FULL_SYSTEM 139 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 140 if (quiesce) { 141 // Point the quiesce event's TC at this TC so that it wakes up 142 // the proper CPU. 143 quiesce->tc = tc; 144 } 145 if (quiesceEvent) { 146 quiesceEvent->tc = tc; 147 } 148 149 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 150 if (stats) { 151 kernelStats = stats; 152 } 153#endif 154 155 storeCondFailures = 0; 156 157 oldContext->setStatus(ThreadContext::Halted); 158} 159 160void 161SimpleThread::copyTC(ThreadContext *context) 162{ 163 copyState(context); 164 165#if FULL_SYSTEM 166 EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 167 if (quiesce) { 168 quiesceEvent = quiesce; 169 } 170 TheISA::Kernel::Statistics *stats = context->getKernelStats(); 171 if (stats) { 172 kernelStats = stats; 173 } 174#endif 175} 176 177void 178SimpleThread::copyState(ThreadContext *oldContext) 179{ 180 // copy over functional state 181 _status = oldContext->status(); 182 copyArchRegs(oldContext); 183#if !FULL_SYSTEM 184 funcExeInst = oldContext->readFuncExeInst(); 185#endif 186 187 _threadId = oldContext->threadId(); 188 _contextId = oldContext->contextId(); 189} 190 191void 192SimpleThread::serialize(ostream &os) 193{ 194 ThreadState::serialize(os); 195 SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 196 SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 197 _pcState.serialize(os); 198 // thread_num and cpu_id are deterministic from the config 199 200 // 201 // Now must serialize all the ISA dependent state 202 // 203 isa.serialize(cpu, os); 204} 205 206 207void 208SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 209{ 210 ThreadState::unserialize(cp, section); 211 UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 212 UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 213 _pcState.unserialize(cp, section); 214 // thread_num and cpu_id are deterministic from the config 215 216 // 217 // Now must unserialize all the ISA dependent state 218 // 219 isa.unserialize(cpu, cp, section); 220} 221 222#if FULL_SYSTEM 223void 224SimpleThread::dumpFuncProfile() 225{ 226 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 227 profile->dump(tc, *os); 228} 229#endif 230 231void 232SimpleThread::activate(int delay) 233{ 234 if (status() == ThreadContext::Active) 235 return; 236 237 lastActivate = curTick(); 238 239// if (status() == ThreadContext::Unallocated) { 240// cpu->activateWhenReady(_threadId); 241// return; 242// } 243 244 _status = ThreadContext::Active; 245 246 // status() == Suspended 247 cpu->activateContext(_threadId, delay); 248} 249 250void 251SimpleThread::suspend() 252{ 253 if (status() == ThreadContext::Suspended) 254 return; 255 256 lastActivate = curTick(); 257 lastSuspend = curTick(); 258/* 259#if FULL_SYSTEM 260 // Don't change the status from active if there are pending interrupts 261 if (cpu->checkInterrupts()) { 262 assert(status() == ThreadContext::Active); 263 return; 264 } 265#endif 266*/ 267 _status = ThreadContext::Suspended; 268 cpu->suspendContext(_threadId); 269} 270 271 272void 273SimpleThread::halt() 274{ 275 if (status() == ThreadContext::Halted) 276 return; 277 278 _status = ThreadContext::Halted; 279 cpu->haltContext(_threadId); 280} 281 282 283void 284SimpleThread::regStats(const string &name) 285{ 286#if FULL_SYSTEM 287 if (kernelStats) 288 kernelStats->regStats(name + ".kern"); 289#endif 290} 291 292void 293SimpleThread::copyArchRegs(ThreadContext *src_tc) 294{ 295 TheISA::copyRegs(src_tc, tc); 296} 297 298