simple_thread.cc revision 9377
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 373565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 385529Snate@binkert.org#include "arch/stacktrace.hh" 398777Sgblack@eecs.umich.edu#include "arch/utility.hh" 401917SN/A#include "base/callback.hh" 411070SN/A#include "base/cprintf.hh" 421917SN/A#include "base/output.hh" 432188SN/A#include "base/trace.hh" 448777Sgblack@eecs.umich.edu#include "config/the_isa.hh" 458777Sgblack@eecs.umich.edu#include "cpu/base.hh" 461917SN/A#include "cpu/profile.hh" 472290SN/A#include "cpu/quiesce_event.hh" 488777Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh" 498777Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 508706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 518799Sgblack@eecs.umich.edu#include "mem/se_translating_port_proxy.hh" 528809Sgblack@eecs.umich.edu#include "params/BaseCPU.hh" 538793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 548777Sgblack@eecs.umich.edu#include "sim/process.hh" 551070SN/A#include "sim/serialize.hh" 561917SN/A#include "sim/sim_exit.hh" 572519SN/A#include "sim/system.hh" 582SN/A 592SN/Ausing namespace std; 602SN/A 612SN/A// constructor 628820Sgblack@eecs.umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 638820Sgblack@eecs.umich.edu Process *_process, TheISA::TLB *_itb, 648820Sgblack@eecs.umich.edu TheISA::TLB *_dtb) 658820Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, _process), system(_sys), itb(_itb), 669377Sgblack@eecs.umich.edu dtb(_dtb) 678766Sgblack@eecs.umich.edu{ 688766Sgblack@eecs.umich.edu clearArchRegs(); 698766Sgblack@eecs.umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 708766Sgblack@eecs.umich.edu} 719377Sgblack@eecs.umich.edu 722683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 736022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 742683Sktlim@umich.edu bool use_kernel_stats) 759377Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb) 762SN/A{ 772683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 782190SN/A 792680SN/A quiesceEvent = new EndQuiesceEvent(tc); 802290SN/A 816316Sgblack@eecs.umich.edu clearArchRegs(); 821917SN/A 838735Sandreas.hanson@arm.com if (baseCpu->params()->profile) { 841982SN/A profile = new FunctionProfile(system->kernelSymtab); 851917SN/A Callback *cb = 862683Sktlim@umich.edu new MakeCallback<SimpleThread, 872683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 881917SN/A registerExitCallback(cb); 891917SN/A } 901917SN/A 911917SN/A // let's fill with a dummy node for now so we don't get a segfault 921917SN/A // on the first cycle when there's no node available. 931917SN/A static ProfileNode dummyNode; 941917SN/A profileNode = &dummyNode; 951917SN/A profilePC = 3; 962521SN/A 975482Snate@binkert.org if (use_kernel_stats) 983548Sgblack@eecs.umich.edu kernelStats = new TheISA::Kernel::Statistics(system); 992SN/A} 1002862Sktlim@umich.edu 1012864Sktlim@umich.eduSimpleThread::SimpleThread() 1029377Sgblack@eecs.umich.edu : ThreadState(NULL, -1, NULL) 1032190SN/A{ 1042683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1052190SN/A} 1062190SN/A 1072683Sktlim@umich.eduSimpleThread::~SimpleThread() 1081070SN/A{ 1092680SN/A delete tc; 1101070SN/A} 1111070SN/A 1121917SN/Avoid 1132683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 114180SN/A{ 115180SN/A // some things should already be set up 1168793Sgblack@eecs.umich.edu if (FullSystem) 1178793Sgblack@eecs.umich.edu assert(system == oldContext->getSystemPtr()); 1182235SN/A assert(process == oldContext->getProcessPtr()); 119180SN/A 1202862Sktlim@umich.edu copyState(oldContext); 1218793Sgblack@eecs.umich.edu if (FullSystem) { 1228793Sgblack@eecs.umich.edu EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1238793Sgblack@eecs.umich.edu if (quiesce) { 1248793Sgblack@eecs.umich.edu // Point the quiesce event's TC at this TC so that it wakes up 1258793Sgblack@eecs.umich.edu // the proper CPU. 1268793Sgblack@eecs.umich.edu quiesce->tc = tc; 1278793Sgblack@eecs.umich.edu } 1288793Sgblack@eecs.umich.edu if (quiesceEvent) { 1298793Sgblack@eecs.umich.edu quiesceEvent->tc = tc; 1308793Sgblack@eecs.umich.edu } 1318793Sgblack@eecs.umich.edu 1328793Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1338793Sgblack@eecs.umich.edu if (stats) { 1348793Sgblack@eecs.umich.edu kernelStats = stats; 1358793Sgblack@eecs.umich.edu } 1362313SN/A } 137180SN/A 138180SN/A storeCondFailures = 0; 139180SN/A 1406029Ssteve.reinhardt@amd.com oldContext->setStatus(ThreadContext::Halted); 141180SN/A} 142180SN/A 1432SN/Avoid 1442864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1452864Sktlim@umich.edu{ 1462864Sktlim@umich.edu copyState(context); 1472864Sktlim@umich.edu 1488793Sgblack@eecs.umich.edu if (FullSystem) { 1498793Sgblack@eecs.umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1508793Sgblack@eecs.umich.edu if (quiesce) { 1518793Sgblack@eecs.umich.edu quiesceEvent = quiesce; 1528793Sgblack@eecs.umich.edu } 1538793Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1548793Sgblack@eecs.umich.edu if (stats) { 1558793Sgblack@eecs.umich.edu kernelStats = stats; 1568793Sgblack@eecs.umich.edu } 1572864Sktlim@umich.edu } 1582864Sktlim@umich.edu} 1592864Sktlim@umich.edu 1602864Sktlim@umich.eduvoid 1612862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1622862Sktlim@umich.edu{ 1632862Sktlim@umich.edu // copy over functional state 1642862Sktlim@umich.edu _status = oldContext->status(); 1652862Sktlim@umich.edu copyArchRegs(oldContext); 1668793Sgblack@eecs.umich.edu if (FullSystem) 1678793Sgblack@eecs.umich.edu funcExeInst = oldContext->readFuncExeInst(); 1685714Shsul@eecs.umich.edu 1695715Shsul@eecs.umich.edu _threadId = oldContext->threadId(); 1705714Shsul@eecs.umich.edu _contextId = oldContext->contextId(); 1712862Sktlim@umich.edu} 1722862Sktlim@umich.edu 1732862Sktlim@umich.eduvoid 1742683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 175217SN/A{ 1762862Sktlim@umich.edu ThreadState::serialize(os); 1776315Sgblack@eecs.umich.edu SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 1786316Sgblack@eecs.umich.edu SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 1797720Sgblack@eecs.umich.edu _pcState.serialize(os); 180223SN/A // thread_num and cpu_id are deterministic from the config 1816677SBrad.Beckmann@amd.com 1826677SBrad.Beckmann@amd.com // 1836677SBrad.Beckmann@amd.com // Now must serialize all the ISA dependent state 1846677SBrad.Beckmann@amd.com // 1858735Sandreas.hanson@arm.com isa.serialize(baseCpu, os); 186217SN/A} 187217SN/A 188217SN/A 189217SN/Avoid 1902683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 191217SN/A{ 1922862Sktlim@umich.edu ThreadState::unserialize(cp, section); 1936315Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 1946316Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 1957720Sgblack@eecs.umich.edu _pcState.unserialize(cp, section); 196223SN/A // thread_num and cpu_id are deterministic from the config 1976677SBrad.Beckmann@amd.com 1986677SBrad.Beckmann@amd.com // 1996677SBrad.Beckmann@amd.com // Now must unserialize all the ISA dependent state 2006677SBrad.Beckmann@amd.com // 2018735Sandreas.hanson@arm.com isa.unserialize(baseCpu, cp, section); 202217SN/A} 203217SN/A 2042683Sktlim@umich.eduvoid 2052683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2062683Sktlim@umich.edu{ 2078735Sandreas.hanson@arm.com std::ostream *os = simout.create(csprintf("profile.%s.dat", 2088735Sandreas.hanson@arm.com baseCpu->name())); 2092683Sktlim@umich.edu profile->dump(tc, *os); 2102683Sktlim@umich.edu} 211217SN/A 212217SN/Avoid 2139180Sandreas.hansson@arm.comSimpleThread::activate(Cycles delay) 2142SN/A{ 2152680SN/A if (status() == ThreadContext::Active) 2162SN/A return; 2172SN/A 2187823Ssteve.reinhardt@amd.com lastActivate = curTick(); 2192188SN/A 2204400Srdreslin@umich.edu// if (status() == ThreadContext::Unallocated) { 2215715Shsul@eecs.umich.edu// cpu->activateWhenReady(_threadId); 2225543Ssaidi@eecs.umich.edu// return; 2234400Srdreslin@umich.edu// } 2242290SN/A 2252680SN/A _status = ThreadContext::Active; 2262290SN/A 2272290SN/A // status() == Suspended 2288735Sandreas.hanson@arm.com baseCpu->activateContext(_threadId, delay); 229393SN/A} 230393SN/A 231393SN/Avoid 2322683Sktlim@umich.eduSimpleThread::suspend() 233393SN/A{ 2342680SN/A if (status() == ThreadContext::Suspended) 235393SN/A return; 236393SN/A 2377823Ssteve.reinhardt@amd.com lastActivate = curTick(); 2387823Ssteve.reinhardt@amd.com lastSuspend = curTick(); 2392680SN/A _status = ThreadContext::Suspended; 2408735Sandreas.hanson@arm.com baseCpu->suspendContext(_threadId); 2412SN/A} 2422SN/A 243393SN/A 244393SN/Avoid 2452683Sktlim@umich.eduSimpleThread::halt() 246393SN/A{ 2472680SN/A if (status() == ThreadContext::Halted) 248393SN/A return; 249393SN/A 2502680SN/A _status = ThreadContext::Halted; 2518735Sandreas.hanson@arm.com baseCpu->haltContext(_threadId); 252393SN/A} 253393SN/A 254393SN/A 255393SN/Avoid 2562683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2572SN/A{ 2588793Sgblack@eecs.umich.edu if (FullSystem && kernelStats) 2592341SN/A kernelStats->regStats(name + ".kern"); 2602SN/A} 261716SN/A 262716SN/Avoid 2632683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2642190SN/A{ 2652680SN/A TheISA::copyRegs(src_tc, tc); 2662190SN/A} 2672190SN/A 268