simple_thread.cc revision 8766
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 377680Sgblack@eecs.umich.edu#include "arch/utility.hh" 386658Snate@binkert.org#include "config/the_isa.hh" 391717SN/A#include "cpu/base.hh" 402683Sktlim@umich.edu#include "cpu/simple_thread.hh" 412680SN/A#include "cpu/thread_context.hh" 428761Sgblack@eecs.umich.edu#include "mem/vport.hh" 435529Snate@binkert.org#include "params/BaseCPU.hh" 442SN/A 451858SN/A#if FULL_SYSTEM 463565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 475529Snate@binkert.org#include "arch/stacktrace.hh" 481917SN/A#include "base/callback.hh" 491070SN/A#include "base/cprintf.hh" 501917SN/A#include "base/output.hh" 512188SN/A#include "base/trace.hh" 521917SN/A#include "cpu/profile.hh" 532290SN/A#include "cpu/quiesce_event.hh" 541070SN/A#include "sim/serialize.hh" 551917SN/A#include "sim/sim_exit.hh" 562SN/A#else 575529Snate@binkert.org#include "mem/translating_port.hh" 58360SN/A#include "sim/process.hh" 592519SN/A#include "sim/system.hh" 602SN/A#endif 612SN/A 622SN/Ausing namespace std; 632SN/A 642SN/A// constructor 658766Sgblack@eecs.umich.edu#if !FULL_SYSTEM 668766Sgblack@eecs.umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 678766Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb) 688766Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, _process), 698766Sgblack@eecs.umich.edu cpu(_cpu), itb(_itb), dtb(_dtb) 708766Sgblack@eecs.umich.edu{ 718766Sgblack@eecs.umich.edu clearArchRegs(); 728766Sgblack@eecs.umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 738766Sgblack@eecs.umich.edu} 748766Sgblack@eecs.umich.edu#else 752683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 766022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 772683Sktlim@umich.edu bool use_kernel_stats) 788766Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, NULL), 796324Sgblack@eecs.umich.edu cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) 802521SN/A 812SN/A{ 822683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 832190SN/A 842680SN/A quiesceEvent = new EndQuiesceEvent(tc); 852290SN/A 866316Sgblack@eecs.umich.edu clearArchRegs(); 871917SN/A 885529Snate@binkert.org if (cpu->params()->profile) { 891982SN/A profile = new FunctionProfile(system->kernelSymtab); 901917SN/A Callback *cb = 912683Sktlim@umich.edu new MakeCallback<SimpleThread, 922683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 931917SN/A registerExitCallback(cb); 941917SN/A } 951917SN/A 961917SN/A // let's fill with a dummy node for now so we don't get a segfault 971917SN/A // on the first cycle when there's no node available. 981917SN/A static ProfileNode dummyNode; 991917SN/A profileNode = &dummyNode; 1001917SN/A profilePC = 3; 1012521SN/A 1025482Snate@binkert.org if (use_kernel_stats) 1033548Sgblack@eecs.umich.edu kernelStats = new TheISA::Kernel::Statistics(system); 1042SN/A} 1052862Sktlim@umich.edu#endif 1062862Sktlim@umich.edu 1072864Sktlim@umich.eduSimpleThread::SimpleThread() 1086331Sgblack@eecs.umich.edu : ThreadState(NULL, -1, NULL) 1092190SN/A{ 1102683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1112190SN/A} 1122190SN/A 1132683Sktlim@umich.eduSimpleThread::~SimpleThread() 1141070SN/A{ 1158754Sgblack@eecs.umich.edu delete physPort; 1163486Sktlim@umich.edu delete virtPort; 1172680SN/A delete tc; 1181070SN/A} 1191070SN/A 1201917SN/Avoid 1212683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 122180SN/A{ 123180SN/A // some things should already be set up 1241858SN/A#if FULL_SYSTEM 1252235SN/A assert(system == oldContext->getSystemPtr()); 126180SN/A#else 1272235SN/A assert(process == oldContext->getProcessPtr()); 128180SN/A#endif 129180SN/A 1302862Sktlim@umich.edu copyState(oldContext); 1312862Sktlim@umich.edu#if FULL_SYSTEM 1322313SN/A EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1332313SN/A if (quiesce) { 1342680SN/A // Point the quiesce event's TC at this TC so that it wakes up 1352313SN/A // the proper CPU. 1362680SN/A quiesce->tc = tc; 1372313SN/A } 1382313SN/A if (quiesceEvent) { 1392680SN/A quiesceEvent->tc = tc; 1402313SN/A } 1412361SN/A 1423548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1432361SN/A if (stats) { 1442361SN/A kernelStats = stats; 1452361SN/A } 1462235SN/A#endif 147180SN/A 148180SN/A storeCondFailures = 0; 149180SN/A 1506029Ssteve.reinhardt@amd.com oldContext->setStatus(ThreadContext::Halted); 151180SN/A} 152180SN/A 1532SN/Avoid 1542864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1552864Sktlim@umich.edu{ 1562864Sktlim@umich.edu copyState(context); 1572864Sktlim@umich.edu 1582864Sktlim@umich.edu#if FULL_SYSTEM 1592864Sktlim@umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1602864Sktlim@umich.edu if (quiesce) { 1612864Sktlim@umich.edu quiesceEvent = quiesce; 1622864Sktlim@umich.edu } 1633548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1642864Sktlim@umich.edu if (stats) { 1652864Sktlim@umich.edu kernelStats = stats; 1662864Sktlim@umich.edu } 1672864Sktlim@umich.edu#endif 1682864Sktlim@umich.edu} 1692864Sktlim@umich.edu 1702864Sktlim@umich.eduvoid 1712862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1722862Sktlim@umich.edu{ 1732862Sktlim@umich.edu // copy over functional state 1742862Sktlim@umich.edu _status = oldContext->status(); 1752862Sktlim@umich.edu copyArchRegs(oldContext); 1762862Sktlim@umich.edu#if !FULL_SYSTEM 1772862Sktlim@umich.edu funcExeInst = oldContext->readFuncExeInst(); 1782862Sktlim@umich.edu#endif 1795714Shsul@eecs.umich.edu 1805715Shsul@eecs.umich.edu _threadId = oldContext->threadId(); 1815714Shsul@eecs.umich.edu _contextId = oldContext->contextId(); 1822862Sktlim@umich.edu} 1832862Sktlim@umich.edu 1842862Sktlim@umich.eduvoid 1852683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 186217SN/A{ 1872862Sktlim@umich.edu ThreadState::serialize(os); 1886315Sgblack@eecs.umich.edu SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 1896316Sgblack@eecs.umich.edu SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 1907720Sgblack@eecs.umich.edu _pcState.serialize(os); 191223SN/A // thread_num and cpu_id are deterministic from the config 1926677SBrad.Beckmann@amd.com 1936677SBrad.Beckmann@amd.com // 1946677SBrad.Beckmann@amd.com // Now must serialize all the ISA dependent state 1956677SBrad.Beckmann@amd.com // 1966678Sgblack@eecs.umich.edu isa.serialize(cpu, os); 197217SN/A} 198217SN/A 199217SN/A 200217SN/Avoid 2012683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 202217SN/A{ 2032862Sktlim@umich.edu ThreadState::unserialize(cp, section); 2046315Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 2056316Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 2067720Sgblack@eecs.umich.edu _pcState.unserialize(cp, section); 207223SN/A // thread_num and cpu_id are deterministic from the config 2086677SBrad.Beckmann@amd.com 2096677SBrad.Beckmann@amd.com // 2106677SBrad.Beckmann@amd.com // Now must unserialize all the ISA dependent state 2116677SBrad.Beckmann@amd.com // 2126678Sgblack@eecs.umich.edu isa.unserialize(cpu, cp, section); 213217SN/A} 214217SN/A 2152683Sktlim@umich.edu#if FULL_SYSTEM 2162683Sktlim@umich.eduvoid 2172683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2182683Sktlim@umich.edu{ 2192683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2202683Sktlim@umich.edu profile->dump(tc, *os); 2212683Sktlim@umich.edu} 2222683Sktlim@umich.edu#endif 223217SN/A 224217SN/Avoid 2252683Sktlim@umich.eduSimpleThread::activate(int delay) 2262SN/A{ 2272680SN/A if (status() == ThreadContext::Active) 2282SN/A return; 2292SN/A 2307823Ssteve.reinhardt@amd.com lastActivate = curTick(); 2312188SN/A 2324400Srdreslin@umich.edu// if (status() == ThreadContext::Unallocated) { 2335715Shsul@eecs.umich.edu// cpu->activateWhenReady(_threadId); 2345543Ssaidi@eecs.umich.edu// return; 2354400Srdreslin@umich.edu// } 2362290SN/A 2372680SN/A _status = ThreadContext::Active; 2382290SN/A 2392290SN/A // status() == Suspended 2405715Shsul@eecs.umich.edu cpu->activateContext(_threadId, delay); 241393SN/A} 242393SN/A 243393SN/Avoid 2442683Sktlim@umich.eduSimpleThread::suspend() 245393SN/A{ 2462680SN/A if (status() == ThreadContext::Suspended) 247393SN/A return; 248393SN/A 2497823Ssteve.reinhardt@amd.com lastActivate = curTick(); 2507823Ssteve.reinhardt@amd.com lastSuspend = curTick(); 2512188SN/A/* 2521858SN/A#if FULL_SYSTEM 2532SN/A // Don't change the status from active if there are pending interrupts 2545704Snate@binkert.org if (cpu->checkInterrupts()) { 2552680SN/A assert(status() == ThreadContext::Active); 2562SN/A return; 2572SN/A } 2582SN/A#endif 2592188SN/A*/ 2602680SN/A _status = ThreadContext::Suspended; 2615715Shsul@eecs.umich.edu cpu->suspendContext(_threadId); 2622SN/A} 2632SN/A 264393SN/A 265393SN/Avoid 2662683Sktlim@umich.eduSimpleThread::halt() 267393SN/A{ 2682680SN/A if (status() == ThreadContext::Halted) 269393SN/A return; 270393SN/A 2712680SN/A _status = ThreadContext::Halted; 2725715Shsul@eecs.umich.edu cpu->haltContext(_threadId); 273393SN/A} 274393SN/A 275393SN/A 276393SN/Avoid 2772683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2782SN/A{ 2792330SN/A#if FULL_SYSTEM 2802341SN/A if (kernelStats) 2812341SN/A kernelStats->regStats(name + ".kern"); 2822330SN/A#endif 2832SN/A} 284716SN/A 285716SN/Avoid 2862683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2872190SN/A{ 2882680SN/A TheISA::copyRegs(src_tc, tc); 2892190SN/A} 2902190SN/A 291