simple_thread.cc revision 8706
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 377680Sgblack@eecs.umich.edu#include "arch/utility.hh" 386658Snate@binkert.org#include "config/the_isa.hh" 391717SN/A#include "cpu/base.hh" 402683Sktlim@umich.edu#include "cpu/simple_thread.hh" 412680SN/A#include "cpu/thread_context.hh" 425529Snate@binkert.org#include "params/BaseCPU.hh" 432SN/A 441858SN/A#if FULL_SYSTEM 453565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 465529Snate@binkert.org#include "arch/stacktrace.hh" 471917SN/A#include "base/callback.hh" 481070SN/A#include "base/cprintf.hh" 491917SN/A#include "base/output.hh" 502188SN/A#include "base/trace.hh" 511917SN/A#include "cpu/profile.hh" 522290SN/A#include "cpu/quiesce_event.hh" 538706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 541070SN/A#include "sim/serialize.hh" 551917SN/A#include "sim/sim_exit.hh" 562SN/A#else 578706Sandreas.hansson@arm.com#include "mem/se_translating_port_proxy.hh" 58360SN/A#include "sim/process.hh" 592519SN/A#include "sim/system.hh" 602SN/A#endif 612SN/A 622SN/Ausing namespace std; 632SN/A 642SN/A// constructor 651858SN/A#if FULL_SYSTEM 662683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 676022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 682683Sktlim@umich.edu bool use_kernel_stats) 696324Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num), 706324Sgblack@eecs.umich.edu cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) 712521SN/A 722SN/A{ 732683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 742190SN/A 752680SN/A quiesceEvent = new EndQuiesceEvent(tc); 762290SN/A 776316Sgblack@eecs.umich.edu clearArchRegs(); 781917SN/A 795529Snate@binkert.org if (cpu->params()->profile) { 801982SN/A profile = new FunctionProfile(system->kernelSymtab); 811917SN/A Callback *cb = 822683Sktlim@umich.edu new MakeCallback<SimpleThread, 832683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 841917SN/A registerExitCallback(cb); 851917SN/A } 861917SN/A 871917SN/A // let's fill with a dummy node for now so we don't get a segfault 881917SN/A // on the first cycle when there's no node available. 891917SN/A static ProfileNode dummyNode; 901917SN/A profileNode = &dummyNode; 911917SN/A profilePC = 3; 922521SN/A 935482Snate@binkert.org if (use_kernel_stats) 943548Sgblack@eecs.umich.edu kernelStats = new TheISA::Kernel::Statistics(system); 952SN/A} 962SN/A#else 974997Sgblack@eecs.umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 986331Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb) 996331Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, _process), 1004997Sgblack@eecs.umich.edu cpu(_cpu), itb(_itb), dtb(_dtb) 1012SN/A{ 1026316Sgblack@eecs.umich.edu clearArchRegs(); 1032683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1042SN/A} 1052190SN/A 1062862Sktlim@umich.edu#endif 1072862Sktlim@umich.edu 1082864Sktlim@umich.eduSimpleThread::SimpleThread() 1092862Sktlim@umich.edu#if FULL_SYSTEM 1105712Shsul@eecs.umich.edu : ThreadState(NULL, -1) 1112862Sktlim@umich.edu#else 1126331Sgblack@eecs.umich.edu : ThreadState(NULL, -1, NULL) 1132862Sktlim@umich.edu#endif 1142190SN/A{ 1152683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1162190SN/A} 1172190SN/A 1182683Sktlim@umich.eduSimpleThread::~SimpleThread() 1191070SN/A{ 1202680SN/A delete tc; 1211070SN/A} 1221070SN/A 1231917SN/Avoid 1242683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 125180SN/A{ 126180SN/A // some things should already be set up 1271858SN/A#if FULL_SYSTEM 1282235SN/A assert(system == oldContext->getSystemPtr()); 129180SN/A#else 1302235SN/A assert(process == oldContext->getProcessPtr()); 131180SN/A#endif 132180SN/A 1332862Sktlim@umich.edu copyState(oldContext); 1342862Sktlim@umich.edu#if FULL_SYSTEM 1352313SN/A EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1362313SN/A if (quiesce) { 1372680SN/A // Point the quiesce event's TC at this TC so that it wakes up 1382313SN/A // the proper CPU. 1392680SN/A quiesce->tc = tc; 1402313SN/A } 1412313SN/A if (quiesceEvent) { 1422680SN/A quiesceEvent->tc = tc; 1432313SN/A } 1442361SN/A 1453548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1462361SN/A if (stats) { 1472361SN/A kernelStats = stats; 1482361SN/A } 1492235SN/A#endif 150180SN/A 151180SN/A storeCondFailures = 0; 152180SN/A 1536029Ssteve.reinhardt@amd.com oldContext->setStatus(ThreadContext::Halted); 154180SN/A} 155180SN/A 1562SN/Avoid 1572864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1582864Sktlim@umich.edu{ 1592864Sktlim@umich.edu copyState(context); 1602864Sktlim@umich.edu 1612864Sktlim@umich.edu#if FULL_SYSTEM 1622864Sktlim@umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1632864Sktlim@umich.edu if (quiesce) { 1642864Sktlim@umich.edu quiesceEvent = quiesce; 1652864Sktlim@umich.edu } 1663548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1672864Sktlim@umich.edu if (stats) { 1682864Sktlim@umich.edu kernelStats = stats; 1692864Sktlim@umich.edu } 1702864Sktlim@umich.edu#endif 1712864Sktlim@umich.edu} 1722864Sktlim@umich.edu 1732864Sktlim@umich.eduvoid 1742862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1752862Sktlim@umich.edu{ 1762862Sktlim@umich.edu // copy over functional state 1772862Sktlim@umich.edu _status = oldContext->status(); 1782862Sktlim@umich.edu copyArchRegs(oldContext); 1792862Sktlim@umich.edu#if !FULL_SYSTEM 1802862Sktlim@umich.edu funcExeInst = oldContext->readFuncExeInst(); 1812862Sktlim@umich.edu#endif 1825714Shsul@eecs.umich.edu 1835715Shsul@eecs.umich.edu _threadId = oldContext->threadId(); 1845714Shsul@eecs.umich.edu _contextId = oldContext->contextId(); 1852862Sktlim@umich.edu} 1862862Sktlim@umich.edu 1872862Sktlim@umich.eduvoid 1882683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 189217SN/A{ 1902862Sktlim@umich.edu ThreadState::serialize(os); 1916315Sgblack@eecs.umich.edu SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 1926316Sgblack@eecs.umich.edu SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 1937720Sgblack@eecs.umich.edu _pcState.serialize(os); 194223SN/A // thread_num and cpu_id are deterministic from the config 1956677SBrad.Beckmann@amd.com 1966677SBrad.Beckmann@amd.com // 1976677SBrad.Beckmann@amd.com // Now must serialize all the ISA dependent state 1986677SBrad.Beckmann@amd.com // 1996678Sgblack@eecs.umich.edu isa.serialize(cpu, os); 200217SN/A} 201217SN/A 202217SN/A 203217SN/Avoid 2042683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 205217SN/A{ 2062862Sktlim@umich.edu ThreadState::unserialize(cp, section); 2076315Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 2086316Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 2097720Sgblack@eecs.umich.edu _pcState.unserialize(cp, section); 210223SN/A // thread_num and cpu_id are deterministic from the config 2116677SBrad.Beckmann@amd.com 2126677SBrad.Beckmann@amd.com // 2136677SBrad.Beckmann@amd.com // Now must unserialize all the ISA dependent state 2146677SBrad.Beckmann@amd.com // 2156678Sgblack@eecs.umich.edu isa.unserialize(cpu, cp, section); 216217SN/A} 217217SN/A 2182683Sktlim@umich.edu#if FULL_SYSTEM 2192683Sktlim@umich.eduvoid 2202683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2212683Sktlim@umich.edu{ 2222683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2232683Sktlim@umich.edu profile->dump(tc, *os); 2242683Sktlim@umich.edu} 2252683Sktlim@umich.edu#endif 226217SN/A 227217SN/Avoid 2282683Sktlim@umich.eduSimpleThread::activate(int delay) 2292SN/A{ 2302680SN/A if (status() == ThreadContext::Active) 2312SN/A return; 2322SN/A 2337823Ssteve.reinhardt@amd.com lastActivate = curTick(); 2342188SN/A 2354400Srdreslin@umich.edu// if (status() == ThreadContext::Unallocated) { 2365715Shsul@eecs.umich.edu// cpu->activateWhenReady(_threadId); 2375543Ssaidi@eecs.umich.edu// return; 2384400Srdreslin@umich.edu// } 2392290SN/A 2402680SN/A _status = ThreadContext::Active; 2412290SN/A 2422290SN/A // status() == Suspended 2435715Shsul@eecs.umich.edu cpu->activateContext(_threadId, delay); 244393SN/A} 245393SN/A 246393SN/Avoid 2472683Sktlim@umich.eduSimpleThread::suspend() 248393SN/A{ 2492680SN/A if (status() == ThreadContext::Suspended) 250393SN/A return; 251393SN/A 2527823Ssteve.reinhardt@amd.com lastActivate = curTick(); 2537823Ssteve.reinhardt@amd.com lastSuspend = curTick(); 2542188SN/A/* 2551858SN/A#if FULL_SYSTEM 2562SN/A // Don't change the status from active if there are pending interrupts 2575704Snate@binkert.org if (cpu->checkInterrupts()) { 2582680SN/A assert(status() == ThreadContext::Active); 2592SN/A return; 2602SN/A } 2612SN/A#endif 2622188SN/A*/ 2632680SN/A _status = ThreadContext::Suspended; 2645715Shsul@eecs.umich.edu cpu->suspendContext(_threadId); 2652SN/A} 2662SN/A 267393SN/A 268393SN/Avoid 2692683Sktlim@umich.eduSimpleThread::halt() 270393SN/A{ 2712680SN/A if (status() == ThreadContext::Halted) 272393SN/A return; 273393SN/A 2742680SN/A _status = ThreadContext::Halted; 2755715Shsul@eecs.umich.edu cpu->haltContext(_threadId); 276393SN/A} 277393SN/A 278393SN/A 279393SN/Avoid 2802683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2812SN/A{ 2822330SN/A#if FULL_SYSTEM 2832341SN/A if (kernelStats) 2842341SN/A kernelStats->regStats(name + ".kern"); 2852330SN/A#endif 2862SN/A} 287716SN/A 288716SN/Avoid 2892683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2902190SN/A{ 2912680SN/A TheISA::copyRegs(src_tc, tc); 2922190SN/A} 2932190SN/A 294