simple_thread.cc revision 7720
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 377680Sgblack@eecs.umich.edu#include "arch/utility.hh" 386658Snate@binkert.org#include "config/the_isa.hh" 391717SN/A#include "cpu/base.hh" 402683Sktlim@umich.edu#include "cpu/simple_thread.hh" 412680SN/A#include "cpu/thread_context.hh" 425529Snate@binkert.org#include "params/BaseCPU.hh" 432SN/A 441858SN/A#if FULL_SYSTEM 453565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 465529Snate@binkert.org#include "arch/stacktrace.hh" 471917SN/A#include "base/callback.hh" 481070SN/A#include "base/cprintf.hh" 491917SN/A#include "base/output.hh" 502188SN/A#include "base/trace.hh" 511917SN/A#include "cpu/profile.hh" 522290SN/A#include "cpu/quiesce_event.hh" 531070SN/A#include "sim/serialize.hh" 541917SN/A#include "sim/sim_exit.hh" 552SN/A#else 565529Snate@binkert.org#include "mem/translating_port.hh" 57360SN/A#include "sim/process.hh" 582519SN/A#include "sim/system.hh" 592SN/A#endif 602SN/A 612SN/Ausing namespace std; 622SN/A 632SN/A// constructor 641858SN/A#if FULL_SYSTEM 652683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 666022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 672683Sktlim@umich.edu bool use_kernel_stats) 686324Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num), 696324Sgblack@eecs.umich.edu cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) 702521SN/A 712SN/A{ 722683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 732190SN/A 742680SN/A quiesceEvent = new EndQuiesceEvent(tc); 752290SN/A 766316Sgblack@eecs.umich.edu clearArchRegs(); 771917SN/A 785529Snate@binkert.org if (cpu->params()->profile) { 791982SN/A profile = new FunctionProfile(system->kernelSymtab); 801917SN/A Callback *cb = 812683Sktlim@umich.edu new MakeCallback<SimpleThread, 822683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 831917SN/A registerExitCallback(cb); 841917SN/A } 851917SN/A 861917SN/A // let's fill with a dummy node for now so we don't get a segfault 871917SN/A // on the first cycle when there's no node available. 881917SN/A static ProfileNode dummyNode; 891917SN/A profileNode = &dummyNode; 901917SN/A profilePC = 3; 912521SN/A 925482Snate@binkert.org if (use_kernel_stats) 933548Sgblack@eecs.umich.edu kernelStats = new TheISA::Kernel::Statistics(system); 942SN/A} 952SN/A#else 964997Sgblack@eecs.umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 976331Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb) 986331Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, _process), 994997Sgblack@eecs.umich.edu cpu(_cpu), itb(_itb), dtb(_dtb) 1002SN/A{ 1016316Sgblack@eecs.umich.edu clearArchRegs(); 1022683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1032SN/A} 1042190SN/A 1052862Sktlim@umich.edu#endif 1062862Sktlim@umich.edu 1072864Sktlim@umich.eduSimpleThread::SimpleThread() 1082862Sktlim@umich.edu#if FULL_SYSTEM 1095712Shsul@eecs.umich.edu : ThreadState(NULL, -1) 1102862Sktlim@umich.edu#else 1116331Sgblack@eecs.umich.edu : ThreadState(NULL, -1, NULL) 1122862Sktlim@umich.edu#endif 1132190SN/A{ 1142683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1152190SN/A} 1162190SN/A 1172683Sktlim@umich.eduSimpleThread::~SimpleThread() 1181070SN/A{ 1193486Sktlim@umich.edu#if FULL_SYSTEM 1203486Sktlim@umich.edu delete physPort; 1213486Sktlim@umich.edu delete virtPort; 1223486Sktlim@umich.edu#endif 1232680SN/A delete tc; 1241070SN/A} 1251070SN/A 1261917SN/Avoid 1272683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 128180SN/A{ 129180SN/A // some things should already be set up 1301858SN/A#if FULL_SYSTEM 1312235SN/A assert(system == oldContext->getSystemPtr()); 132180SN/A#else 1332235SN/A assert(process == oldContext->getProcessPtr()); 134180SN/A#endif 135180SN/A 1362862Sktlim@umich.edu copyState(oldContext); 1372862Sktlim@umich.edu#if FULL_SYSTEM 1382313SN/A EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1392313SN/A if (quiesce) { 1402680SN/A // Point the quiesce event's TC at this TC so that it wakes up 1412313SN/A // the proper CPU. 1422680SN/A quiesce->tc = tc; 1432313SN/A } 1442313SN/A if (quiesceEvent) { 1452680SN/A quiesceEvent->tc = tc; 1462313SN/A } 1472361SN/A 1483548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1492361SN/A if (stats) { 1502361SN/A kernelStats = stats; 1512361SN/A } 1522235SN/A#endif 153180SN/A 154180SN/A storeCondFailures = 0; 155180SN/A 1566029Ssteve.reinhardt@amd.com oldContext->setStatus(ThreadContext::Halted); 157180SN/A} 158180SN/A 1592SN/Avoid 1602864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1612864Sktlim@umich.edu{ 1622864Sktlim@umich.edu copyState(context); 1632864Sktlim@umich.edu 1642864Sktlim@umich.edu#if FULL_SYSTEM 1652864Sktlim@umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1662864Sktlim@umich.edu if (quiesce) { 1672864Sktlim@umich.edu quiesceEvent = quiesce; 1682864Sktlim@umich.edu } 1693548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1702864Sktlim@umich.edu if (stats) { 1712864Sktlim@umich.edu kernelStats = stats; 1722864Sktlim@umich.edu } 1732864Sktlim@umich.edu#endif 1742864Sktlim@umich.edu} 1752864Sktlim@umich.edu 1762864Sktlim@umich.eduvoid 1772862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1782862Sktlim@umich.edu{ 1792862Sktlim@umich.edu // copy over functional state 1802862Sktlim@umich.edu _status = oldContext->status(); 1812862Sktlim@umich.edu copyArchRegs(oldContext); 1822862Sktlim@umich.edu#if !FULL_SYSTEM 1832862Sktlim@umich.edu funcExeInst = oldContext->readFuncExeInst(); 1842862Sktlim@umich.edu#endif 1855714Shsul@eecs.umich.edu 1865715Shsul@eecs.umich.edu _threadId = oldContext->threadId(); 1875714Shsul@eecs.umich.edu _contextId = oldContext->contextId(); 1882862Sktlim@umich.edu} 1892862Sktlim@umich.edu 1902862Sktlim@umich.eduvoid 1912683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 192217SN/A{ 1932862Sktlim@umich.edu ThreadState::serialize(os); 1946315Sgblack@eecs.umich.edu SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 1956316Sgblack@eecs.umich.edu SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 1967720Sgblack@eecs.umich.edu _pcState.serialize(os); 197223SN/A // thread_num and cpu_id are deterministic from the config 1986677SBrad.Beckmann@amd.com 1996677SBrad.Beckmann@amd.com // 2006677SBrad.Beckmann@amd.com // Now must serialize all the ISA dependent state 2016677SBrad.Beckmann@amd.com // 2026678Sgblack@eecs.umich.edu isa.serialize(cpu, os); 203217SN/A} 204217SN/A 205217SN/A 206217SN/Avoid 2072683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 208217SN/A{ 2092862Sktlim@umich.edu ThreadState::unserialize(cp, section); 2106315Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 2116316Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 2127720Sgblack@eecs.umich.edu _pcState.unserialize(cp, section); 213223SN/A // thread_num and cpu_id are deterministic from the config 2146677SBrad.Beckmann@amd.com 2156677SBrad.Beckmann@amd.com // 2166677SBrad.Beckmann@amd.com // Now must unserialize all the ISA dependent state 2176677SBrad.Beckmann@amd.com // 2186678Sgblack@eecs.umich.edu isa.unserialize(cpu, cp, section); 219217SN/A} 220217SN/A 2212683Sktlim@umich.edu#if FULL_SYSTEM 2222683Sktlim@umich.eduvoid 2232683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2242683Sktlim@umich.edu{ 2252683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2262683Sktlim@umich.edu profile->dump(tc, *os); 2272683Sktlim@umich.edu} 2282683Sktlim@umich.edu#endif 229217SN/A 230217SN/Avoid 2312683Sktlim@umich.eduSimpleThread::activate(int delay) 2322SN/A{ 2332680SN/A if (status() == ThreadContext::Active) 2342SN/A return; 2352SN/A 2362188SN/A lastActivate = curTick; 2372188SN/A 2384400Srdreslin@umich.edu// if (status() == ThreadContext::Unallocated) { 2395715Shsul@eecs.umich.edu// cpu->activateWhenReady(_threadId); 2405543Ssaidi@eecs.umich.edu// return; 2414400Srdreslin@umich.edu// } 2422290SN/A 2432680SN/A _status = ThreadContext::Active; 2442290SN/A 2452290SN/A // status() == Suspended 2465715Shsul@eecs.umich.edu cpu->activateContext(_threadId, delay); 247393SN/A} 248393SN/A 249393SN/Avoid 2502683Sktlim@umich.eduSimpleThread::suspend() 251393SN/A{ 2522680SN/A if (status() == ThreadContext::Suspended) 253393SN/A return; 254393SN/A 2552188SN/A lastActivate = curTick; 2562188SN/A lastSuspend = curTick; 2572188SN/A/* 2581858SN/A#if FULL_SYSTEM 2592SN/A // Don't change the status from active if there are pending interrupts 2605704Snate@binkert.org if (cpu->checkInterrupts()) { 2612680SN/A assert(status() == ThreadContext::Active); 2622SN/A return; 2632SN/A } 2642SN/A#endif 2652188SN/A*/ 2662680SN/A _status = ThreadContext::Suspended; 2675715Shsul@eecs.umich.edu cpu->suspendContext(_threadId); 2682SN/A} 2692SN/A 270393SN/A 271393SN/Avoid 2722683Sktlim@umich.eduSimpleThread::halt() 273393SN/A{ 2742680SN/A if (status() == ThreadContext::Halted) 275393SN/A return; 276393SN/A 2772680SN/A _status = ThreadContext::Halted; 2785715Shsul@eecs.umich.edu cpu->haltContext(_threadId); 279393SN/A} 280393SN/A 281393SN/A 282393SN/Avoid 2832683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2842SN/A{ 2852330SN/A#if FULL_SYSTEM 2862341SN/A if (kernelStats) 2872341SN/A kernelStats->regStats(name + ".kern"); 2882330SN/A#endif 2892SN/A} 290716SN/A 291716SN/Avoid 2922683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2932190SN/A{ 2942680SN/A TheISA::copyRegs(src_tc, tc); 2952190SN/A} 2962190SN/A 297