simple_thread.cc revision 5482
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 371717SN/A#include "cpu/base.hh" 382683Sktlim@umich.edu#include "cpu/simple_thread.hh" 392680SN/A#include "cpu/thread_context.hh" 402SN/A 411858SN/A#if FULL_SYSTEM 423565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 431917SN/A#include "base/callback.hh" 441070SN/A#include "base/cprintf.hh" 451917SN/A#include "base/output.hh" 462188SN/A#include "base/trace.hh" 471917SN/A#include "cpu/profile.hh" 482290SN/A#include "cpu/quiesce_event.hh" 491070SN/A#include "sim/serialize.hh" 501917SN/A#include "sim/sim_exit.hh" 512170SN/A#include "arch/stacktrace.hh" 522SN/A#else 53360SN/A#include "sim/process.hh" 542519SN/A#include "sim/system.hh" 552420SN/A#include "mem/translating_port.hh" 562SN/A#endif 572SN/A 582SN/Ausing namespace std; 592SN/A 602SN/A// constructor 611858SN/A#if FULL_SYSTEM 622683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 633453Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, 642683Sktlim@umich.edu bool use_kernel_stats) 653402Sktlim@umich.edu : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), 662683Sktlim@umich.edu dtb(_dtb) 672521SN/A 682SN/A{ 692683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 702190SN/A 712680SN/A quiesceEvent = new EndQuiesceEvent(tc); 722290SN/A 732526SN/A regs.clear(); 741917SN/A 751917SN/A if (cpu->params->profile) { 761982SN/A profile = new FunctionProfile(system->kernelSymtab); 771917SN/A Callback *cb = 782683Sktlim@umich.edu new MakeCallback<SimpleThread, 792683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 801917SN/A registerExitCallback(cb); 811917SN/A } 821917SN/A 831917SN/A // let's fill with a dummy node for now so we don't get a segfault 841917SN/A // on the first cycle when there's no node available. 851917SN/A static ProfileNode dummyNode; 861917SN/A profileNode = &dummyNode; 871917SN/A profilePC = 3; 882521SN/A 895482Snate@binkert.org if (use_kernel_stats) 903548Sgblack@eecs.umich.edu kernelStats = new TheISA::Kernel::Statistics(system); 912SN/A} 922SN/A#else 934997Sgblack@eecs.umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 944997Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid) 953402Sktlim@umich.edu : ThreadState(_cpu, -1, _thread_num, _process, _asid), 964997Sgblack@eecs.umich.edu cpu(_cpu), itb(_itb), dtb(_dtb) 972SN/A{ 982526SN/A regs.clear(); 992683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1002SN/A} 1012190SN/A 1022862Sktlim@umich.edu#endif 1032862Sktlim@umich.edu 1042864Sktlim@umich.eduSimpleThread::SimpleThread() 1052862Sktlim@umich.edu#if FULL_SYSTEM 1063402Sktlim@umich.edu : ThreadState(NULL, -1, -1) 1072862Sktlim@umich.edu#else 1083402Sktlim@umich.edu : ThreadState(NULL, -1, -1, NULL, -1) 1092862Sktlim@umich.edu#endif 1102190SN/A{ 1112683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1122862Sktlim@umich.edu regs.clear(); 1132190SN/A} 1142190SN/A 1152683Sktlim@umich.eduSimpleThread::~SimpleThread() 1161070SN/A{ 1173486Sktlim@umich.edu#if FULL_SYSTEM 1183486Sktlim@umich.edu delete physPort; 1193486Sktlim@umich.edu delete virtPort; 1203486Sktlim@umich.edu#endif 1212680SN/A delete tc; 1221070SN/A} 1231070SN/A 1241917SN/Avoid 1252683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 126180SN/A{ 127180SN/A // some things should already be set up 1281858SN/A#if FULL_SYSTEM 1292235SN/A assert(system == oldContext->getSystemPtr()); 130180SN/A#else 1312235SN/A assert(process == oldContext->getProcessPtr()); 132180SN/A#endif 133180SN/A 1342862Sktlim@umich.edu copyState(oldContext); 1352862Sktlim@umich.edu#if FULL_SYSTEM 1362313SN/A EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1372313SN/A if (quiesce) { 1382680SN/A // Point the quiesce event's TC at this TC so that it wakes up 1392313SN/A // the proper CPU. 1402680SN/A quiesce->tc = tc; 1412313SN/A } 1422313SN/A if (quiesceEvent) { 1432680SN/A quiesceEvent->tc = tc; 1442313SN/A } 1452361SN/A 1463548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1472361SN/A if (stats) { 1482361SN/A kernelStats = stats; 1492361SN/A } 1502235SN/A#endif 151180SN/A 152180SN/A storeCondFailures = 0; 153180SN/A 1542680SN/A oldContext->setStatus(ThreadContext::Unallocated); 155180SN/A} 156180SN/A 1572SN/Avoid 1582864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1592864Sktlim@umich.edu{ 1602864Sktlim@umich.edu copyState(context); 1612864Sktlim@umich.edu 1622864Sktlim@umich.edu#if FULL_SYSTEM 1632864Sktlim@umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1642864Sktlim@umich.edu if (quiesce) { 1652864Sktlim@umich.edu quiesceEvent = quiesce; 1662864Sktlim@umich.edu } 1673548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1682864Sktlim@umich.edu if (stats) { 1692864Sktlim@umich.edu kernelStats = stats; 1702864Sktlim@umich.edu } 1712864Sktlim@umich.edu#endif 1722864Sktlim@umich.edu} 1732864Sktlim@umich.edu 1742864Sktlim@umich.eduvoid 1752862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1762862Sktlim@umich.edu{ 1772862Sktlim@umich.edu // copy over functional state 1782862Sktlim@umich.edu _status = oldContext->status(); 1792862Sktlim@umich.edu copyArchRegs(oldContext); 1802862Sktlim@umich.edu cpuId = oldContext->readCpuId(); 1812862Sktlim@umich.edu#if !FULL_SYSTEM 1822862Sktlim@umich.edu funcExeInst = oldContext->readFuncExeInst(); 1832862Sktlim@umich.edu#endif 1842915Sktlim@umich.edu inst = oldContext->getInst(); 1852862Sktlim@umich.edu} 1862862Sktlim@umich.edu 1872862Sktlim@umich.eduvoid 1882683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 189217SN/A{ 1902862Sktlim@umich.edu ThreadState::serialize(os); 191223SN/A regs.serialize(os); 192223SN/A // thread_num and cpu_id are deterministic from the config 193217SN/A} 194217SN/A 195217SN/A 196217SN/Avoid 1972683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 198217SN/A{ 1992862Sktlim@umich.edu ThreadState::unserialize(cp, section); 200237SN/A regs.unserialize(cp, section); 201223SN/A // thread_num and cpu_id are deterministic from the config 202217SN/A} 203217SN/A 2042683Sktlim@umich.edu#if FULL_SYSTEM 2052683Sktlim@umich.eduvoid 2062683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2072683Sktlim@umich.edu{ 2082683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2092683Sktlim@umich.edu profile->dump(tc, *os); 2102683Sktlim@umich.edu} 2112683Sktlim@umich.edu#endif 212217SN/A 213217SN/Avoid 2142683Sktlim@umich.eduSimpleThread::activate(int delay) 2152SN/A{ 2162680SN/A if (status() == ThreadContext::Active) 2172SN/A return; 2182SN/A 2192188SN/A lastActivate = curTick; 2202188SN/A 2214400Srdreslin@umich.edu// if (status() == ThreadContext::Unallocated) { 2224400Srdreslin@umich.edu// cpu->activateWhenReady(tid); 2234400Srdreslin@umich.edu// return; 2244400Srdreslin@umich.edu// } 2252290SN/A 2262680SN/A _status = ThreadContext::Active; 2272290SN/A 2282290SN/A // status() == Suspended 2292683Sktlim@umich.edu cpu->activateContext(tid, delay); 230393SN/A} 231393SN/A 232393SN/Avoid 2332683Sktlim@umich.eduSimpleThread::suspend() 234393SN/A{ 2352680SN/A if (status() == ThreadContext::Suspended) 236393SN/A return; 237393SN/A 2382188SN/A lastActivate = curTick; 2392188SN/A lastSuspend = curTick; 2402188SN/A/* 2411858SN/A#if FULL_SYSTEM 2422SN/A // Don't change the status from active if there are pending interrupts 243393SN/A if (cpu->check_interrupts()) { 2442680SN/A assert(status() == ThreadContext::Active); 2452SN/A return; 2462SN/A } 2472SN/A#endif 2482188SN/A*/ 2492680SN/A _status = ThreadContext::Suspended; 2502683Sktlim@umich.edu cpu->suspendContext(tid); 2512SN/A} 2522SN/A 2532SN/Avoid 2542683Sktlim@umich.eduSimpleThread::deallocate() 255393SN/A{ 2562680SN/A if (status() == ThreadContext::Unallocated) 257393SN/A return; 258393SN/A 2592680SN/A _status = ThreadContext::Unallocated; 2602683Sktlim@umich.edu cpu->deallocateContext(tid); 261393SN/A} 262393SN/A 263393SN/Avoid 2642683Sktlim@umich.eduSimpleThread::halt() 265393SN/A{ 2662680SN/A if (status() == ThreadContext::Halted) 267393SN/A return; 268393SN/A 2692680SN/A _status = ThreadContext::Halted; 2702683Sktlim@umich.edu cpu->haltContext(tid); 271393SN/A} 272393SN/A 273393SN/A 274393SN/Avoid 2752683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2762SN/A{ 2772330SN/A#if FULL_SYSTEM 2782341SN/A if (kernelStats) 2792341SN/A kernelStats->regStats(name + ".kern"); 2802330SN/A#endif 2812SN/A} 282716SN/A 283716SN/Avoid 2842683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2852190SN/A{ 2862680SN/A TheISA::copyRegs(src_tc, tc); 2872190SN/A} 2882190SN/A 2892521SN/A#if FULL_SYSTEM 2902521SN/AVirtualPort* 2912683Sktlim@umich.eduSimpleThread::getVirtPort(ThreadContext *src_tc) 2922521SN/A{ 2932680SN/A if (!src_tc) 2942521SN/A return virtPort; 2952521SN/A 2963486Sktlim@umich.edu VirtualPort *vp = new VirtualPort("tc-vport", src_tc); 2973675Sktlim@umich.edu connectToMemFunc(vp); 2982521SN/A return vp; 2992521SN/A} 3002521SN/A 3012521SN/Avoid 3022683Sktlim@umich.eduSimpleThread::delVirtPort(VirtualPort *vp) 3032521SN/A{ 3042684Ssaidi@eecs.umich.edu if (vp != virtPort) { 3054217Ssaidi@eecs.umich.edu vp->removeConn(); 3062684Ssaidi@eecs.umich.edu delete vp; 3072684Ssaidi@eecs.umich.edu } 3082521SN/A} 3092521SN/A 3102521SN/A#endif 3112521SN/A 312