simple_thread.cc revision 3565
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 371717SN/A#include "cpu/base.hh" 382683Sktlim@umich.edu#include "cpu/simple_thread.hh" 392680SN/A#include "cpu/thread_context.hh" 402SN/A 411858SN/A#if FULL_SYSTEM 423565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 431917SN/A#include "base/callback.hh" 441070SN/A#include "base/cprintf.hh" 451917SN/A#include "base/output.hh" 462188SN/A#include "base/trace.hh" 471917SN/A#include "cpu/profile.hh" 482290SN/A#include "cpu/quiesce_event.hh" 491070SN/A#include "sim/serialize.hh" 501917SN/A#include "sim/sim_exit.hh" 512170SN/A#include "arch/stacktrace.hh" 522SN/A#else 53360SN/A#include "sim/process.hh" 542519SN/A#include "sim/system.hh" 552420SN/A#include "mem/translating_port.hh" 562SN/A#endif 572SN/A 582SN/Ausing namespace std; 592SN/A 602SN/A// constructor 611858SN/A#if FULL_SYSTEM 622683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 633453Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, 642683Sktlim@umich.edu bool use_kernel_stats) 653402Sktlim@umich.edu : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), 662683Sktlim@umich.edu dtb(_dtb) 672521SN/A 682SN/A{ 692683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 702190SN/A 712680SN/A quiesceEvent = new EndQuiesceEvent(tc); 722290SN/A 732526SN/A regs.clear(); 741917SN/A 751917SN/A if (cpu->params->profile) { 761982SN/A profile = new FunctionProfile(system->kernelSymtab); 771917SN/A Callback *cb = 782683Sktlim@umich.edu new MakeCallback<SimpleThread, 792683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 801917SN/A registerExitCallback(cb); 811917SN/A } 821917SN/A 831917SN/A // let's fill with a dummy node for now so we don't get a segfault 841917SN/A // on the first cycle when there's no node available. 851917SN/A static ProfileNode dummyNode; 861917SN/A profileNode = &dummyNode; 871917SN/A profilePC = 3; 882521SN/A 892341SN/A if (use_kernel_stats) { 903548Sgblack@eecs.umich.edu kernelStats = new TheISA::Kernel::Statistics(system); 912341SN/A } else { 922341SN/A kernelStats = NULL; 932341SN/A } 942521SN/A Port *mem_port; 952640SN/A physPort = new FunctionalPort(csprintf("%s-%d-funcport", 962683Sktlim@umich.edu cpu->name(), tid)); 972521SN/A mem_port = system->physmem->getPort("functional"); 982521SN/A mem_port->setPeer(physPort); 992521SN/A physPort->setPeer(mem_port); 1002521SN/A 1012640SN/A virtPort = new VirtualPort(csprintf("%s-%d-vport", 1022683Sktlim@umich.edu cpu->name(), tid)); 1032521SN/A mem_port = system->physmem->getPort("functional"); 1042521SN/A mem_port->setPeer(virtPort); 1052521SN/A virtPort->setPeer(mem_port); 1062SN/A} 1072SN/A#else 1082683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, 1093402Sktlim@umich.edu Process *_process, int _asid) 1103402Sktlim@umich.edu : ThreadState(_cpu, -1, _thread_num, _process, _asid), 1112683Sktlim@umich.edu cpu(_cpu) 1122SN/A{ 1132526SN/A regs.clear(); 1142683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1152SN/A} 1162190SN/A 1172862Sktlim@umich.edu#endif 1182862Sktlim@umich.edu 1192864Sktlim@umich.eduSimpleThread::SimpleThread() 1202862Sktlim@umich.edu#if FULL_SYSTEM 1213402Sktlim@umich.edu : ThreadState(NULL, -1, -1) 1222862Sktlim@umich.edu#else 1233402Sktlim@umich.edu : ThreadState(NULL, -1, -1, NULL, -1) 1242862Sktlim@umich.edu#endif 1252190SN/A{ 1262683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1272862Sktlim@umich.edu regs.clear(); 1282190SN/A} 1292190SN/A 1302683Sktlim@umich.eduSimpleThread::~SimpleThread() 1311070SN/A{ 1323486Sktlim@umich.edu#if FULL_SYSTEM 1333486Sktlim@umich.edu delete physPort; 1343486Sktlim@umich.edu delete virtPort; 1353486Sktlim@umich.edu#endif 1362680SN/A delete tc; 1371070SN/A} 1381070SN/A 1391917SN/Avoid 1402683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 141180SN/A{ 142180SN/A // some things should already be set up 1431858SN/A#if FULL_SYSTEM 1442235SN/A assert(system == oldContext->getSystemPtr()); 145180SN/A#else 1462235SN/A assert(process == oldContext->getProcessPtr()); 147180SN/A#endif 148180SN/A 1492862Sktlim@umich.edu copyState(oldContext); 1502862Sktlim@umich.edu#if FULL_SYSTEM 1512313SN/A EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1522313SN/A if (quiesce) { 1532680SN/A // Point the quiesce event's TC at this TC so that it wakes up 1542313SN/A // the proper CPU. 1552680SN/A quiesce->tc = tc; 1562313SN/A } 1572313SN/A if (quiesceEvent) { 1582680SN/A quiesceEvent->tc = tc; 1592313SN/A } 1602361SN/A 1613548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1622361SN/A if (stats) { 1632361SN/A kernelStats = stats; 1642361SN/A } 1652235SN/A#endif 166180SN/A 167180SN/A storeCondFailures = 0; 168180SN/A 1692680SN/A oldContext->setStatus(ThreadContext::Unallocated); 170180SN/A} 171180SN/A 1722SN/Avoid 1732864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1742864Sktlim@umich.edu{ 1752864Sktlim@umich.edu copyState(context); 1762864Sktlim@umich.edu 1772864Sktlim@umich.edu#if FULL_SYSTEM 1782864Sktlim@umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1792864Sktlim@umich.edu if (quiesce) { 1802864Sktlim@umich.edu quiesceEvent = quiesce; 1812864Sktlim@umich.edu } 1823548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1832864Sktlim@umich.edu if (stats) { 1842864Sktlim@umich.edu kernelStats = stats; 1852864Sktlim@umich.edu } 1862864Sktlim@umich.edu#endif 1872864Sktlim@umich.edu} 1882864Sktlim@umich.edu 1892864Sktlim@umich.eduvoid 1902862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1912862Sktlim@umich.edu{ 1922862Sktlim@umich.edu // copy over functional state 1932862Sktlim@umich.edu _status = oldContext->status(); 1942862Sktlim@umich.edu copyArchRegs(oldContext); 1952862Sktlim@umich.edu cpuId = oldContext->readCpuId(); 1962862Sktlim@umich.edu#if !FULL_SYSTEM 1972862Sktlim@umich.edu funcExeInst = oldContext->readFuncExeInst(); 1982862Sktlim@umich.edu#endif 1992915Sktlim@umich.edu inst = oldContext->getInst(); 2002862Sktlim@umich.edu} 2012862Sktlim@umich.edu 2022862Sktlim@umich.eduvoid 2032683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 204217SN/A{ 2052862Sktlim@umich.edu ThreadState::serialize(os); 206223SN/A regs.serialize(os); 207223SN/A // thread_num and cpu_id are deterministic from the config 208217SN/A} 209217SN/A 210217SN/A 211217SN/Avoid 2122683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 213217SN/A{ 2142862Sktlim@umich.edu ThreadState::unserialize(cp, section); 215237SN/A regs.unserialize(cp, section); 216223SN/A // thread_num and cpu_id are deterministic from the config 217217SN/A} 218217SN/A 2192683Sktlim@umich.edu#if FULL_SYSTEM 2202683Sktlim@umich.eduvoid 2212683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2222683Sktlim@umich.edu{ 2232683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2242683Sktlim@umich.edu profile->dump(tc, *os); 2252683Sktlim@umich.edu} 2262683Sktlim@umich.edu#endif 227217SN/A 228217SN/Avoid 2292683Sktlim@umich.eduSimpleThread::activate(int delay) 2302SN/A{ 2312680SN/A if (status() == ThreadContext::Active) 2322SN/A return; 2332SN/A 2342188SN/A lastActivate = curTick; 2352188SN/A 2362680SN/A if (status() == ThreadContext::Unallocated) { 2372683Sktlim@umich.edu cpu->activateWhenReady(tid); 2382290SN/A return; 2392290SN/A } 2402290SN/A 2412680SN/A _status = ThreadContext::Active; 2422290SN/A 2432290SN/A // status() == Suspended 2442683Sktlim@umich.edu cpu->activateContext(tid, delay); 245393SN/A} 246393SN/A 247393SN/Avoid 2482683Sktlim@umich.eduSimpleThread::suspend() 249393SN/A{ 2502680SN/A if (status() == ThreadContext::Suspended) 251393SN/A return; 252393SN/A 2532188SN/A lastActivate = curTick; 2542188SN/A lastSuspend = curTick; 2552188SN/A/* 2561858SN/A#if FULL_SYSTEM 2572SN/A // Don't change the status from active if there are pending interrupts 258393SN/A if (cpu->check_interrupts()) { 2592680SN/A assert(status() == ThreadContext::Active); 2602SN/A return; 2612SN/A } 2622SN/A#endif 2632188SN/A*/ 2642680SN/A _status = ThreadContext::Suspended; 2652683Sktlim@umich.edu cpu->suspendContext(tid); 2662SN/A} 2672SN/A 2682SN/Avoid 2692683Sktlim@umich.eduSimpleThread::deallocate() 270393SN/A{ 2712680SN/A if (status() == ThreadContext::Unallocated) 272393SN/A return; 273393SN/A 2742680SN/A _status = ThreadContext::Unallocated; 2752683Sktlim@umich.edu cpu->deallocateContext(tid); 276393SN/A} 277393SN/A 278393SN/Avoid 2792683Sktlim@umich.eduSimpleThread::halt() 280393SN/A{ 2812680SN/A if (status() == ThreadContext::Halted) 282393SN/A return; 283393SN/A 2842680SN/A _status = ThreadContext::Halted; 2852683Sktlim@umich.edu cpu->haltContext(tid); 286393SN/A} 287393SN/A 288393SN/A 289393SN/Avoid 2902683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2912SN/A{ 2922330SN/A#if FULL_SYSTEM 2932341SN/A if (kernelStats) 2942341SN/A kernelStats->regStats(name + ".kern"); 2952330SN/A#endif 2962SN/A} 297716SN/A 298716SN/Avoid 2992683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 3002190SN/A{ 3012680SN/A TheISA::copyRegs(src_tc, tc); 3022190SN/A} 3032190SN/A 3042521SN/A#if FULL_SYSTEM 3052521SN/AVirtualPort* 3062683Sktlim@umich.eduSimpleThread::getVirtPort(ThreadContext *src_tc) 3072521SN/A{ 3082680SN/A if (!src_tc) 3092521SN/A return virtPort; 3102521SN/A 3113486Sktlim@umich.edu VirtualPort *vp = new VirtualPort("tc-vport", src_tc); 3123486Sktlim@umich.edu Port *mem_port = getMemFuncPort(); 3132521SN/A 3142521SN/A mem_port->setPeer(vp); 3152521SN/A vp->setPeer(mem_port); 3162521SN/A return vp; 3172521SN/A} 3182521SN/A 3192521SN/Avoid 3202683Sktlim@umich.eduSimpleThread::delVirtPort(VirtualPort *vp) 3212521SN/A{ 3222684Ssaidi@eecs.umich.edu if (vp != virtPort) { 3232684Ssaidi@eecs.umich.edu delete vp->getPeer(); 3242684Ssaidi@eecs.umich.edu delete vp; 3252684Ssaidi@eecs.umich.edu } 3262521SN/A} 3272521SN/A 3282521SN/A#endif 3292521SN/A 330