simple_thread.cc revision 3402
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 371717SN/A#include "cpu/base.hh" 382683Sktlim@umich.edu#include "cpu/simple_thread.hh" 392680SN/A#include "cpu/thread_context.hh" 402SN/A 411858SN/A#if FULL_SYSTEM 421917SN/A#include "base/callback.hh" 431070SN/A#include "base/cprintf.hh" 441917SN/A#include "base/output.hh" 452188SN/A#include "base/trace.hh" 461917SN/A#include "cpu/profile.hh" 472290SN/A#include "cpu/quiesce_event.hh" 481070SN/A#include "kern/kernel_stats.hh" 491070SN/A#include "sim/serialize.hh" 501917SN/A#include "sim/sim_exit.hh" 512170SN/A#include "arch/stacktrace.hh" 522SN/A#else 53360SN/A#include "sim/process.hh" 542519SN/A#include "sim/system.hh" 552420SN/A#include "mem/translating_port.hh" 562SN/A#endif 572SN/A 582SN/Ausing namespace std; 592SN/A 602SN/A// constructor 611858SN/A#if FULL_SYSTEM 622683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 632683Sktlim@umich.edu AlphaITB *_itb, AlphaDTB *_dtb, 642683Sktlim@umich.edu bool use_kernel_stats) 653402Sktlim@umich.edu : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), 662683Sktlim@umich.edu dtb(_dtb) 672521SN/A 682SN/A{ 692683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 702190SN/A 712680SN/A quiesceEvent = new EndQuiesceEvent(tc); 722290SN/A 732526SN/A regs.clear(); 741917SN/A 751917SN/A if (cpu->params->profile) { 761982SN/A profile = new FunctionProfile(system->kernelSymtab); 771917SN/A Callback *cb = 782683Sktlim@umich.edu new MakeCallback<SimpleThread, 792683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 801917SN/A registerExitCallback(cb); 811917SN/A } 821917SN/A 831917SN/A // let's fill with a dummy node for now so we don't get a segfault 841917SN/A // on the first cycle when there's no node available. 851917SN/A static ProfileNode dummyNode; 861917SN/A profileNode = &dummyNode; 871917SN/A profilePC = 3; 882521SN/A 892341SN/A if (use_kernel_stats) { 902341SN/A kernelStats = new Kernel::Statistics(system); 912341SN/A } else { 922341SN/A kernelStats = NULL; 932341SN/A } 942521SN/A Port *mem_port; 952640SN/A physPort = new FunctionalPort(csprintf("%s-%d-funcport", 962683Sktlim@umich.edu cpu->name(), tid)); 972521SN/A mem_port = system->physmem->getPort("functional"); 982521SN/A mem_port->setPeer(physPort); 992521SN/A physPort->setPeer(mem_port); 1002521SN/A 1012640SN/A virtPort = new VirtualPort(csprintf("%s-%d-vport", 1022683Sktlim@umich.edu cpu->name(), tid)); 1032521SN/A mem_port = system->physmem->getPort("functional"); 1042521SN/A mem_port->setPeer(virtPort); 1052521SN/A virtPort->setPeer(mem_port); 1062SN/A} 1072SN/A#else 1082683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, 1093402Sktlim@umich.edu Process *_process, int _asid) 1103402Sktlim@umich.edu : ThreadState(_cpu, -1, _thread_num, _process, _asid), 1112683Sktlim@umich.edu cpu(_cpu) 1122SN/A{ 1132526SN/A regs.clear(); 1142683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1152SN/A} 1162190SN/A 1172862Sktlim@umich.edu#endif 1182862Sktlim@umich.edu 1192864Sktlim@umich.eduSimpleThread::SimpleThread() 1202862Sktlim@umich.edu#if FULL_SYSTEM 1213402Sktlim@umich.edu : ThreadState(NULL, -1, -1) 1222862Sktlim@umich.edu#else 1233402Sktlim@umich.edu : ThreadState(NULL, -1, -1, NULL, -1) 1242862Sktlim@umich.edu#endif 1252190SN/A{ 1262683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1272862Sktlim@umich.edu regs.clear(); 1282190SN/A} 1292190SN/A 1302683Sktlim@umich.eduSimpleThread::~SimpleThread() 1311070SN/A{ 1322680SN/A delete tc; 1331070SN/A} 1341070SN/A 1351917SN/Avoid 1362683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 137180SN/A{ 138180SN/A // some things should already be set up 1391858SN/A#if FULL_SYSTEM 1402235SN/A assert(system == oldContext->getSystemPtr()); 141180SN/A#else 1422235SN/A assert(process == oldContext->getProcessPtr()); 143180SN/A#endif 144180SN/A 1452862Sktlim@umich.edu copyState(oldContext); 1462862Sktlim@umich.edu#if FULL_SYSTEM 1472313SN/A EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1482313SN/A if (quiesce) { 1492680SN/A // Point the quiesce event's TC at this TC so that it wakes up 1502313SN/A // the proper CPU. 1512680SN/A quiesce->tc = tc; 1522313SN/A } 1532313SN/A if (quiesceEvent) { 1542680SN/A quiesceEvent->tc = tc; 1552313SN/A } 1562361SN/A 1572361SN/A Kernel::Statistics *stats = oldContext->getKernelStats(); 1582361SN/A if (stats) { 1592361SN/A kernelStats = stats; 1602361SN/A } 1612235SN/A#endif 162180SN/A 163180SN/A storeCondFailures = 0; 164180SN/A 1652680SN/A oldContext->setStatus(ThreadContext::Unallocated); 166180SN/A} 167180SN/A 1682SN/Avoid 1692864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1702864Sktlim@umich.edu{ 1712864Sktlim@umich.edu copyState(context); 1722864Sktlim@umich.edu 1732864Sktlim@umich.edu#if FULL_SYSTEM 1742864Sktlim@umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1752864Sktlim@umich.edu if (quiesce) { 1762864Sktlim@umich.edu quiesceEvent = quiesce; 1772864Sktlim@umich.edu } 1782864Sktlim@umich.edu Kernel::Statistics *stats = context->getKernelStats(); 1792864Sktlim@umich.edu if (stats) { 1802864Sktlim@umich.edu kernelStats = stats; 1812864Sktlim@umich.edu } 1822864Sktlim@umich.edu#endif 1832864Sktlim@umich.edu} 1842864Sktlim@umich.edu 1852864Sktlim@umich.eduvoid 1862862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1872862Sktlim@umich.edu{ 1882862Sktlim@umich.edu // copy over functional state 1892862Sktlim@umich.edu _status = oldContext->status(); 1902862Sktlim@umich.edu copyArchRegs(oldContext); 1912862Sktlim@umich.edu cpuId = oldContext->readCpuId(); 1922862Sktlim@umich.edu#if !FULL_SYSTEM 1932862Sktlim@umich.edu funcExeInst = oldContext->readFuncExeInst(); 1942862Sktlim@umich.edu#endif 1952915Sktlim@umich.edu inst = oldContext->getInst(); 1962862Sktlim@umich.edu} 1972862Sktlim@umich.edu 1982862Sktlim@umich.eduvoid 1992683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 200217SN/A{ 2012862Sktlim@umich.edu ThreadState::serialize(os); 202223SN/A regs.serialize(os); 203223SN/A // thread_num and cpu_id are deterministic from the config 204217SN/A} 205217SN/A 206217SN/A 207217SN/Avoid 2082683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 209217SN/A{ 2102862Sktlim@umich.edu ThreadState::unserialize(cp, section); 211237SN/A regs.unserialize(cp, section); 212223SN/A // thread_num and cpu_id are deterministic from the config 213217SN/A} 214217SN/A 2152683Sktlim@umich.edu#if FULL_SYSTEM 2162683Sktlim@umich.eduvoid 2172683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2182683Sktlim@umich.edu{ 2192683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2202683Sktlim@umich.edu profile->dump(tc, *os); 2212683Sktlim@umich.edu} 2222683Sktlim@umich.edu#endif 223217SN/A 224217SN/Avoid 2252683Sktlim@umich.eduSimpleThread::activate(int delay) 2262SN/A{ 2272680SN/A if (status() == ThreadContext::Active) 2282SN/A return; 2292SN/A 2302188SN/A lastActivate = curTick; 2312188SN/A 2322680SN/A if (status() == ThreadContext::Unallocated) { 2332683Sktlim@umich.edu cpu->activateWhenReady(tid); 2342290SN/A return; 2352290SN/A } 2362290SN/A 2372680SN/A _status = ThreadContext::Active; 2382290SN/A 2392290SN/A // status() == Suspended 2402683Sktlim@umich.edu cpu->activateContext(tid, delay); 241393SN/A} 242393SN/A 243393SN/Avoid 2442683Sktlim@umich.eduSimpleThread::suspend() 245393SN/A{ 2462680SN/A if (status() == ThreadContext::Suspended) 247393SN/A return; 248393SN/A 2492188SN/A lastActivate = curTick; 2502188SN/A lastSuspend = curTick; 2512188SN/A/* 2521858SN/A#if FULL_SYSTEM 2532SN/A // Don't change the status from active if there are pending interrupts 254393SN/A if (cpu->check_interrupts()) { 2552680SN/A assert(status() == ThreadContext::Active); 2562SN/A return; 2572SN/A } 2582SN/A#endif 2592188SN/A*/ 2602680SN/A _status = ThreadContext::Suspended; 2612683Sktlim@umich.edu cpu->suspendContext(tid); 2622SN/A} 2632SN/A 2642SN/Avoid 2652683Sktlim@umich.eduSimpleThread::deallocate() 266393SN/A{ 2672680SN/A if (status() == ThreadContext::Unallocated) 268393SN/A return; 269393SN/A 2702680SN/A _status = ThreadContext::Unallocated; 2712683Sktlim@umich.edu cpu->deallocateContext(tid); 272393SN/A} 273393SN/A 274393SN/Avoid 2752683Sktlim@umich.eduSimpleThread::halt() 276393SN/A{ 2772680SN/A if (status() == ThreadContext::Halted) 278393SN/A return; 279393SN/A 2802680SN/A _status = ThreadContext::Halted; 2812683Sktlim@umich.edu cpu->haltContext(tid); 282393SN/A} 283393SN/A 284393SN/A 285393SN/Avoid 2862683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2872SN/A{ 2882330SN/A#if FULL_SYSTEM 2892341SN/A if (kernelStats) 2902341SN/A kernelStats->regStats(name + ".kern"); 2912330SN/A#endif 2922SN/A} 293716SN/A 294716SN/Avoid 2952683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2962190SN/A{ 2972680SN/A TheISA::copyRegs(src_tc, tc); 2982190SN/A} 2992190SN/A 3002521SN/A#if FULL_SYSTEM 3012521SN/AVirtualPort* 3022683Sktlim@umich.eduSimpleThread::getVirtPort(ThreadContext *src_tc) 3032521SN/A{ 3042680SN/A if (!src_tc) 3052521SN/A return virtPort; 3062521SN/A 3072521SN/A VirtualPort *vp; 3082521SN/A Port *mem_port; 3092521SN/A 3102680SN/A vp = new VirtualPort("tc-vport", src_tc); 3112521SN/A mem_port = system->physmem->getPort("functional"); 3122521SN/A mem_port->setPeer(vp); 3132521SN/A vp->setPeer(mem_port); 3142521SN/A return vp; 3152521SN/A} 3162521SN/A 3172521SN/Avoid 3182683Sktlim@umich.eduSimpleThread::delVirtPort(VirtualPort *vp) 3192521SN/A{ 3202684Ssaidi@eecs.umich.edu if (vp != virtPort) { 3212684Ssaidi@eecs.umich.edu delete vp->getPeer(); 3222684Ssaidi@eecs.umich.edu delete vp; 3232684Ssaidi@eecs.umich.edu } 3242521SN/A} 3252521SN/A 3263402Sktlim@umich.edu#else 3273402Sktlim@umich.eduTranslatingPort * 3283402Sktlim@umich.eduSimpleThread::getMemPort() 3293402Sktlim@umich.edu{ 3303402Sktlim@umich.edu if (port != NULL) 3313402Sktlim@umich.edu return port; 3323402Sktlim@umich.edu 3333402Sktlim@umich.edu /* Use this port to for syscall emulation writes to memory. */ 3343402Sktlim@umich.edu Port *dcache_port; 3353402Sktlim@umich.edu port = new TranslatingPort(csprintf("%s-%d-funcport", 3363402Sktlim@umich.edu cpu->name(), tid), 3373402Sktlim@umich.edu process->pTable, false); 3383402Sktlim@umich.edu dcache_port = cpu->getPort("dcache_port"); 3393402Sktlim@umich.edu assert(dcache_port != NULL); 3403402Sktlim@umich.edu dcache_port = dcache_port->getPeer(); 3413402Sktlim@umich.edu// mem_port->setPeer(port); 3423402Sktlim@umich.edu port->setPeer(dcache_port); 3433402Sktlim@umich.edu return port; 3443402Sktlim@umich.edu} 3452521SN/A 3462521SN/A#endif 3472521SN/A 348