simple_thread.cc revision 2862
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 371717SN/A#include "cpu/base.hh" 382683Sktlim@umich.edu#include "cpu/simple_thread.hh" 392680SN/A#include "cpu/thread_context.hh" 402SN/A 411858SN/A#if FULL_SYSTEM 421917SN/A#include "base/callback.hh" 431070SN/A#include "base/cprintf.hh" 441917SN/A#include "base/output.hh" 452188SN/A#include "base/trace.hh" 461917SN/A#include "cpu/profile.hh" 472290SN/A#include "cpu/quiesce_event.hh" 481070SN/A#include "kern/kernel_stats.hh" 491070SN/A#include "sim/serialize.hh" 501917SN/A#include "sim/sim_exit.hh" 512170SN/A#include "arch/stacktrace.hh" 522SN/A#else 53360SN/A#include "sim/process.hh" 542519SN/A#include "sim/system.hh" 552420SN/A#include "mem/translating_port.hh" 562SN/A#endif 572SN/A 582SN/Ausing namespace std; 592SN/A 602SN/A// constructor 611858SN/A#if FULL_SYSTEM 622683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 632683Sktlim@umich.edu AlphaITB *_itb, AlphaDTB *_dtb, 642683Sktlim@umich.edu bool use_kernel_stats) 652683Sktlim@umich.edu : ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), 662683Sktlim@umich.edu dtb(_dtb) 672521SN/A 682SN/A{ 692683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 702190SN/A 712680SN/A quiesceEvent = new EndQuiesceEvent(tc); 722290SN/A 732526SN/A regs.clear(); 741917SN/A 751917SN/A if (cpu->params->profile) { 761982SN/A profile = new FunctionProfile(system->kernelSymtab); 771917SN/A Callback *cb = 782683Sktlim@umich.edu new MakeCallback<SimpleThread, 792683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 801917SN/A registerExitCallback(cb); 811917SN/A } 821917SN/A 831917SN/A // let's fill with a dummy node for now so we don't get a segfault 841917SN/A // on the first cycle when there's no node available. 851917SN/A static ProfileNode dummyNode; 861917SN/A profileNode = &dummyNode; 871917SN/A profilePC = 3; 882521SN/A 892341SN/A if (use_kernel_stats) { 902341SN/A kernelStats = new Kernel::Statistics(system); 912341SN/A } else { 922341SN/A kernelStats = NULL; 932341SN/A } 942521SN/A Port *mem_port; 952640SN/A physPort = new FunctionalPort(csprintf("%s-%d-funcport", 962683Sktlim@umich.edu cpu->name(), tid)); 972521SN/A mem_port = system->physmem->getPort("functional"); 982521SN/A mem_port->setPeer(physPort); 992521SN/A physPort->setPeer(mem_port); 1002521SN/A 1012640SN/A virtPort = new VirtualPort(csprintf("%s-%d-vport", 1022683Sktlim@umich.edu cpu->name(), tid)); 1032521SN/A mem_port = system->physmem->getPort("functional"); 1042521SN/A mem_port->setPeer(virtPort); 1052521SN/A virtPort->setPeer(mem_port); 1062SN/A} 1072SN/A#else 1082683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, 1092520SN/A Process *_process, int _asid, MemObject* memobj) 1102791Sktlim@umich.edu : ThreadState(-1, _thread_num, _process, _asid, memobj), 1112683Sktlim@umich.edu cpu(_cpu) 1122SN/A{ 1132519SN/A /* Use this port to for syscall emulation writes to memory. */ 1142519SN/A Port *mem_port; 1152640SN/A port = new TranslatingPort(csprintf("%s-%d-funcport", 1162683Sktlim@umich.edu cpu->name(), tid), 1172640SN/A process->pTable, false); 1182520SN/A mem_port = memobj->getPort("functional"); 1192519SN/A mem_port->setPeer(port); 1202519SN/A port->setPeer(mem_port); 1212519SN/A 1222526SN/A regs.clear(); 1232683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1242SN/A} 1252190SN/A 1262862Sktlim@umich.edu#endif 1272862Sktlim@umich.edu 1282862Sktlim@umich.eduSimpleThread::SimpleThread(ThreadContext *oldContext) 1292862Sktlim@umich.edu#if FULL_SYSTEM 1302862Sktlim@umich.edu : ThreadState(-1, -1) 1312862Sktlim@umich.edu#else 1322862Sktlim@umich.edu : ThreadState(-1, -1, NULL, -1, NULL) 1332862Sktlim@umich.edu#endif 1342190SN/A{ 1352683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1362862Sktlim@umich.edu regs.clear(); 1372862Sktlim@umich.edu 1382862Sktlim@umich.edu copyState(oldContext); 1392862Sktlim@umich.edu 1402862Sktlim@umich.edu#if FULL_SYSTEM 1412862Sktlim@umich.edu EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1422862Sktlim@umich.edu if (quiesce) { 1432862Sktlim@umich.edu quiesceEvent = quiesce; 1442862Sktlim@umich.edu } 1452862Sktlim@umich.edu Kernel::Statistics *stats = oldContext->getKernelStats(); 1462862Sktlim@umich.edu if (stats) { 1472862Sktlim@umich.edu kernelStats = stats; 1482862Sktlim@umich.edu } 1492862Sktlim@umich.edu#endif 1502190SN/A} 1512190SN/A 1522683Sktlim@umich.eduSimpleThread::~SimpleThread() 1531070SN/A{ 1542680SN/A delete tc; 1551070SN/A} 1561070SN/A 1571917SN/Avoid 1582683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 159180SN/A{ 160180SN/A // some things should already be set up 1611858SN/A#if FULL_SYSTEM 1622235SN/A assert(system == oldContext->getSystemPtr()); 163180SN/A#else 1642235SN/A assert(process == oldContext->getProcessPtr()); 165180SN/A#endif 166180SN/A 1672862Sktlim@umich.edu copyState(oldContext); 1682862Sktlim@umich.edu#if FULL_SYSTEM 1692313SN/A EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1702313SN/A if (quiesce) { 1712680SN/A // Point the quiesce event's TC at this TC so that it wakes up 1722313SN/A // the proper CPU. 1732680SN/A quiesce->tc = tc; 1742313SN/A } 1752313SN/A if (quiesceEvent) { 1762680SN/A quiesceEvent->tc = tc; 1772313SN/A } 1782235SN/A#endif 179180SN/A 180180SN/A storeCondFailures = 0; 181180SN/A 1822680SN/A oldContext->setStatus(ThreadContext::Unallocated); 183180SN/A} 184180SN/A 1852SN/Avoid 1862862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1872862Sktlim@umich.edu{ 1882862Sktlim@umich.edu // copy over functional state 1892862Sktlim@umich.edu _status = oldContext->status(); 1902862Sktlim@umich.edu copyArchRegs(oldContext); 1912862Sktlim@umich.edu cpuId = oldContext->readCpuId(); 1922862Sktlim@umich.edu#if !FULL_SYSTEM 1932862Sktlim@umich.edu funcExeInst = oldContext->readFuncExeInst(); 1942862Sktlim@umich.edu#endif 1952862Sktlim@umich.edu} 1962862Sktlim@umich.edu 1972862Sktlim@umich.eduvoid 1982683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 199217SN/A{ 2002862Sktlim@umich.edu ThreadState::serialize(os); 201223SN/A regs.serialize(os); 202223SN/A // thread_num and cpu_id are deterministic from the config 203217SN/A} 204217SN/A 205217SN/A 206217SN/Avoid 2072683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 208217SN/A{ 2092862Sktlim@umich.edu ThreadState::unserialize(cp, section); 210237SN/A regs.unserialize(cp, section); 211223SN/A // thread_num and cpu_id are deterministic from the config 212217SN/A} 213217SN/A 2142683Sktlim@umich.edu#if FULL_SYSTEM 2152683Sktlim@umich.eduvoid 2162683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2172683Sktlim@umich.edu{ 2182683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2192683Sktlim@umich.edu profile->dump(tc, *os); 2202683Sktlim@umich.edu} 2212683Sktlim@umich.edu#endif 222217SN/A 223217SN/Avoid 2242683Sktlim@umich.eduSimpleThread::activate(int delay) 2252SN/A{ 2262680SN/A if (status() == ThreadContext::Active) 2272SN/A return; 2282SN/A 2292188SN/A lastActivate = curTick; 2302188SN/A 2312680SN/A if (status() == ThreadContext::Unallocated) { 2322683Sktlim@umich.edu cpu->activateWhenReady(tid); 2332290SN/A return; 2342290SN/A } 2352290SN/A 2362680SN/A _status = ThreadContext::Active; 2372290SN/A 2382290SN/A // status() == Suspended 2392683Sktlim@umich.edu cpu->activateContext(tid, delay); 240393SN/A} 241393SN/A 242393SN/Avoid 2432683Sktlim@umich.eduSimpleThread::suspend() 244393SN/A{ 2452680SN/A if (status() == ThreadContext::Suspended) 246393SN/A return; 247393SN/A 2482188SN/A lastActivate = curTick; 2492188SN/A lastSuspend = curTick; 2502188SN/A/* 2511858SN/A#if FULL_SYSTEM 2522SN/A // Don't change the status from active if there are pending interrupts 253393SN/A if (cpu->check_interrupts()) { 2542680SN/A assert(status() == ThreadContext::Active); 2552SN/A return; 2562SN/A } 2572SN/A#endif 2582188SN/A*/ 2592680SN/A _status = ThreadContext::Suspended; 2602683Sktlim@umich.edu cpu->suspendContext(tid); 2612SN/A} 2622SN/A 2632SN/Avoid 2642683Sktlim@umich.eduSimpleThread::deallocate() 265393SN/A{ 2662680SN/A if (status() == ThreadContext::Unallocated) 267393SN/A return; 268393SN/A 2692680SN/A _status = ThreadContext::Unallocated; 2702683Sktlim@umich.edu cpu->deallocateContext(tid); 271393SN/A} 272393SN/A 273393SN/Avoid 2742683Sktlim@umich.eduSimpleThread::halt() 275393SN/A{ 2762680SN/A if (status() == ThreadContext::Halted) 277393SN/A return; 278393SN/A 2792680SN/A _status = ThreadContext::Halted; 2802683Sktlim@umich.edu cpu->haltContext(tid); 281393SN/A} 282393SN/A 283393SN/A 284393SN/Avoid 2852683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2862SN/A{ 2872330SN/A#if FULL_SYSTEM 2882341SN/A if (kernelStats) 2892341SN/A kernelStats->regStats(name + ".kern"); 2902330SN/A#endif 2912SN/A} 292716SN/A 293716SN/Avoid 2942683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2952190SN/A{ 2962680SN/A TheISA::copyRegs(src_tc, tc); 2972190SN/A} 2982190SN/A 2992521SN/A#if FULL_SYSTEM 3002521SN/AVirtualPort* 3012683Sktlim@umich.eduSimpleThread::getVirtPort(ThreadContext *src_tc) 3022521SN/A{ 3032680SN/A if (!src_tc) 3042521SN/A return virtPort; 3052521SN/A 3062521SN/A VirtualPort *vp; 3072521SN/A Port *mem_port; 3082521SN/A 3092680SN/A vp = new VirtualPort("tc-vport", src_tc); 3102521SN/A mem_port = system->physmem->getPort("functional"); 3112521SN/A mem_port->setPeer(vp); 3122521SN/A vp->setPeer(mem_port); 3132521SN/A return vp; 3142521SN/A} 3152521SN/A 3162521SN/Avoid 3172683Sktlim@umich.eduSimpleThread::delVirtPort(VirtualPort *vp) 3182521SN/A{ 3192684Ssaidi@eecs.umich.edu if (vp != virtPort) { 3202684Ssaidi@eecs.umich.edu delete vp->getPeer(); 3212684Ssaidi@eecs.umich.edu delete vp; 3222684Ssaidi@eecs.umich.edu } 3232521SN/A} 3242521SN/A 3252521SN/A 3262521SN/A#endif 3272521SN/A 328