simple_thread.cc revision 13865
12SN/A/* 213759Sgiacomo.gabrielli@arm.com * Copyright (c) 2018 ARM Limited 313759Sgiacomo.gabrielli@arm.com * All rights reserved 413759Sgiacomo.gabrielli@arm.com * 513759Sgiacomo.gabrielli@arm.com * The license below extends only to copyright in the software and shall 613759Sgiacomo.gabrielli@arm.com * not be construed as granting a license to any other intellectual 713759Sgiacomo.gabrielli@arm.com * property including but not limited to intellectual property relating 813759Sgiacomo.gabrielli@arm.com * to a hardware implementation of the functionality of the software 913759Sgiacomo.gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 1013759Sgiacomo.gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 1113759Sgiacomo.gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 1213759Sgiacomo.gabrielli@arm.com * modified or unmodified, in source code or in binary form. 1313759Sgiacomo.gabrielli@arm.com * 142188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Steve Reinhardt 412665SN/A * Nathan Binkert 422665SN/A * Lisa Hsu 432665SN/A * Kevin Lim 442SN/A */ 452SN/A 4611793Sbrandon.potter@amd.com#include "cpu/simple_thread.hh" 4711793Sbrandon.potter@amd.com 482SN/A#include <string> 492SN/A 502465SN/A#include "arch/isa_traits.hh" 513565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 525529Snate@binkert.org#include "arch/stacktrace.hh" 538777Sgblack@eecs.umich.edu#include "arch/utility.hh" 541917SN/A#include "base/callback.hh" 551070SN/A#include "base/cprintf.hh" 561917SN/A#include "base/output.hh" 572188SN/A#include "base/trace.hh" 588777Sgblack@eecs.umich.edu#include "config/the_isa.hh" 598777Sgblack@eecs.umich.edu#include "cpu/base.hh" 601917SN/A#include "cpu/profile.hh" 612290SN/A#include "cpu/quiesce_event.hh" 628777Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 638706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 648799Sgblack@eecs.umich.edu#include "mem/se_translating_port_proxy.hh" 658809Sgblack@eecs.umich.edu#include "params/BaseCPU.hh" 6610319SAndreas.Sandberg@ARM.com#include "sim/faults.hh" 678793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 688777Sgblack@eecs.umich.edu#include "sim/process.hh" 691070SN/A#include "sim/serialize.hh" 701917SN/A#include "sim/sim_exit.hh" 712519SN/A#include "sim/system.hh" 722SN/A 732SN/Ausing namespace std; 742SN/A 752SN/A// constructor 768820Sgblack@eecs.umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 7712406Sgabeblack@google.com Process *_process, BaseTLB *_itb, 7812406Sgabeblack@google.com BaseTLB *_dtb, TheISA::ISA *_isa) 7910537Sandreas.hansson@arm.com : ThreadState(_cpu, _thread_num, _process), isa(_isa), 8010537Sandreas.hansson@arm.com predicate(false), system(_sys), 8113759Sgiacomo.gabrielli@arm.com itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa)) 828766Sgblack@eecs.umich.edu{ 838766Sgblack@eecs.umich.edu clearArchRegs(); 8413865Sgabeblack@google.com quiesceEvent = new EndQuiesceEvent(this); 858766Sgblack@eecs.umich.edu} 869377Sgblack@eecs.umich.edu 872683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 8812406Sgabeblack@google.com BaseTLB *_itb, BaseTLB *_dtb, 899384SAndreas.Sandberg@arm.com TheISA::ISA *_isa, bool use_kernel_stats) 909384SAndreas.Sandberg@arm.com : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb), 9113759Sgiacomo.gabrielli@arm.com dtb(_dtb), decoder(TheISA::Decoder(_isa)) 922SN/A{ 9313865Sgabeblack@google.com quiesceEvent = new EndQuiesceEvent(this); 942290SN/A 956316Sgblack@eecs.umich.edu clearArchRegs(); 961917SN/A 978735Sandreas.hanson@arm.com if (baseCpu->params()->profile) { 981982SN/A profile = new FunctionProfile(system->kernelSymtab); 991917SN/A Callback *cb = 1002683Sktlim@umich.edu new MakeCallback<SimpleThread, 1012683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 1021917SN/A registerExitCallback(cb); 1031917SN/A } 1041917SN/A 1051917SN/A // let's fill with a dummy node for now so we don't get a segfault 1061917SN/A // on the first cycle when there's no node available. 1071917SN/A static ProfileNode dummyNode; 1081917SN/A profileNode = &dummyNode; 1091917SN/A profilePC = 3; 1102521SN/A 1115482Snate@binkert.org if (use_kernel_stats) 11212181Sgabeblack@google.com kernelStats = new TheISA::Kernel::Statistics(); 1132SN/A} 1142862Sktlim@umich.edu 1151917SN/Avoid 1162683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 117180SN/A{ 11813865Sgabeblack@google.com ::takeOverFrom(*this, *oldContext); 1199478Snilay@cs.wisc.edu decoder.takeOverFrom(oldContext->getDecoderPtr()); 120180SN/A 1219441SAndreas.Sandberg@ARM.com kernelStats = oldContext->getKernelStats(); 1229441SAndreas.Sandberg@ARM.com funcExeInst = oldContext->readFuncExeInst(); 123180SN/A storeCondFailures = 0; 1242864Sktlim@umich.edu} 1252864Sktlim@umich.edu 1262864Sktlim@umich.eduvoid 1272862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1282862Sktlim@umich.edu{ 1292862Sktlim@umich.edu // copy over functional state 1302862Sktlim@umich.edu _status = oldContext->status(); 1312862Sktlim@umich.edu copyArchRegs(oldContext); 1328793Sgblack@eecs.umich.edu if (FullSystem) 1338793Sgblack@eecs.umich.edu funcExeInst = oldContext->readFuncExeInst(); 1345714Shsul@eecs.umich.edu 1355715Shsul@eecs.umich.edu _threadId = oldContext->threadId(); 1365714Shsul@eecs.umich.edu _contextId = oldContext->contextId(); 1372862Sktlim@umich.edu} 1382862Sktlim@umich.edu 1392862Sktlim@umich.eduvoid 14010905Sandreas.sandberg@arm.comSimpleThread::serialize(CheckpointOut &cp) const 141217SN/A{ 14210905Sandreas.sandberg@arm.com ThreadState::serialize(cp); 14313865Sgabeblack@google.com ::serialize(*this, cp); 144217SN/A} 145217SN/A 146217SN/A 147217SN/Avoid 14810905Sandreas.sandberg@arm.comSimpleThread::unserialize(CheckpointIn &cp) 149217SN/A{ 15010905Sandreas.sandberg@arm.com ThreadState::unserialize(cp); 15113865Sgabeblack@google.com ::unserialize(*this, cp); 152217SN/A} 153217SN/A 1542683Sktlim@umich.eduvoid 1559461Snilay@cs.wisc.eduSimpleThread::startup() 1569461Snilay@cs.wisc.edu{ 15713865Sgabeblack@google.com isa->startup(this); 1589461Snilay@cs.wisc.edu} 1599461Snilay@cs.wisc.edu 1609461Snilay@cs.wisc.eduvoid 1612683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 1622683Sktlim@umich.edu{ 16311359Sandreas@sandberg.pp.se OutputStream *os(simout.create(csprintf("profile.%s.dat", baseCpu->name()))); 16413865Sgabeblack@google.com profile->dump(this, *os->stream()); 16511359Sandreas@sandberg.pp.se simout.close(os); 1662683Sktlim@umich.edu} 167217SN/A 168217SN/Avoid 16910407Smitch.hayenga@arm.comSimpleThread::activate() 1702SN/A{ 1712680SN/A if (status() == ThreadContext::Active) 1722SN/A return; 1732SN/A 1747823Ssteve.reinhardt@amd.com lastActivate = curTick(); 1752680SN/A _status = ThreadContext::Active; 17610407Smitch.hayenga@arm.com baseCpu->activateContext(_threadId); 177393SN/A} 178393SN/A 179393SN/Avoid 1802683Sktlim@umich.eduSimpleThread::suspend() 181393SN/A{ 1822680SN/A if (status() == ThreadContext::Suspended) 183393SN/A return; 184393SN/A 1857823Ssteve.reinhardt@amd.com lastActivate = curTick(); 1867823Ssteve.reinhardt@amd.com lastSuspend = curTick(); 1872680SN/A _status = ThreadContext::Suspended; 1888735Sandreas.hanson@arm.com baseCpu->suspendContext(_threadId); 1892SN/A} 1902SN/A 191393SN/A 192393SN/Avoid 1932683Sktlim@umich.eduSimpleThread::halt() 194393SN/A{ 1952680SN/A if (status() == ThreadContext::Halted) 196393SN/A return; 197393SN/A 1982680SN/A _status = ThreadContext::Halted; 1998735Sandreas.hanson@arm.com baseCpu->haltContext(_threadId); 200393SN/A} 201393SN/A 202393SN/A 203393SN/Avoid 2042683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2052SN/A{ 2068793Sgblack@eecs.umich.edu if (FullSystem && kernelStats) 2072341SN/A kernelStats->regStats(name + ".kern"); 2082SN/A} 209716SN/A 210716SN/Avoid 2112683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2122190SN/A{ 21313865Sgabeblack@google.com TheISA::copyRegs(src_tc, this); 2142190SN/A} 2152190SN/A 21610319SAndreas.Sandberg@ARM.com// The following methods are defined in src/arch/alpha/ev5.cc for 21710319SAndreas.Sandberg@ARM.com// Alpha. 21810319SAndreas.Sandberg@ARM.com#if THE_ISA != ALPHA_ISA 21910319SAndreas.Sandberg@ARM.comFault 22010319SAndreas.Sandberg@ARM.comSimpleThread::hwrei() 22110319SAndreas.Sandberg@ARM.com{ 22210319SAndreas.Sandberg@ARM.com return NoFault; 22310319SAndreas.Sandberg@ARM.com} 22410319SAndreas.Sandberg@ARM.com 22510319SAndreas.Sandberg@ARM.combool 22610319SAndreas.Sandberg@ARM.comSimpleThread::simPalCheck(int palFunc) 22710319SAndreas.Sandberg@ARM.com{ 22810319SAndreas.Sandberg@ARM.com return true; 22910319SAndreas.Sandberg@ARM.com} 23010319SAndreas.Sandberg@ARM.com#endif 231