simple_thread.cc revision 13759
11388SN/A/* 21388SN/A * Copyright (c) 2018 ARM Limited 31388SN/A * All rights reserved 41388SN/A * 51388SN/A * The license below extends only to copyright in the software and shall 61388SN/A * not be construed as granting a license to any other intellectual 71388SN/A * property including but not limited to intellectual property relating 81388SN/A * to a hardware implementation of the functionality of the software 91388SN/A * licensed hereunder. You may use the software subject to the license 101388SN/A * terms below provided that you ensure that this notice is replicated 111388SN/A * unmodified and in its entirety in all distributions of the software, 121388SN/A * modified or unmodified, in source code or in binary form. 131388SN/A * 141388SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 151388SN/A * All rights reserved. 161388SN/A * 171388SN/A * Redistribution and use in source and binary forms, with or without 181388SN/A * modification, are permitted provided that the following conditions are 191388SN/A * met: redistributions of source code must retain the above copyright 201388SN/A * notice, this list of conditions and the following disclaimer; 211388SN/A * redistributions in binary form must reproduce the above copyright 221388SN/A * notice, this list of conditions and the following disclaimer in the 231388SN/A * documentation and/or other materials provided with the distribution; 241388SN/A * neither the name of the copyright holders nor the names of its 251388SN/A * contributors may be used to endorse or promote products derived from 261388SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 298634Schris.emmons@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301388SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311388SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321388SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331388SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 348634Schris.emmons@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351388SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 368634Schris.emmons@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 378229Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 388229Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 398229Snate@binkert.org * 401388SN/A * Authors: Steve Reinhardt 411388SN/A * Nathan Binkert 425749Scws3k@cs.virginia.edu * Lisa Hsu 435749Scws3k@cs.virginia.edu * Kevin Lim 441388SN/A */ 451388SN/A 461388SN/A#include "cpu/simple_thread.hh" 471388SN/A 481388SN/A#include <string> 491388SN/A 501388SN/A#include "arch/isa_traits.hh" 511388SN/A#include "arch/kernel_stats.hh" 528634Schris.emmons@arm.com#include "arch/stacktrace.hh" 531388SN/A#include "arch/utility.hh" 541388SN/A#include "base/callback.hh" 551388SN/A#include "base/cprintf.hh" 561388SN/A#include "base/output.hh" 571388SN/A#include "base/trace.hh" 585749Scws3k@cs.virginia.edu#include "config/the_isa.hh" 595749Scws3k@cs.virginia.edu#include "cpu/base.hh" 605749Scws3k@cs.virginia.edu#include "cpu/profile.hh" 615749Scws3k@cs.virginia.edu#include "cpu/quiesce_event.hh" 625749Scws3k@cs.virginia.edu#include "cpu/thread_context.hh" 635749Scws3k@cs.virginia.edu#include "mem/fs_translating_port_proxy.hh" 645749Scws3k@cs.virginia.edu#include "mem/se_translating_port_proxy.hh" 655749Scws3k@cs.virginia.edu#include "params/BaseCPU.hh" 665749Scws3k@cs.virginia.edu#include "sim/faults.hh" 675749Scws3k@cs.virginia.edu#include "sim/full_system.hh" 685749Scws3k@cs.virginia.edu#include "sim/process.hh" 695749Scws3k@cs.virginia.edu#include "sim/serialize.hh" 705749Scws3k@cs.virginia.edu#include "sim/sim_exit.hh" 715749Scws3k@cs.virginia.edu#include "sim/system.hh" 725749Scws3k@cs.virginia.edu 735749Scws3k@cs.virginia.eduusing namespace std; 745749Scws3k@cs.virginia.edu 755749Scws3k@cs.virginia.edu// constructor 765749Scws3k@cs.virginia.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 775749Scws3k@cs.virginia.edu Process *_process, BaseTLB *_itb, 785749Scws3k@cs.virginia.edu BaseTLB *_dtb, TheISA::ISA *_isa) 798634Schris.emmons@arm.com : ThreadState(_cpu, _thread_num, _process), isa(_isa), 805749Scws3k@cs.virginia.edu predicate(false), system(_sys), 815749Scws3k@cs.virginia.edu itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa)) 825749Scws3k@cs.virginia.edu{ 835749Scws3k@cs.virginia.edu clearArchRegs(); 845749Scws3k@cs.virginia.edu tc = new ProxyThreadContext<SimpleThread>(this); 858634Schris.emmons@arm.com quiesceEvent = new EndQuiesceEvent(tc); 868634Schris.emmons@arm.com} 875749Scws3k@cs.virginia.edu 885749Scws3k@cs.virginia.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 895749Scws3k@cs.virginia.edu BaseTLB *_itb, BaseTLB *_dtb, 905749Scws3k@cs.virginia.edu TheISA::ISA *_isa, bool use_kernel_stats) 915749Scws3k@cs.virginia.edu : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb), 928634Schris.emmons@arm.com dtb(_dtb), decoder(TheISA::Decoder(_isa)) 938634Schris.emmons@arm.com{ 945749Scws3k@cs.virginia.edu tc = new ProxyThreadContext<SimpleThread>(this); 955749Scws3k@cs.virginia.edu 965749Scws3k@cs.virginia.edu quiesceEvent = new EndQuiesceEvent(tc); 971388SN/A 981388SN/A clearArchRegs(); 998634Schris.emmons@arm.com 1008634Schris.emmons@arm.com if (baseCpu->params()->profile) { 1018634Schris.emmons@arm.com profile = new FunctionProfile(system->kernelSymtab); 1028634Schris.emmons@arm.com Callback *cb = 1038634Schris.emmons@arm.com new MakeCallback<SimpleThread, 1048634Schris.emmons@arm.com &SimpleThread::dumpFuncProfile>(this); 1058634Schris.emmons@arm.com registerExitCallback(cb); 1068634Schris.emmons@arm.com } 1078634Schris.emmons@arm.com 1088634Schris.emmons@arm.com // let's fill with a dummy node for now so we don't get a segfault 1098634Schris.emmons@arm.com // on the first cycle when there's no node available. 1108634Schris.emmons@arm.com static ProfileNode dummyNode; 1118634Schris.emmons@arm.com profileNode = &dummyNode; 1128634Schris.emmons@arm.com profilePC = 3; 1138634Schris.emmons@arm.com 1148634Schris.emmons@arm.com if (use_kernel_stats) 1158634Schris.emmons@arm.com kernelStats = new TheISA::Kernel::Statistics(); 1168634Schris.emmons@arm.com} 1178634Schris.emmons@arm.com 1188634Schris.emmons@arm.comSimpleThread::~SimpleThread() 1198634Schris.emmons@arm.com{ 1208634Schris.emmons@arm.com delete tc; 1218634Schris.emmons@arm.com} 1228634Schris.emmons@arm.com 1238634Schris.emmons@arm.comvoid 1248634Schris.emmons@arm.comSimpleThread::takeOverFrom(ThreadContext *oldContext) 1258634Schris.emmons@arm.com{ 1268634Schris.emmons@arm.com ::takeOverFrom(*tc, *oldContext); 1271388SN/A decoder.takeOverFrom(oldContext->getDecoderPtr()); 1281388SN/A 1291388SN/A kernelStats = oldContext->getKernelStats(); 1301388SN/A funcExeInst = oldContext->readFuncExeInst(); 1311388SN/A storeCondFailures = 0; 1321388SN/A} 1331388SN/A 1348634Schris.emmons@arm.comvoid 1358634Schris.emmons@arm.comSimpleThread::copyState(ThreadContext *oldContext) 1368634Schris.emmons@arm.com{ 1371388SN/A // copy over functional state 1381388SN/A _status = oldContext->status(); 1391388SN/A copyArchRegs(oldContext); 1405749Scws3k@cs.virginia.edu if (FullSystem) 1411388SN/A funcExeInst = oldContext->readFuncExeInst(); 1421388SN/A 1431388SN/A _threadId = oldContext->threadId(); 1441388SN/A _contextId = oldContext->contextId(); 1451388SN/A} 1461388SN/A 1471388SN/Avoid 1489398Sandreas.hansson@arm.comSimpleThread::serialize(CheckpointOut &cp) const 1495749Scws3k@cs.virginia.edu{ 1501388SN/A ThreadState::serialize(cp); 1518634Schris.emmons@arm.com ::serialize(*tc, cp); 1521388SN/A} 1531388SN/A 1541388SN/A 1554840Ssaidi@eecs.umich.eduvoid 1561388SN/ASimpleThread::unserialize(CheckpointIn &cp) 1575749Scws3k@cs.virginia.edu{ 1585749Scws3k@cs.virginia.edu ThreadState::unserialize(cp); 1595749Scws3k@cs.virginia.edu ::unserialize(*tc, cp); 1601388SN/A} 1615749Scws3k@cs.virginia.edu 1625749Scws3k@cs.virginia.eduvoid 1638989SAli.Saidi@ARM.comSimpleThread::startup() 1645749Scws3k@cs.virginia.edu{ 1651388SN/A isa->startup(tc); 1661388SN/A} 1671388SN/A 1681388SN/Avoid 1691388SN/ASimpleThread::dumpFuncProfile() 1708634Schris.emmons@arm.com{ 1711388SN/A OutputStream *os(simout.create(csprintf("profile.%s.dat", baseCpu->name()))); 1725749Scws3k@cs.virginia.edu profile->dump(tc, *os->stream()); 1735749Scws3k@cs.virginia.edu simout.close(os); 1745749Scws3k@cs.virginia.edu} 1751388SN/A 1768634Schris.emmons@arm.comvoid 1778634Schris.emmons@arm.comSimpleThread::activate() 1781388SN/A{ 1791388SN/A if (status() == ThreadContext::Active) 1801388SN/A return; 1818634Schris.emmons@arm.com 1821388SN/A lastActivate = curTick(); 1831388SN/A _status = ThreadContext::Active; 1841388SN/A baseCpu->activateContext(_threadId); 1851388SN/A} 1861388SN/A 1871388SN/Avoid 1881388SN/ASimpleThread::suspend() 1898634Schris.emmons@arm.com{ 1908634Schris.emmons@arm.com if (status() == ThreadContext::Suspended) 1918634Schris.emmons@arm.com return; 1928634Schris.emmons@arm.com 1938634Schris.emmons@arm.com lastActivate = curTick(); 1948634Schris.emmons@arm.com lastSuspend = curTick(); 1958634Schris.emmons@arm.com _status = ThreadContext::Suspended; 1968634Schris.emmons@arm.com baseCpu->suspendContext(_threadId); 1978634Schris.emmons@arm.com} 1988634Schris.emmons@arm.com 1998634Schris.emmons@arm.com 2008634Schris.emmons@arm.comvoid 2018634Schris.emmons@arm.comSimpleThread::halt() 2028634Schris.emmons@arm.com{ 2038634Schris.emmons@arm.com if (status() == ThreadContext::Halted) 2048634Schris.emmons@arm.com return; 2058634Schris.emmons@arm.com 2068634Schris.emmons@arm.com _status = ThreadContext::Halted; 2078634Schris.emmons@arm.com baseCpu->haltContext(_threadId); 2088634Schris.emmons@arm.com} 2098634Schris.emmons@arm.com 2108634Schris.emmons@arm.com 2118634Schris.emmons@arm.comvoid 2128634Schris.emmons@arm.comSimpleThread::regStats(const string &name) 2138634Schris.emmons@arm.com{ 2148634Schris.emmons@arm.com if (FullSystem && kernelStats) 2158634Schris.emmons@arm.com kernelStats->regStats(name + ".kern"); 2168634Schris.emmons@arm.com} 2178634Schris.emmons@arm.com 2188634Schris.emmons@arm.comvoid 2198634Schris.emmons@arm.comSimpleThread::copyArchRegs(ThreadContext *src_tc) 2208634Schris.emmons@arm.com{ 2218634Schris.emmons@arm.com TheISA::copyRegs(src_tc, tc); 2228634Schris.emmons@arm.com} 2238634Schris.emmons@arm.com 2248634Schris.emmons@arm.com// The following methods are defined in src/arch/alpha/ev5.cc for 2258634Schris.emmons@arm.com// Alpha. 2268634Schris.emmons@arm.com#if THE_ISA != ALPHA_ISA 2278634Schris.emmons@arm.comFault 2288634Schris.emmons@arm.comSimpleThread::hwrei() 2298634Schris.emmons@arm.com{ 2308634Schris.emmons@arm.com return NoFault; 2318634Schris.emmons@arm.com} 2328634Schris.emmons@arm.com 2338634Schris.emmons@arm.combool 2348634Schris.emmons@arm.comSimpleThread::simPalCheck(int palFunc) 2358634Schris.emmons@arm.com{ 2369550Sandreas.hansson@arm.com return true; 2378634Schris.emmons@arm.com} 2388634Schris.emmons@arm.com#endif 2399550Sandreas.hansson@arm.com