timing.hh revision 6973 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35#include "cpu/translation.hh"
36
37#include "params/TimingSimpleCPU.hh"
38
39class TimingSimpleCPU : public BaseSimpleCPU
40{
41  public:
42
43    TimingSimpleCPU(TimingSimpleCPUParams * params);
44    virtual ~TimingSimpleCPU();
45
46    virtual void init();
47
48  public:
49    Event *drainEvent;
50
51  private:
52
53    /*
54     * If an access needs to be broken into fragments, currently at most two,
55     * the the following two classes are used as the sender state of the
56     * packets so the CPU can keep track of everything. In the main packet
57     * sender state, there's an array with a spot for each fragment. If a
58     * fragment has already been accepted by the CPU, aka isn't waiting for
59     * a retry, it's pointer is NULL. After each fragment has successfully
60     * been processed, the "outstanding" counter is decremented. Once the
61     * count is zero, the entire larger access is complete.
62     */
63    class SplitMainSenderState : public Packet::SenderState
64    {
65      public:
66        int outstanding;
67        PacketPtr fragments[2];
68
69        int
70        getPendingFragment()
71        {
72            if (fragments[0]) {
73                return 0;
74            } else if (fragments[1]) {
75                return 1;
76            } else {
77                return -1;
78            }
79        }
80    };
81
82    class SplitFragmentSenderState : public Packet::SenderState
83    {
84      public:
85        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
86            bigPkt(_bigPkt), index(_index)
87        {}
88        PacketPtr bigPkt;
89        int index;
90
91        void
92        clearFromParent()
93        {
94            SplitMainSenderState * main_send_state =
95                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
96            main_send_state->fragments[index] = NULL;
97        }
98    };
99
100    class FetchTranslation : public BaseTLB::Translation
101    {
102      protected:
103        TimingSimpleCPU *cpu;
104
105      public:
106        FetchTranslation(TimingSimpleCPU *_cpu)
107            : cpu(_cpu)
108        {}
109
110        void
111        finish(Fault fault, RequestPtr req, ThreadContext *tc,
112               BaseTLB::Mode mode)
113        {
114            cpu->sendFetch(fault, req, tc);
115        }
116    };
117    FetchTranslation fetchTranslation;
118
119    void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
120    void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
121                       uint8_t *data, bool read);
122
123    void translationFault(Fault fault);
124
125    void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
126    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
127            RequestPtr req1, RequestPtr req2, RequestPtr req,
128            uint8_t *data, bool read);
129
130    bool handleReadPacket(PacketPtr pkt);
131    // This function always implicitly uses dcache_pkt.
132    bool handleWritePacket();
133
134    class CpuPort : public Port
135    {
136      protected:
137        TimingSimpleCPU *cpu;
138        Tick lat;
139
140      public:
141
142        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
143            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
144        { }
145
146        bool snoopRangeSent;
147
148      protected:
149
150        virtual Tick recvAtomic(PacketPtr pkt);
151
152        virtual void recvFunctional(PacketPtr pkt);
153
154        virtual void recvStatusChange(Status status);
155
156        virtual void getDeviceAddressRanges(AddrRangeList &resp,
157                                            bool &snoop)
158        { resp.clear(); snoop = false; }
159
160        struct TickEvent : public Event
161        {
162            PacketPtr pkt;
163            TimingSimpleCPU *cpu;
164
165            TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
166            const char *description() const { return "Timing CPU tick"; }
167            void schedule(PacketPtr _pkt, Tick t);
168        };
169
170    };
171
172    class IcachePort : public CpuPort
173    {
174      public:
175
176        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
177            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
178        { }
179
180      protected:
181
182        virtual bool recvTiming(PacketPtr pkt);
183
184        virtual void recvRetry();
185
186        struct ITickEvent : public TickEvent
187        {
188
189            ITickEvent(TimingSimpleCPU *_cpu)
190                : TickEvent(_cpu) {}
191            void process();
192            const char *description() const { return "Timing CPU icache tick"; }
193        };
194
195        ITickEvent tickEvent;
196
197    };
198
199    class DcachePort : public CpuPort
200    {
201      public:
202
203        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
204            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
205        { }
206
207        virtual void setPeer(Port *port);
208
209      protected:
210
211        virtual bool recvTiming(PacketPtr pkt);
212
213        virtual void recvRetry();
214
215        struct DTickEvent : public TickEvent
216        {
217            DTickEvent(TimingSimpleCPU *_cpu)
218                : TickEvent(_cpu) {}
219            void process();
220            const char *description() const { return "Timing CPU dcache tick"; }
221        };
222
223        DTickEvent tickEvent;
224
225    };
226
227    IcachePort icachePort;
228    DcachePort dcachePort;
229
230    PacketPtr ifetch_pkt;
231    PacketPtr dcache_pkt;
232
233    Tick previousTick;
234
235  public:
236
237    virtual Port *getPort(const std::string &if_name, int idx = -1);
238
239    virtual void serialize(std::ostream &os);
240    virtual void unserialize(Checkpoint *cp, const std::string &section);
241
242    virtual unsigned int drain(Event *drain_event);
243    virtual void resume();
244
245    void switchOut();
246    void takeOverFrom(BaseCPU *oldCPU);
247
248    virtual void activateContext(int thread_num, int delay);
249    virtual void suspendContext(int thread_num);
250
251    template <class T>
252    Fault read(Addr addr, T &data, unsigned flags);
253
254    template <class T>
255    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
256
257    void fetch();
258    void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
259    void completeIfetch(PacketPtr );
260    void completeDataAccess(PacketPtr pkt);
261    void advanceInst(Fault fault);
262
263    /**
264     * Print state of address in memory system via PrintReq (for
265     * debugging).
266     */
267    void printAddr(Addr a);
268
269    /**
270     * Finish a DTB translation.
271     * @param state The DTB translation state.
272     */
273    void finishTranslation(WholeTranslationState *state);
274
275  private:
276
277    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
278    FetchEvent fetchEvent;
279
280    struct IprEvent : Event {
281        Packet *pkt;
282        TimingSimpleCPU *cpu;
283        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
284        virtual void process();
285        virtual const char *description() const;
286    };
287
288    void completeDrain();
289};
290
291#endif // __CPU_SIMPLE_TIMING_HH__
292