timing.hh revision 5894 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40  public:
41
42    TimingSimpleCPU(TimingSimpleCPUParams * params);
43    virtual ~TimingSimpleCPU();
44
45    virtual void init();
46
47  public:
48    Event *drainEvent;
49
50  private:
51
52    /*
53     * If an access needs to be broken into fragments, currently at most two,
54     * the the following two classes are used as the sender state of the
55     * packets so the CPU can keep track of everything. In the main packet
56     * sender state, there's an array with a spot for each fragment. If a
57     * fragment has already been accepted by the CPU, aka isn't waiting for
58     * a retry, it's pointer is NULL. After each fragment has successfully
59     * been processed, the "outstanding" counter is decremented. Once the
60     * count is zero, the entire larger access is complete.
61     */
62    class SplitMainSenderState : public Packet::SenderState
63    {
64      public:
65        int outstanding;
66        PacketPtr fragments[2];
67
68        int
69        getPendingFragment()
70        {
71            if (fragments[0]) {
72                return 0;
73            } else if (fragments[1]) {
74                return 1;
75            } else {
76                return -1;
77            }
78        }
79    };
80
81    class SplitFragmentSenderState : public Packet::SenderState
82    {
83      public:
84        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85            bigPkt(_bigPkt), index(_index)
86        {}
87        PacketPtr bigPkt;
88        int index;
89
90        void
91        clearFromParent()
92        {
93            SplitMainSenderState * main_send_state =
94                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95            main_send_state->fragments[index] = NULL;
96        }
97    };
98
99    class FetchTranslation : public BaseTLB::Translation
100    {
101      protected:
102        TimingSimpleCPU *cpu;
103
104      public:
105        FetchTranslation(TimingSimpleCPU *_cpu) : cpu(_cpu)
106        {}
107
108        void finish(Fault fault, RequestPtr req,
109                ThreadContext *tc, bool write)
110        {
111            cpu->sendFetch(fault, req, tc);
112        }
113    };
114    FetchTranslation fetchTranslation;
115
116    class DataTranslation : public BaseTLB::Translation
117    {
118      protected:
119        TimingSimpleCPU *cpu;
120        uint8_t *data;
121        uint64_t *res;
122        bool read;
123
124      public:
125        DataTranslation(TimingSimpleCPU *_cpu,
126                uint8_t *_data, uint64_t *_res, bool _read) :
127            cpu(_cpu), data(_data), res(_res), read(_read)
128        {}
129
130        void
131        finish(Fault fault, RequestPtr req,
132                ThreadContext *tc, bool write)
133        {
134            cpu->sendData(fault, req, data, res, read);
135            delete this;
136        }
137    };
138
139    class SplitDataTranslation : public BaseTLB::Translation
140    {
141      public:
142        struct WholeTranslationState
143        {
144          public:
145            int outstanding;
146            RequestPtr requests[2];
147            RequestPtr mainReq;
148            Fault faults[2];
149            uint8_t *data;
150            bool read;
151
152            WholeTranslationState(RequestPtr req1, RequestPtr req2,
153                    RequestPtr main, uint8_t *_data, bool _read)
154            {
155                outstanding = 2;
156                requests[0] = req1;
157                requests[1] = req2;
158                mainReq = main;
159                faults[0] = faults[1] = NoFault;
160                data = _data;
161                read = _read;
162            }
163        };
164
165        TimingSimpleCPU *cpu;
166        int index;
167        WholeTranslationState *state;
168
169        SplitDataTranslation(TimingSimpleCPU *_cpu, int _index,
170                WholeTranslationState *_state) :
171            cpu(_cpu), index(_index), state(_state)
172        {}
173
174        void
175        finish(Fault fault, RequestPtr req,
176                ThreadContext *tc, bool write)
177        {
178            assert(state);
179            assert(state->outstanding);
180            state->faults[index] = fault;
181            if (--state->outstanding == 0) {
182                cpu->sendSplitData(state->faults[0],
183                                   state->faults[1],
184                                   state->requests[0],
185                                   state->requests[1],
186                                   state->mainReq,
187                                   state->data,
188                                   state->read);
189                delete state;
190            }
191            delete this;
192        }
193    };
194
195    void sendData(Fault fault, RequestPtr req,
196            uint8_t *data, uint64_t *res, bool read);
197    void sendSplitData(Fault fault1, Fault fault2,
198            RequestPtr req1, RequestPtr req2, RequestPtr req,
199            uint8_t *data, bool read);
200
201    void translationFault(Fault fault);
202
203    void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
204    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
205            RequestPtr req1, RequestPtr req2, RequestPtr req,
206            uint8_t *data, bool read);
207
208    bool handleReadPacket(PacketPtr pkt);
209    // This function always implicitly uses dcache_pkt.
210    bool handleWritePacket();
211
212    class CpuPort : public Port
213    {
214      protected:
215        TimingSimpleCPU *cpu;
216        Tick lat;
217
218      public:
219
220        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
221            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
222        { }
223
224        bool snoopRangeSent;
225
226      protected:
227
228        virtual Tick recvAtomic(PacketPtr pkt);
229
230        virtual void recvFunctional(PacketPtr pkt);
231
232        virtual void recvStatusChange(Status status);
233
234        virtual void getDeviceAddressRanges(AddrRangeList &resp,
235                                            bool &snoop)
236        { resp.clear(); snoop = false; }
237
238        struct TickEvent : public Event
239        {
240            PacketPtr pkt;
241            TimingSimpleCPU *cpu;
242
243            TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
244            const char *description() const { return "Timing CPU tick"; }
245            void schedule(PacketPtr _pkt, Tick t);
246        };
247
248    };
249
250    class IcachePort : public CpuPort
251    {
252      public:
253
254        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
255            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
256        { }
257
258      protected:
259
260        virtual bool recvTiming(PacketPtr pkt);
261
262        virtual void recvRetry();
263
264        struct ITickEvent : public TickEvent
265        {
266
267            ITickEvent(TimingSimpleCPU *_cpu)
268                : TickEvent(_cpu) {}
269            void process();
270            const char *description() const { return "Timing CPU icache tick"; }
271        };
272
273        ITickEvent tickEvent;
274
275    };
276
277    class DcachePort : public CpuPort
278    {
279      public:
280
281        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
282            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
283        { }
284
285        virtual void setPeer(Port *port);
286
287      protected:
288
289        virtual bool recvTiming(PacketPtr pkt);
290
291        virtual void recvRetry();
292
293        struct DTickEvent : public TickEvent
294        {
295            DTickEvent(TimingSimpleCPU *_cpu)
296                : TickEvent(_cpu) {}
297            void process();
298            const char *description() const { return "Timing CPU dcache tick"; }
299        };
300
301        DTickEvent tickEvent;
302
303    };
304
305    IcachePort icachePort;
306    DcachePort dcachePort;
307
308    PacketPtr ifetch_pkt;
309    PacketPtr dcache_pkt;
310
311    Tick previousTick;
312
313  public:
314
315    virtual Port *getPort(const std::string &if_name, int idx = -1);
316
317    virtual void serialize(std::ostream &os);
318    virtual void unserialize(Checkpoint *cp, const std::string &section);
319
320    virtual unsigned int drain(Event *drain_event);
321    virtual void resume();
322
323    void switchOut();
324    void takeOverFrom(BaseCPU *oldCPU);
325
326    virtual void activateContext(int thread_num, int delay);
327    virtual void suspendContext(int thread_num);
328
329    template <class T>
330    Fault read(Addr addr, T &data, unsigned flags);
331
332    template <class T>
333    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
334
335    void fetch();
336    void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
337    void completeIfetch(PacketPtr );
338    void completeDataAccess(PacketPtr pkt);
339    void advanceInst(Fault fault);
340
341    /**
342     * Print state of address in memory system via PrintReq (for
343     * debugging).
344     */
345    void printAddr(Addr a);
346
347  private:
348
349    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
350    FetchEvent fetchEvent;
351
352    struct IprEvent : Event {
353        Packet *pkt;
354        TimingSimpleCPU *cpu;
355        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
356        virtual void process();
357        virtual const char *description() const;
358    };
359
360    void completeDrain();
361};
362
363#endif // __CPU_SIMPLE_TIMING_HH__
364