timing.hh revision 5890:bdef71accd68 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40  public:
41
42    TimingSimpleCPU(TimingSimpleCPUParams * params);
43    virtual ~TimingSimpleCPU();
44
45    virtual void init();
46
47  public:
48    Event *drainEvent;
49
50  private:
51
52    /*
53     * If an access needs to be broken into fragments, currently at most two,
54     * the the following two classes are used as the sender state of the
55     * packets so the CPU can keep track of everything. In the main packet
56     * sender state, there's an array with a spot for each fragment. If a
57     * fragment has already been accepted by the CPU, aka isn't waiting for
58     * a retry, it's pointer is NULL. After each fragment has successfully
59     * been processed, the "outstanding" counter is decremented. Once the
60     * count is zero, the entire larger access is complete.
61     */
62    class SplitMainSenderState : public Packet::SenderState
63    {
64      public:
65        int outstanding;
66        PacketPtr fragments[2];
67
68        int
69        getPendingFragment()
70        {
71            if (fragments[0]) {
72                return 0;
73            } else if (fragments[1]) {
74                return 1;
75            } else {
76                return -1;
77            }
78        }
79    };
80
81    class SplitFragmentSenderState : public Packet::SenderState
82    {
83      public:
84        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85            bigPkt(_bigPkt), index(_index)
86        {}
87        PacketPtr bigPkt;
88        int index;
89
90        void
91        clearFromParent()
92        {
93            SplitMainSenderState * main_send_state =
94                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95            main_send_state->fragments[index] = NULL;
96        }
97    };
98
99    Fault buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, RequestPtr &req,
100            Addr split_addr, uint8_t *data, bool read);
101    Fault buildPacket(PacketPtr &pkt, RequestPtr &req, bool read);
102
103    bool handleReadPacket(PacketPtr pkt);
104    // This function always implicitly uses dcache_pkt.
105    bool handleWritePacket();
106
107    class CpuPort : public Port
108    {
109      protected:
110        TimingSimpleCPU *cpu;
111        Tick lat;
112
113      public:
114
115        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
116            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
117        { }
118
119        bool snoopRangeSent;
120
121      protected:
122
123        virtual Tick recvAtomic(PacketPtr pkt);
124
125        virtual void recvFunctional(PacketPtr pkt);
126
127        virtual void recvStatusChange(Status status);
128
129        virtual void getDeviceAddressRanges(AddrRangeList &resp,
130                                            bool &snoop)
131        { resp.clear(); snoop = false; }
132
133        struct TickEvent : public Event
134        {
135            PacketPtr pkt;
136            TimingSimpleCPU *cpu;
137
138            TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
139            const char *description() const { return "Timing CPU tick"; }
140            void schedule(PacketPtr _pkt, Tick t);
141        };
142
143    };
144
145    class IcachePort : public CpuPort
146    {
147      public:
148
149        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
150            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
151        { }
152
153      protected:
154
155        virtual bool recvTiming(PacketPtr pkt);
156
157        virtual void recvRetry();
158
159        struct ITickEvent : public TickEvent
160        {
161
162            ITickEvent(TimingSimpleCPU *_cpu)
163                : TickEvent(_cpu) {}
164            void process();
165            const char *description() const { return "Timing CPU icache tick"; }
166        };
167
168        ITickEvent tickEvent;
169
170    };
171
172    class DcachePort : public CpuPort
173    {
174      public:
175
176        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
177            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
178        { }
179
180        virtual void setPeer(Port *port);
181
182      protected:
183
184        virtual bool recvTiming(PacketPtr pkt);
185
186        virtual void recvRetry();
187
188        struct DTickEvent : public TickEvent
189        {
190            DTickEvent(TimingSimpleCPU *_cpu)
191                : TickEvent(_cpu) {}
192            void process();
193            const char *description() const { return "Timing CPU dcache tick"; }
194        };
195
196        DTickEvent tickEvent;
197
198    };
199
200    IcachePort icachePort;
201    DcachePort dcachePort;
202
203    PacketPtr ifetch_pkt;
204    PacketPtr dcache_pkt;
205
206    Tick previousTick;
207
208  public:
209
210    virtual Port *getPort(const std::string &if_name, int idx = -1);
211
212    virtual void serialize(std::ostream &os);
213    virtual void unserialize(Checkpoint *cp, const std::string &section);
214
215    virtual unsigned int drain(Event *drain_event);
216    virtual void resume();
217
218    void switchOut();
219    void takeOverFrom(BaseCPU *oldCPU);
220
221    virtual void activateContext(int thread_num, int delay);
222    virtual void suspendContext(int thread_num);
223
224    template <class T>
225    Fault read(Addr addr, T &data, unsigned flags);
226
227    template <class T>
228    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
229
230    void fetch();
231    void completeIfetch(PacketPtr );
232    void completeDataAccess(PacketPtr );
233    void advanceInst(Fault fault);
234
235    /**
236     * Print state of address in memory system via PrintReq (for
237     * debugging).
238     */
239    void printAddr(Addr a);
240
241  private:
242
243    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
244    FetchEvent fetchEvent;
245
246    struct IprEvent : Event {
247        Packet *pkt;
248        TimingSimpleCPU *cpu;
249        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
250        virtual void process();
251        virtual const char *description() const;
252    };
253
254    void completeDrain();
255};
256
257#endif // __CPU_SIMPLE_TIMING_HH__
258