timing.hh revision 5169:bfd18d401251
12689Sktlim@umich.edu/* 22689Sktlim@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32689Sktlim@umich.edu * All rights reserved. 42689Sktlim@umich.edu * 52689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 62689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 72689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 82689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 92689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 102689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 112689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 122689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 132689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 142689Sktlim@umich.edu * this software without specific prior written permission. 152689Sktlim@umich.edu * 162689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Steve Reinhardt 292689Sktlim@umich.edu */ 302290SN/A 313368Sstever@eecs.umich.edu#ifndef __CPU_SIMPLE_TIMING_HH__ 322680Sktlim@umich.edu#define __CPU_SIMPLE_TIMING_HH__ 332290SN/A 342290SN/A#include "cpu/simple/base.hh" 352680Sktlim@umich.edu 362680Sktlim@umich.educlass TimingSimpleCPU : public BaseSimpleCPU 372290SN/A{ 382290SN/A public: 392290SN/A 402290SN/A struct Params : public BaseSimpleCPU::Params { 412290SN/A }; 422290SN/A 433368Sstever@eecs.umich.edu TimingSimpleCPU(Params *params); 442680Sktlim@umich.edu virtual ~TimingSimpleCPU(); 452290SN/A 462290SN/A virtual void init(); 472290SN/A 482290SN/A public: 492290SN/A // 504873Sstever@eecs.umich.edu enum Status { 512290SN/A Idle, 52 Running, 53 IcacheRetry, 54 IcacheWaitResponse, 55 IcacheWaitSwitch, 56 DcacheRetry, 57 DcacheWaitResponse, 58 DcacheWaitSwitch, 59 SwitchedOut 60 }; 61 62 protected: 63 Status _status; 64 65 Status status() const { return _status; } 66 67 Event *drainEvent; 68 69 private: 70 71 class CpuPort : public Port 72 { 73 protected: 74 TimingSimpleCPU *cpu; 75 Tick lat; 76 77 public: 78 79 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 80 : Port(_name, _cpu), cpu(_cpu), lat(_lat) 81 { } 82 83 bool snoopRangeSent; 84 85 protected: 86 87 virtual Tick recvAtomic(PacketPtr pkt); 88 89 virtual void recvFunctional(PacketPtr pkt); 90 91 virtual void recvStatusChange(Status status); 92 93 virtual void getDeviceAddressRanges(AddrRangeList &resp, 94 bool &snoop) 95 { resp.clear(); snoop = false; } 96 97 struct TickEvent : public Event 98 { 99 PacketPtr pkt; 100 TimingSimpleCPU *cpu; 101 102 TickEvent(TimingSimpleCPU *_cpu) 103 :Event(&mainEventQueue), cpu(_cpu) {} 104 const char *description() { return "Timing CPU tick"; } 105 void schedule(PacketPtr _pkt, Tick t); 106 }; 107 108 }; 109 110 class IcachePort : public CpuPort 111 { 112 public: 113 114 IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 115 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 116 { } 117 118 protected: 119 120 virtual bool recvTiming(PacketPtr pkt); 121 122 virtual void recvRetry(); 123 124 struct ITickEvent : public TickEvent 125 { 126 127 ITickEvent(TimingSimpleCPU *_cpu) 128 : TickEvent(_cpu) {} 129 void process(); 130 const char *description() { return "Timing CPU icache tick"; } 131 }; 132 133 ITickEvent tickEvent; 134 135 }; 136 137 class DcachePort : public CpuPort 138 { 139 public: 140 141 DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 142 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 143 { } 144 145 virtual void setPeer(Port *port); 146 147 protected: 148 149 virtual bool recvTiming(PacketPtr pkt); 150 151 virtual void recvRetry(); 152 153 struct DTickEvent : public TickEvent 154 { 155 DTickEvent(TimingSimpleCPU *_cpu) 156 : TickEvent(_cpu) {} 157 void process(); 158 const char *description() { return "Timing CPU dcache tick"; } 159 }; 160 161 DTickEvent tickEvent; 162 163 }; 164 165 IcachePort icachePort; 166 DcachePort dcachePort; 167 168 PacketPtr ifetch_pkt; 169 PacketPtr dcache_pkt; 170 171 Tick previousTick; 172 173 public: 174 175 virtual Port *getPort(const std::string &if_name, int idx = -1); 176 177 virtual void serialize(std::ostream &os); 178 virtual void unserialize(Checkpoint *cp, const std::string §ion); 179 180 virtual unsigned int drain(Event *drain_event); 181 virtual void resume(); 182 183 void switchOut(); 184 void takeOverFrom(BaseCPU *oldCPU); 185 186 virtual void activateContext(int thread_num, int delay); 187 virtual void suspendContext(int thread_num); 188 189 template <class T> 190 Fault read(Addr addr, T &data, unsigned flags); 191 192 template <class T> 193 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 194 195 void fetch(); 196 void completeIfetch(PacketPtr ); 197 void completeDataAccess(PacketPtr ); 198 void advanceInst(Fault fault); 199 200 private: 201 202 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 203 FetchEvent *fetchEvent; 204 205 struct IprEvent : Event { 206 Packet *pkt; 207 TimingSimpleCPU *cpu; 208 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 209 virtual void process(); 210 virtual const char *description(); 211 }; 212 213 void completeDrain(); 214}; 215 216#endif // __CPU_SIMPLE_TIMING_HH__ 217