timing.hh revision 5103:391933804192
16019Shines@cs.fsu.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 37093Sgblack@eecs.umich.edu * All rights reserved. 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67093Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77093Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97093Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117093Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127093Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137093Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Steve Reinhardt 296019Shines@cs.fsu.edu */ 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.edu#ifndef __CPU_SIMPLE_TIMING_HH__ 326019Shines@cs.fsu.edu#define __CPU_SIMPLE_TIMING_HH__ 336019Shines@cs.fsu.edu 346019Shines@cs.fsu.edu#include "cpu/simple/base.hh" 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.educlass TimingSimpleCPU : public BaseSimpleCPU 376019Shines@cs.fsu.edu{ 386019Shines@cs.fsu.edu public: 396019Shines@cs.fsu.edu 406019Shines@cs.fsu.edu struct Params : public BaseSimpleCPU::Params { 416735Sgblack@eecs.umich.edu }; 426735Sgblack@eecs.umich.edu 436019Shines@cs.fsu.edu TimingSimpleCPU(Params *params); 446019Shines@cs.fsu.edu virtual ~TimingSimpleCPU(); 456019Shines@cs.fsu.edu 468229Snate@binkert.org virtual void init(); 478229Snate@binkert.org 486019Shines@cs.fsu.edu public: 498232Snate@binkert.org // 508782Sgblack@eecs.umich.edu enum Status { 516019Shines@cs.fsu.edu Idle, 526019Shines@cs.fsu.edu Running, 536019Shines@cs.fsu.edu IcacheRetry, 546019Shines@cs.fsu.edu IcacheWaitResponse, 557362Sgblack@eecs.umich.edu IcacheWaitSwitch, 566735Sgblack@eecs.umich.edu DcacheRetry, 576019Shines@cs.fsu.edu DcacheWaitResponse, 587362Sgblack@eecs.umich.edu DcacheWaitSwitch, 596735Sgblack@eecs.umich.edu SwitchedOut 606019Shines@cs.fsu.edu }; 617362Sgblack@eecs.umich.edu 626735Sgblack@eecs.umich.edu protected: 636019Shines@cs.fsu.edu Status _status; 647362Sgblack@eecs.umich.edu 656735Sgblack@eecs.umich.edu Status status() const { return _status; } 666019Shines@cs.fsu.edu 677362Sgblack@eecs.umich.edu Event *drainEvent; 686735Sgblack@eecs.umich.edu 696019Shines@cs.fsu.edu private: 707362Sgblack@eecs.umich.edu 716735Sgblack@eecs.umich.edu class CpuPort : public Port 726019Shines@cs.fsu.edu { 737362Sgblack@eecs.umich.edu protected: 746735Sgblack@eecs.umich.edu TimingSimpleCPU *cpu; 756019Shines@cs.fsu.edu Tick lat; 767652Sminkyu.jeong@arm.com 777652Sminkyu.jeong@arm.com public: 787652Sminkyu.jeong@arm.com 798518Sgeoffrey.blake@arm.com CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 808518Sgeoffrey.blake@arm.com : Port(_name, _cpu), cpu(_cpu), lat(_lat) 816735Sgblack@eecs.umich.edu { } 827362Sgblack@eecs.umich.edu 836735Sgblack@eecs.umich.edu bool snoopRangeSent; 846735Sgblack@eecs.umich.edu 856019Shines@cs.fsu.edu protected: 866735Sgblack@eecs.umich.edu 877400SAli.Saidi@ARM.com virtual Tick recvAtomic(PacketPtr pkt); 886735Sgblack@eecs.umich.edu 896735Sgblack@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 906735Sgblack@eecs.umich.edu 917400SAli.Saidi@ARM.com virtual void recvStatusChange(Status status); 926735Sgblack@eecs.umich.edu 936735Sgblack@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 946735Sgblack@eecs.umich.edu bool &snoop) 956019Shines@cs.fsu.edu { resp.clear(); snoop = false; } 966019Shines@cs.fsu.edu 976019Shines@cs.fsu.edu struct TickEvent : public Event 986735Sgblack@eecs.umich.edu { 997678Sgblack@eecs.umich.edu PacketPtr pkt; 1006019Shines@cs.fsu.edu TimingSimpleCPU *cpu; 1016735Sgblack@eecs.umich.edu 1026735Sgblack@eecs.umich.edu TickEvent(TimingSimpleCPU *_cpu) 1038782Sgblack@eecs.umich.edu :Event(&mainEventQueue), cpu(_cpu) {} 1048782Sgblack@eecs.umich.edu const char *description() { return "Timing CPU tick"; } 1056735Sgblack@eecs.umich.edu void schedule(PacketPtr _pkt, Tick t); 1066019Shines@cs.fsu.edu }; 1076735Sgblack@eecs.umich.edu 1086735Sgblack@eecs.umich.edu }; 1098303SAli.Saidi@ARM.com 1108303SAli.Saidi@ARM.com class IcachePort : public CpuPort 1118303SAli.Saidi@ARM.com { 1128303SAli.Saidi@ARM.com public: 1138303SAli.Saidi@ARM.com 1148303SAli.Saidi@ARM.com IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1157720Sgblack@eecs.umich.edu : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 1168205SAli.Saidi@ARM.com { } 1178205SAli.Saidi@ARM.com 1188205SAli.Saidi@ARM.com protected: 1196735Sgblack@eecs.umich.edu 1206735Sgblack@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1216735Sgblack@eecs.umich.edu 1226735Sgblack@eecs.umich.edu virtual void recvRetry(); 1236735Sgblack@eecs.umich.edu 1247093Sgblack@eecs.umich.edu struct ITickEvent : public TickEvent 1256735Sgblack@eecs.umich.edu { 1266735Sgblack@eecs.umich.edu 1276735Sgblack@eecs.umich.edu ITickEvent(TimingSimpleCPU *_cpu) 1287302Sgblack@eecs.umich.edu : TickEvent(_cpu) {} 1296735Sgblack@eecs.umich.edu void process(); 1308518Sgeoffrey.blake@arm.com const char *description() { return "Timing CPU icache tick"; } 1318518Sgeoffrey.blake@arm.com }; 1327720Sgblack@eecs.umich.edu 1336735Sgblack@eecs.umich.edu ITickEvent tickEvent; 1346735Sgblack@eecs.umich.edu 1356735Sgblack@eecs.umich.edu }; 1366735Sgblack@eecs.umich.edu 1376735Sgblack@eecs.umich.edu class DcachePort : public CpuPort 1386735Sgblack@eecs.umich.edu { 1396735Sgblack@eecs.umich.edu public: 1406735Sgblack@eecs.umich.edu 1416735Sgblack@eecs.umich.edu DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1426735Sgblack@eecs.umich.edu : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 1436735Sgblack@eecs.umich.edu { } 1446735Sgblack@eecs.umich.edu 1456735Sgblack@eecs.umich.edu virtual void setPeer(Port *port); 1466735Sgblack@eecs.umich.edu 1476735Sgblack@eecs.umich.edu protected: 1486735Sgblack@eecs.umich.edu 1496735Sgblack@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1506735Sgblack@eecs.umich.edu 1516735Sgblack@eecs.umich.edu virtual void recvRetry(); 1526735Sgblack@eecs.umich.edu 1537093Sgblack@eecs.umich.edu struct DTickEvent : public TickEvent 1547093Sgblack@eecs.umich.edu { 1557720Sgblack@eecs.umich.edu DTickEvent(TimingSimpleCPU *_cpu) 1567585SAli.Saidi@arm.com : TickEvent(_cpu) {} 1577720Sgblack@eecs.umich.edu void process(); 1587720Sgblack@eecs.umich.edu const char *description() { return "Timing CPU dcache tick"; } 1597720Sgblack@eecs.umich.edu }; 1607720Sgblack@eecs.umich.edu 1617720Sgblack@eecs.umich.edu DTickEvent tickEvent; 1627720Sgblack@eecs.umich.edu 1637720Sgblack@eecs.umich.edu }; 1646019Shines@cs.fsu.edu 1657189Sgblack@eecs.umich.edu IcachePort icachePort; 1667400SAli.Saidi@ARM.com DcachePort dcachePort; 1677678Sgblack@eecs.umich.edu 1687400SAli.Saidi@ARM.com PacketPtr ifetch_pkt; 1698782Sgblack@eecs.umich.edu PacketPtr dcache_pkt; 1708782Sgblack@eecs.umich.edu 1718782Sgblack@eecs.umich.edu int cpu_id; 1728782Sgblack@eecs.umich.edu Tick previousTick; 1738205SAli.Saidi@ARM.com 1747400SAli.Saidi@ARM.com public: 1757400SAli.Saidi@ARM.com 1767189Sgblack@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 1777678Sgblack@eecs.umich.edu 1787189Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 1798782Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1808782Sgblack@eecs.umich.edu 1818806Sgblack@eecs.umich.edu virtual unsigned int drain(Event *drain_event); 1828806Sgblack@eecs.umich.edu virtual void resume(); 1838806Sgblack@eecs.umich.edu 1848806Sgblack@eecs.umich.edu void switchOut(); 1858806Sgblack@eecs.umich.edu void takeOverFrom(BaseCPU *oldCPU); 1868806Sgblack@eecs.umich.edu 1878806Sgblack@eecs.umich.edu virtual void activateContext(int thread_num, int delay); 1888806Sgblack@eecs.umich.edu virtual void suspendContext(int thread_num); 1898806Sgblack@eecs.umich.edu 1908806Sgblack@eecs.umich.edu template <class T> 1918806Sgblack@eecs.umich.edu Fault read(Addr addr, T &data, unsigned flags); 1927189Sgblack@eecs.umich.edu 1938806Sgblack@eecs.umich.edu template <class T> 1948806Sgblack@eecs.umich.edu Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1957189Sgblack@eecs.umich.edu 1967189Sgblack@eecs.umich.edu void fetch(); 1977189Sgblack@eecs.umich.edu void completeIfetch(PacketPtr ); 1987197Sgblack@eecs.umich.edu void completeDataAccess(PacketPtr ); 1997678Sgblack@eecs.umich.edu void advanceInst(Fault fault); 2007197Sgblack@eecs.umich.edu 2018782Sgblack@eecs.umich.edu private: 2028782Sgblack@eecs.umich.edu 2038806Sgblack@eecs.umich.edu typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 2048806Sgblack@eecs.umich.edu FetchEvent *fetchEvent; 2057197Sgblack@eecs.umich.edu 2068806Sgblack@eecs.umich.edu struct IprEvent : Event { 2078806Sgblack@eecs.umich.edu Packet *pkt; 2088806Sgblack@eecs.umich.edu TimingSimpleCPU *cpu; 2098806Sgblack@eecs.umich.edu IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 2108806Sgblack@eecs.umich.edu virtual void process(); 2118806Sgblack@eecs.umich.edu virtual const char *description(); 2128806Sgblack@eecs.umich.edu }; 2138806Sgblack@eecs.umich.edu 2148806Sgblack@eecs.umich.edu void completeDrain(); 2158806Sgblack@eecs.umich.edu}; 2168806Sgblack@eecs.umich.edu 2177197Sgblack@eecs.umich.edu#endif // __CPU_SIMPLE_TIMING_HH__ 2187197Sgblack@eecs.umich.edu