timing.hh revision 4192:7accc6365bb9
12036SN/A/* 22036SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32036SN/A * All rights reserved. 42036SN/A * 52036SN/A * Redistribution and use in source and binary forms, with or without 62036SN/A * modification, are permitted provided that the following conditions are 72036SN/A * met: redistributions of source code must retain the above copyright 82036SN/A * notice, this list of conditions and the following disclaimer; 92036SN/A * redistributions in binary form must reproduce the above copyright 102036SN/A * notice, this list of conditions and the following disclaimer in the 112036SN/A * documentation and/or other materials provided with the distribution; 122036SN/A * neither the name of the copyright holders nor the names of its 132036SN/A * contributors may be used to endorse or promote products derived from 142036SN/A * this software without specific prior written permission. 152036SN/A * 162036SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172036SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182036SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192036SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202036SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212036SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222036SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232036SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242036SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252036SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262036SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282956Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 292956Sgblack@eecs.umich.edu */ 302772Ssaidi@eecs.umich.edu 312036SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 322036SN/A#define __CPU_SIMPLE_TIMING_HH__ 332036SN/A 342036SN/A#include "cpu/simple/base.hh" 352036SN/A 362036SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 372036SN/A{ 382036SN/A public: 392036SN/A 402779Sbinkertn@umich.edu struct Params : public BaseSimpleCPU::Params { 412036SN/A }; 422036SN/A 432036SN/A TimingSimpleCPU(Params *params); 442036SN/A virtual ~TimingSimpleCPU(); 452036SN/A 462565SN/A virtual void init(); 472565SN/A 482565SN/A public: 492565SN/A // 503483Ssaidi@eecs.umich.edu enum Status { 513483Ssaidi@eecs.umich.edu Idle, 522036SN/A Running, 532036SN/A IcacheRetry, 542036SN/A IcacheWaitResponse, 552036SN/A IcacheWaitSwitch, 562778Ssaidi@eecs.umich.edu DcacheRetry, 572778Ssaidi@eecs.umich.edu DcacheWaitResponse, 582778Ssaidi@eecs.umich.edu DcacheWaitSwitch, 592778Ssaidi@eecs.umich.edu SwitchedOut 603799Sgblack@eecs.umich.edu }; 613799Sgblack@eecs.umich.edu 622036SN/A protected: 632036SN/A Status _status; 642036SN/A 652036SN/A Status status() const { return _status; } 662036SN/A 672565SN/A Event *drainEvent; 682565SN/A 692778Ssaidi@eecs.umich.edu Event *fetchEvent; 702778Ssaidi@eecs.umich.edu 712565SN/A private: 722036SN/A 732036SN/A class CpuPort : public Port 742036SN/A { 752036SN/A protected: 762036SN/A TimingSimpleCPU *cpu; 772036SN/A Tick lat; 782036SN/A 792036SN/A public: 802565SN/A 812036SN/A CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 822036SN/A : Port(_name, _cpu), cpu(_cpu), lat(_lat) 832036SN/A { } 842036SN/A 852036SN/A bool snoopRangeSent; 862565SN/A 872565SN/A protected: 882778Ssaidi@eecs.umich.edu 892778Ssaidi@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 902565SN/A 912036SN/A virtual void recvFunctional(PacketPtr pkt); 922036SN/A 932036SN/A virtual void recvStatusChange(Status status); 942565SN/A 952036SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 962036SN/A AddrRangeList &snoop) 972036SN/A { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } 982036SN/A 992036SN/A struct TickEvent : public Event 1002565SN/A { 1012565SN/A PacketPtr pkt; 1022778Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 1032778Ssaidi@eecs.umich.edu 1042565SN/A TickEvent(TimingSimpleCPU *_cpu) 1052036SN/A :Event(&mainEventQueue), cpu(_cpu) {} 1062036SN/A const char *description() { return "Timing CPU clock event"; } 1072565SN/A void schedule(PacketPtr _pkt, Tick t); 1082036SN/A }; 1092036SN/A 1102764Sstever@eecs.umich.edu }; 1112764Sstever@eecs.umich.edu 1122764Sstever@eecs.umich.edu class IcachePort : public CpuPort 1132764Sstever@eecs.umich.edu { 1142764Sstever@eecs.umich.edu public: 1152764Sstever@eecs.umich.edu 1162764Sstever@eecs.umich.edu IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1172764Sstever@eecs.umich.edu : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 1182764Sstever@eecs.umich.edu { } 1192764Sstever@eecs.umich.edu 1202764Sstever@eecs.umich.edu protected: 1212764Sstever@eecs.umich.edu 1222764Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1232764Sstever@eecs.umich.edu 1242764Sstever@eecs.umich.edu virtual void recvRetry(); 1252764Sstever@eecs.umich.edu 1262764Sstever@eecs.umich.edu struct ITickEvent : public TickEvent 1272036SN/A { 1282036SN/A 1292036SN/A ITickEvent(TimingSimpleCPU *_cpu) 1302036SN/A : TickEvent(_cpu) {} 1312036SN/A void process(); 1322036SN/A const char *description() { return "Timing CPU clock event"; } 1332036SN/A }; 1342036SN/A 1353483Ssaidi@eecs.umich.edu ITickEvent tickEvent; 1363799Sgblack@eecs.umich.edu 1372036SN/A }; 1382036SN/A 1392036SN/A class DcachePort : public CpuPort 1402036SN/A { 1413483Ssaidi@eecs.umich.edu public: 1423799Sgblack@eecs.umich.edu 1432036SN/A DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1442036SN/A : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 1452036SN/A { } 1462036SN/A 1472036SN/A virtual void setPeer(Port *port); 1482036SN/A 1492036SN/A protected: 1502036SN/A 1512036SN/A virtual bool recvTiming(PacketPtr pkt); 1522036SN/A 1533799Sgblack@eecs.umich.edu virtual void recvRetry(); 1543799Sgblack@eecs.umich.edu 1553799Sgblack@eecs.umich.edu struct DTickEvent : public TickEvent 1563799Sgblack@eecs.umich.edu { 1573799Sgblack@eecs.umich.edu DTickEvent(TimingSimpleCPU *_cpu) 1583799Sgblack@eecs.umich.edu : TickEvent(_cpu) {} 1593799Sgblack@eecs.umich.edu void process(); 1603799Sgblack@eecs.umich.edu const char *description() { return "Timing CPU clock event"; } 1613799Sgblack@eecs.umich.edu }; 1623799Sgblack@eecs.umich.edu 1633799Sgblack@eecs.umich.edu DTickEvent tickEvent; 1643799Sgblack@eecs.umich.edu 1653799Sgblack@eecs.umich.edu }; 1662036SN/A 1672036SN/A IcachePort icachePort; 1682036SN/A DcachePort dcachePort; 1692036SN/A 1703799Sgblack@eecs.umich.edu PacketPtr ifetch_pkt; 1713799Sgblack@eecs.umich.edu PacketPtr dcache_pkt; 1723799Sgblack@eecs.umich.edu 1733799Sgblack@eecs.umich.edu int cpu_id; 1743799Sgblack@eecs.umich.edu Tick previousTick; 1753799Sgblack@eecs.umich.edu 1763799Sgblack@eecs.umich.edu public: 1773799Sgblack@eecs.umich.edu 1783799Sgblack@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 1793799Sgblack@eecs.umich.edu 1803799Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 1813799Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1823799Sgblack@eecs.umich.edu 1832036SN/A virtual unsigned int drain(Event *drain_event); 1842036SN/A virtual void resume(); 185 186 void switchOut(); 187 void takeOverFrom(BaseCPU *oldCPU); 188 189 virtual void activateContext(int thread_num, int delay); 190 virtual void suspendContext(int thread_num); 191 192 template <class T> 193 Fault read(Addr addr, T &data, unsigned flags); 194 195 template <class T> 196 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 197 198 void fetch(); 199 void completeIfetch(PacketPtr ); 200 void completeDataAccess(PacketPtr ); 201 void advanceInst(Fault fault); 202 private: 203 void completeDrain(); 204}; 205 206#endif // __CPU_SIMPLE_TIMING_HH__ 207