timing.hh revision 13652:45d94ac03a27
13630SN/A/* 27090SN/A * Copyright (c) 2012-2013,2015 ARM Limited 37090SN/A * All rights reserved 47090SN/A * 57090SN/A * The license below extends only to copyright in the software and shall 67090SN/A * not be construed as granting a license to any other intellectual 77090SN/A * property including but not limited to intellectual property relating 87090SN/A * to a hardware implementation of the functionality of the software 97090SN/A * licensed hereunder. You may use the software subject to the license 107090SN/A * terms below provided that you ensure that this notice is replicated 117090SN/A * unmodified and in its entirety in all distributions of the software, 127090SN/A * modified or unmodified, in source code or in binary form. 137090SN/A * 143630SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 153630SN/A * All rights reserved. 163630SN/A * 173630SN/A * Redistribution and use in source and binary forms, with or without 183630SN/A * modification, are permitted provided that the following conditions are 193630SN/A * met: redistributions of source code must retain the above copyright 203630SN/A * notice, this list of conditions and the following disclaimer; 213630SN/A * redistributions in binary form must reproduce the above copyright 223630SN/A * notice, this list of conditions and the following disclaimer in the 233630SN/A * documentation and/or other materials provided with the distribution; 243630SN/A * neither the name of the copyright holders nor the names of its 253630SN/A * contributors may be used to endorse or promote products derived from 263630SN/A * this software without specific prior written permission. 273630SN/A * 283630SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293630SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303630SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313630SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323630SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333630SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343630SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353630SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363630SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373630SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383630SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393630SN/A * 403630SN/A * Authors: Steve Reinhardt 413630SN/A */ 423630SN/A 433630SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 443630SN/A#define __CPU_SIMPLE_TIMING_HH__ 457584SAli.Saidi@arm.com 463630SN/A#include "cpu/simple/base.hh" 473630SN/A#include "cpu/simple/exec_context.hh" 483630SN/A#include "cpu/translation.hh" 497584SAli.Saidi@arm.com#include "params/TimingSimpleCPU.hh" 507584SAli.Saidi@arm.com 513630SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 523630SN/A{ 537584SAli.Saidi@arm.com public: 543630SN/A 559525SAndreas.Sandberg@ARM.com TimingSimpleCPU(TimingSimpleCPUParams * params); 563630SN/A virtual ~TimingSimpleCPU(); 573630SN/A 583630SN/A void init() override; 597584SAli.Saidi@arm.com 603630SN/A private: 613630SN/A 623630SN/A /* 633630SN/A * If an access needs to be broken into fragments, currently at most two, 643630SN/A * the the following two classes are used as the sender state of the 659525SAndreas.Sandberg@ARM.com * packets so the CPU can keep track of everything. In the main packet 668525SAli.Saidi@ARM.com * sender state, there's an array with a spot for each fragment. If a 673630SN/A * fragment has already been accepted by the CPU, aka isn't waiting for 687584SAli.Saidi@arm.com * a retry, it's pointer is NULL. After each fragment has successfully 698525SAli.Saidi@ARM.com * been processed, the "outstanding" counter is decremented. Once the 708525SAli.Saidi@ARM.com * count is zero, the entire larger access is complete. 718525SAli.Saidi@ARM.com */ 728525SAli.Saidi@ARM.com class SplitMainSenderState : public Packet::SenderState 738525SAli.Saidi@ARM.com { 743630SN/A public: 753630SN/A int outstanding; 763630SN/A PacketPtr fragments[2]; 773630SN/A 783630SN/A int 793630SN/A getPendingFragment() 807584SAli.Saidi@arm.com { 813630SN/A if (fragments[0]) { 828525SAli.Saidi@ARM.com return 0; 839525SAndreas.Sandberg@ARM.com } else if (fragments[1]) { 848525SAli.Saidi@ARM.com return 1; 853630SN/A } else { 863630SN/A return -1; 873630SN/A } 883630SN/A } 893630SN/A }; 903630SN/A 913812SN/A class SplitFragmentSenderState : public Packet::SenderState 923630SN/A { 933630SN/A public: 943630SN/A SplitFragmentSenderState(PacketPtr _bigPkt, int _index) : 953630SN/A bigPkt(_bigPkt), index(_index) 963630SN/A {} 973630SN/A PacketPtr bigPkt; 983630SN/A int index; 993630SN/A 1003630SN/A void 1013630SN/A clearFromParent() 1023630SN/A { 1033630SN/A SplitMainSenderState * main_send_state = 1043630SN/A dynamic_cast<SplitMainSenderState *>(bigPkt->senderState); 1053630SN/A main_send_state->fragments[index] = NULL; 1063630SN/A } 1073630SN/A }; 1083630SN/A 1093630SN/A class FetchTranslation : public BaseTLB::Translation 1103630SN/A { 1115834SN/A protected: 1125834SN/A TimingSimpleCPU *cpu; 1135834SN/A 1145834SN/A public: 1155834SN/A FetchTranslation(TimingSimpleCPU *_cpu) 1165834SN/A : cpu(_cpu) 1175834SN/A {} 1185834SN/A 1195834SN/A void 1205834SN/A markDelayed() 1215834SN/A { 1223630SN/A assert(cpu->_status == BaseSimpleCPU::Running); 1233630SN/A cpu->_status = ITBWaitResponse; 1247584SAli.Saidi@arm.com } 125 126 void 127 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, 128 BaseTLB::Mode mode) 129 { 130 cpu->sendFetch(fault, req, tc); 131 } 132 }; 133 FetchTranslation fetchTranslation; 134 135 void threadSnoop(PacketPtr pkt, ThreadID sender); 136 void sendData(const RequestPtr &req, 137 uint8_t *data, uint64_t *res, bool read); 138 void sendSplitData(const RequestPtr &req1, const RequestPtr &req2, 139 const RequestPtr &req, 140 uint8_t *data, bool read); 141 142 void translationFault(const Fault &fault); 143 144 PacketPtr buildPacket(const RequestPtr &req, bool read); 145 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 146 const RequestPtr &req1, const RequestPtr &req2, 147 const RequestPtr &req, 148 uint8_t *data, bool read); 149 150 bool handleReadPacket(PacketPtr pkt); 151 // This function always implicitly uses dcache_pkt. 152 bool handleWritePacket(); 153 154 /** 155 * A TimingCPUPort overrides the default behaviour of the 156 * recvTiming and recvRetry and implements events for the 157 * scheduling of handling of incoming packets in the following 158 * cycle. 159 */ 160 class TimingCPUPort : public MasterPort 161 { 162 public: 163 164 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) 165 : MasterPort(_name, _cpu), cpu(_cpu), 166 retryRespEvent([this]{ sendRetryResp(); }, name()) 167 { } 168 169 protected: 170 171 TimingSimpleCPU* cpu; 172 173 struct TickEvent : public Event 174 { 175 PacketPtr pkt; 176 TimingSimpleCPU *cpu; 177 178 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {} 179 const char *description() const { return "Timing CPU tick"; } 180 void schedule(PacketPtr _pkt, Tick t); 181 }; 182 183 EventFunctionWrapper retryRespEvent; 184 }; 185 186 class IcachePort : public TimingCPUPort 187 { 188 public: 189 190 IcachePort(TimingSimpleCPU *_cpu) 191 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu), 192 tickEvent(_cpu) 193 { } 194 195 protected: 196 197 virtual bool recvTimingResp(PacketPtr pkt); 198 199 virtual void recvReqRetry(); 200 201 struct ITickEvent : public TickEvent 202 { 203 204 ITickEvent(TimingSimpleCPU *_cpu) 205 : TickEvent(_cpu) {} 206 void process(); 207 const char *description() const { return "Timing CPU icache tick"; } 208 }; 209 210 ITickEvent tickEvent; 211 212 }; 213 214 class DcachePort : public TimingCPUPort 215 { 216 public: 217 218 DcachePort(TimingSimpleCPU *_cpu) 219 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu), 220 tickEvent(_cpu) 221 { 222 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 223 } 224 225 Addr cacheBlockMask; 226 protected: 227 228 /** Snoop a coherence request, we need to check if this causes 229 * a wakeup event on a cpu that is monitoring an address 230 */ 231 virtual void recvTimingSnoopReq(PacketPtr pkt); 232 virtual void recvFunctionalSnoop(PacketPtr pkt); 233 234 virtual bool recvTimingResp(PacketPtr pkt); 235 236 virtual void recvReqRetry(); 237 238 virtual bool isSnooping() const { 239 return true; 240 } 241 242 struct DTickEvent : public TickEvent 243 { 244 DTickEvent(TimingSimpleCPU *_cpu) 245 : TickEvent(_cpu) {} 246 void process(); 247 const char *description() const { return "Timing CPU dcache tick"; } 248 }; 249 250 DTickEvent tickEvent; 251 252 }; 253 254 void updateCycleCounts(); 255 256 IcachePort icachePort; 257 DcachePort dcachePort; 258 259 PacketPtr ifetch_pkt; 260 PacketPtr dcache_pkt; 261 262 Cycles previousCycle; 263 264 protected: 265 266 /** Return a reference to the data port. */ 267 MasterPort &getDataPort() override { return dcachePort; } 268 269 /** Return a reference to the instruction port. */ 270 MasterPort &getInstPort() override { return icachePort; } 271 272 public: 273 274 DrainState drain() override; 275 void drainResume() override; 276 277 void switchOut() override; 278 void takeOverFrom(BaseCPU *oldCPU) override; 279 280 void verifyMemoryMode() const override; 281 282 void activateContext(ThreadID thread_num) override; 283 void suspendContext(ThreadID thread_num) override; 284 285 Fault initiateMemRead(Addr addr, unsigned size, 286 Request::Flags flags) override; 287 288 Fault writeMem(uint8_t *data, unsigned size, 289 Addr addr, Request::Flags flags, uint64_t *res) override; 290 291 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, 292 AtomicOpFunctor *amo_op) override; 293 294 void fetch(); 295 void sendFetch(const Fault &fault, 296 const RequestPtr &req, ThreadContext *tc); 297 void completeIfetch(PacketPtr ); 298 void completeDataAccess(PacketPtr pkt); 299 void advanceInst(const Fault &fault); 300 301 /** This function is used by the page table walker to determine if it could 302 * translate the a pending request or if the underlying request has been 303 * squashed. This always returns false for the simple timing CPU as it never 304 * executes any instructions speculatively. 305 * @ return Is the current instruction squashed? 306 */ 307 bool isSquashed() const { return false; } 308 309 /** 310 * Print state of address in memory system via PrintReq (for 311 * debugging). 312 */ 313 void printAddr(Addr a); 314 315 /** 316 * Finish a DTB translation. 317 * @param state The DTB translation state. 318 */ 319 void finishTranslation(WholeTranslationState *state); 320 321 private: 322 323 EventFunctionWrapper fetchEvent; 324 325 struct IprEvent : Event { 326 Packet *pkt; 327 TimingSimpleCPU *cpu; 328 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 329 virtual void process(); 330 virtual const char *description() const; 331 }; 332 333 /** 334 * Check if a system is in a drained state. 335 * 336 * We need to drain if: 337 * <ul> 338 * <li>We are in the middle of a microcode sequence as some CPUs 339 * (e.g., HW accelerated CPUs) can't be started in the middle 340 * of a gem5 microcode sequence. 341 * 342 * <li>Stay at PC is true. 343 * 344 * <li>A fetch event is scheduled. Normally this would never be the 345 * case with microPC() == 0, but right after a context is 346 * activated it can happen. 347 * </ul> 348 */ 349 bool isDrained() { 350 SimpleExecContext& t_info = *threadInfo[curThread]; 351 SimpleThread* thread = t_info.thread; 352 353 return thread->microPC() == 0 && !t_info.stayAtPC && 354 !fetchEvent.scheduled(); 355 } 356 357 /** 358 * Try to complete a drain request. 359 * 360 * @returns true if the CPU is drained, false otherwise. 361 */ 362 bool tryCompleteDrain(); 363}; 364 365#endif // __CPU_SIMPLE_TIMING_HH__ 366