timing.hh revision 5529
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 322623SN/A#define __CPU_SIMPLE_TIMING_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 352623SN/A 365529Snate@binkert.org#include "params/TimingSimpleCPU.hh" 375529Snate@binkert.org 382623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 392623SN/A{ 402623SN/A public: 412623SN/A 425529Snate@binkert.org TimingSimpleCPU(TimingSimpleCPUParams * params); 432623SN/A virtual ~TimingSimpleCPU(); 442623SN/A 452623SN/A virtual void init(); 462623SN/A 472623SN/A public: 482839Sktlim@umich.edu Event *drainEvent; 492798Sktlim@umich.edu 502623SN/A private: 512623SN/A 522623SN/A class CpuPort : public Port 532623SN/A { 542623SN/A protected: 552623SN/A TimingSimpleCPU *cpu; 562948Ssaidi@eecs.umich.edu Tick lat; 572623SN/A 582623SN/A public: 592623SN/A 602948Ssaidi@eecs.umich.edu CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 613401Sktlim@umich.edu : Port(_name, _cpu), cpu(_cpu), lat(_lat) 622623SN/A { } 632623SN/A 643647Srdreslin@umich.edu bool snoopRangeSent; 653647Srdreslin@umich.edu 662623SN/A protected: 672623SN/A 683349Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 692623SN/A 703349Sbinkertn@umich.edu virtual void recvFunctional(PacketPtr pkt); 712623SN/A 722623SN/A virtual void recvStatusChange(Status status); 732623SN/A 742623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 754475Sstever@eecs.umich.edu bool &snoop) 764475Sstever@eecs.umich.edu { resp.clear(); snoop = false; } 772948Ssaidi@eecs.umich.edu 782948Ssaidi@eecs.umich.edu struct TickEvent : public Event 792948Ssaidi@eecs.umich.edu { 803349Sbinkertn@umich.edu PacketPtr pkt; 812948Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 822948Ssaidi@eecs.umich.edu 832948Ssaidi@eecs.umich.edu TickEvent(TimingSimpleCPU *_cpu) 842948Ssaidi@eecs.umich.edu :Event(&mainEventQueue), cpu(_cpu) {} 855336Shines@cs.fsu.edu const char *description() const { return "Timing CPU tick"; } 863349Sbinkertn@umich.edu void schedule(PacketPtr _pkt, Tick t); 872948Ssaidi@eecs.umich.edu }; 882948Ssaidi@eecs.umich.edu 892623SN/A }; 902623SN/A 912623SN/A class IcachePort : public CpuPort 922623SN/A { 932623SN/A public: 942623SN/A 952948Ssaidi@eecs.umich.edu IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 962948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 972623SN/A { } 982623SN/A 992623SN/A protected: 1002623SN/A 1013349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 1022623SN/A 1032657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1042948Ssaidi@eecs.umich.edu 1052948Ssaidi@eecs.umich.edu struct ITickEvent : public TickEvent 1062948Ssaidi@eecs.umich.edu { 1072948Ssaidi@eecs.umich.edu 1082948Ssaidi@eecs.umich.edu ITickEvent(TimingSimpleCPU *_cpu) 1092948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 1102948Ssaidi@eecs.umich.edu void process(); 1115336Shines@cs.fsu.edu const char *description() const { return "Timing CPU icache tick"; } 1122948Ssaidi@eecs.umich.edu }; 1132948Ssaidi@eecs.umich.edu 1142948Ssaidi@eecs.umich.edu ITickEvent tickEvent; 1152948Ssaidi@eecs.umich.edu 1162623SN/A }; 1172623SN/A 1182623SN/A class DcachePort : public CpuPort 1192623SN/A { 1202623SN/A public: 1212623SN/A 1222948Ssaidi@eecs.umich.edu DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1232948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 1242623SN/A { } 1252623SN/A 1264192Sktlim@umich.edu virtual void setPeer(Port *port); 1274192Sktlim@umich.edu 1282623SN/A protected: 1292623SN/A 1303349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 1312623SN/A 1322657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1332948Ssaidi@eecs.umich.edu 1342948Ssaidi@eecs.umich.edu struct DTickEvent : public TickEvent 1352948Ssaidi@eecs.umich.edu { 1362948Ssaidi@eecs.umich.edu DTickEvent(TimingSimpleCPU *_cpu) 1372948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 1382948Ssaidi@eecs.umich.edu void process(); 1395336Shines@cs.fsu.edu const char *description() const { return "Timing CPU dcache tick"; } 1402948Ssaidi@eecs.umich.edu }; 1412948Ssaidi@eecs.umich.edu 1422948Ssaidi@eecs.umich.edu DTickEvent tickEvent; 1432948Ssaidi@eecs.umich.edu 1442623SN/A }; 1452623SN/A 1462623SN/A IcachePort icachePort; 1472623SN/A DcachePort dcachePort; 1482623SN/A 1493349Sbinkertn@umich.edu PacketPtr ifetch_pkt; 1503349Sbinkertn@umich.edu PacketPtr dcache_pkt; 1512623SN/A 1523222Sktlim@umich.edu Tick previousTick; 1533170Sstever@eecs.umich.edu 1542623SN/A public: 1552623SN/A 1562856Srdreslin@umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 1572856Srdreslin@umich.edu 1582623SN/A virtual void serialize(std::ostream &os); 1592623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1602623SN/A 1612901Ssaidi@eecs.umich.edu virtual unsigned int drain(Event *drain_event); 1622798Sktlim@umich.edu virtual void resume(); 1632798Sktlim@umich.edu 1642798Sktlim@umich.edu void switchOut(); 1652623SN/A void takeOverFrom(BaseCPU *oldCPU); 1662623SN/A 1672623SN/A virtual void activateContext(int thread_num, int delay); 1682623SN/A virtual void suspendContext(int thread_num); 1692623SN/A 1702623SN/A template <class T> 1712623SN/A Fault read(Addr addr, T &data, unsigned flags); 1722623SN/A 1735177Sgblack@eecs.umich.edu Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 1745177Sgblack@eecs.umich.edu int size, unsigned flags); 1755177Sgblack@eecs.umich.edu 1762623SN/A template <class T> 1772623SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1782623SN/A 1795177Sgblack@eecs.umich.edu Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 1805177Sgblack@eecs.umich.edu int size, unsigned flags); 1815177Sgblack@eecs.umich.edu 1822623SN/A void fetch(); 1833349Sbinkertn@umich.edu void completeIfetch(PacketPtr ); 1843349Sbinkertn@umich.edu void completeDataAccess(PacketPtr ); 1852644Sstever@eecs.umich.edu void advanceInst(Fault fault); 1864471Sstever@eecs.umich.edu 1875315Sstever@gmail.com /** 1885315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 1895315Sstever@gmail.com * debugging). 1905315Sstever@gmail.com */ 1915315Sstever@gmail.com void printAddr(Addr a); 1925315Sstever@gmail.com 1932798Sktlim@umich.edu private: 1944471Sstever@eecs.umich.edu 1954471Sstever@eecs.umich.edu typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 1964471Sstever@eecs.umich.edu FetchEvent *fetchEvent; 1974471Sstever@eecs.umich.edu 1985103Ssaidi@eecs.umich.edu struct IprEvent : Event { 1995103Ssaidi@eecs.umich.edu Packet *pkt; 2005103Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 2015103Ssaidi@eecs.umich.edu IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 2025103Ssaidi@eecs.umich.edu virtual void process(); 2035336Shines@cs.fsu.edu virtual const char *description() const; 2045103Ssaidi@eecs.umich.edu }; 2055103Ssaidi@eecs.umich.edu 2062839Sktlim@umich.edu void completeDrain(); 2072623SN/A}; 2082623SN/A 2092623SN/A#endif // __CPU_SIMPLE_TIMING_HH__ 210