timing.hh revision 5315
12623SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 39442SAndreas.Sandberg@ARM.com * All rights reserved. 49442SAndreas.Sandberg@ARM.com * 59442SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 69442SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 79442SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 89442SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 99442SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 109442SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 119442SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 129442SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 139442SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272623SN/A * 282623SN/A * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 322623SN/A#define __CPU_SIMPLE_TIMING_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 352623SN/A 362623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 372623SN/A{ 382623SN/A public: 392665Ssaidi@eecs.umich.edu 402665Ssaidi@eecs.umich.edu struct Params : public BaseSimpleCPU::Params { 412623SN/A }; 422623SN/A 432623SN/A TimingSimpleCPU(Params *params); 442623SN/A virtual ~TimingSimpleCPU(); 452623SN/A 462623SN/A virtual void init(); 476973Stjones1@inf.ed.ac.uk 485529Snate@binkert.org public: 495529Snate@binkert.org // 502623SN/A enum Status { 512623SN/A Idle, 522623SN/A Running, 532623SN/A IcacheRetry, 545529Snate@binkert.org IcacheWaitResponse, 552623SN/A IcacheWaitSwitch, 562623SN/A DcacheRetry, 572623SN/A DcacheWaitResponse, 582623SN/A DcacheWaitSwitch, 592623SN/A SwitchedOut 602623SN/A }; 615728Sgblack@eecs.umich.edu 625728Sgblack@eecs.umich.edu protected: 635728Sgblack@eecs.umich.edu Status _status; 645728Sgblack@eecs.umich.edu 655728Sgblack@eecs.umich.edu Status status() const { return _status; } 665728Sgblack@eecs.umich.edu 675728Sgblack@eecs.umich.edu Event *drainEvent; 685728Sgblack@eecs.umich.edu 695728Sgblack@eecs.umich.edu private: 705728Sgblack@eecs.umich.edu 715728Sgblack@eecs.umich.edu class CpuPort : public Port 725728Sgblack@eecs.umich.edu { 735728Sgblack@eecs.umich.edu protected: 745728Sgblack@eecs.umich.edu TimingSimpleCPU *cpu; 755728Sgblack@eecs.umich.edu Tick lat; 765728Sgblack@eecs.umich.edu 775728Sgblack@eecs.umich.edu public: 785728Sgblack@eecs.umich.edu 795728Sgblack@eecs.umich.edu CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 805728Sgblack@eecs.umich.edu : Port(_name, _cpu), cpu(_cpu), lat(_lat) 815728Sgblack@eecs.umich.edu { } 825728Sgblack@eecs.umich.edu 835728Sgblack@eecs.umich.edu bool snoopRangeSent; 845728Sgblack@eecs.umich.edu 855728Sgblack@eecs.umich.edu protected: 865728Sgblack@eecs.umich.edu 875728Sgblack@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 885728Sgblack@eecs.umich.edu 895728Sgblack@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 905728Sgblack@eecs.umich.edu 915728Sgblack@eecs.umich.edu virtual void recvStatusChange(Status status); 925728Sgblack@eecs.umich.edu 935728Sgblack@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 945728Sgblack@eecs.umich.edu bool &snoop) 955728Sgblack@eecs.umich.edu { resp.clear(); snoop = false; } 965728Sgblack@eecs.umich.edu 975728Sgblack@eecs.umich.edu struct TickEvent : public Event 985728Sgblack@eecs.umich.edu { 995728Sgblack@eecs.umich.edu PacketPtr pkt; 1005728Sgblack@eecs.umich.edu TimingSimpleCPU *cpu; 1015728Sgblack@eecs.umich.edu 1025728Sgblack@eecs.umich.edu TickEvent(TimingSimpleCPU *_cpu) 1035728Sgblack@eecs.umich.edu :Event(&mainEventQueue), cpu(_cpu) {} 1045728Sgblack@eecs.umich.edu const char *description() { return "Timing CPU tick"; } 1055728Sgblack@eecs.umich.edu void schedule(PacketPtr _pkt, Tick t); 1065728Sgblack@eecs.umich.edu }; 1075728Sgblack@eecs.umich.edu 1085894Sgblack@eecs.umich.edu }; 1095894Sgblack@eecs.umich.edu 1105894Sgblack@eecs.umich.edu class IcachePort : public CpuPort 1115894Sgblack@eecs.umich.edu { 1125894Sgblack@eecs.umich.edu public: 1135894Sgblack@eecs.umich.edu 1146023Snate@binkert.org IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1156023Snate@binkert.org : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 1165894Sgblack@eecs.umich.edu { } 1175894Sgblack@eecs.umich.edu 1186023Snate@binkert.org protected: 1197944SGiacomo.Gabrielli@arm.com 1207945SAli.Saidi@ARM.com virtual bool recvTiming(PacketPtr pkt); 1219342SAndreas.Sandberg@arm.com 1227945SAli.Saidi@ARM.com virtual void recvRetry(); 1237945SAli.Saidi@ARM.com 1247944SGiacomo.Gabrielli@arm.com struct ITickEvent : public TickEvent 1257944SGiacomo.Gabrielli@arm.com { 12610379Sandreas.hansson@arm.com 1276023Snate@binkert.org ITickEvent(TimingSimpleCPU *_cpu) 1285894Sgblack@eecs.umich.edu : TickEvent(_cpu) {} 1295894Sgblack@eecs.umich.edu void process(); 1305894Sgblack@eecs.umich.edu const char *description() { return "Timing CPU icache tick"; } 1315894Sgblack@eecs.umich.edu }; 1325894Sgblack@eecs.umich.edu 1335894Sgblack@eecs.umich.edu ITickEvent tickEvent; 1346973Stjones1@inf.ed.ac.uk 1356973Stjones1@inf.ed.ac.uk }; 1366973Stjones1@inf.ed.ac.uk 1375894Sgblack@eecs.umich.edu class DcachePort : public CpuPort 13810379Sandreas.hansson@arm.com { 1395894Sgblack@eecs.umich.edu public: 14010653Sandreas.hansson@arm.com 1415894Sgblack@eecs.umich.edu DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1425894Sgblack@eecs.umich.edu : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 1435894Sgblack@eecs.umich.edu { } 1445744Sgblack@eecs.umich.edu 1455728Sgblack@eecs.umich.edu virtual void setPeer(Port *port); 1465728Sgblack@eecs.umich.edu 1475728Sgblack@eecs.umich.edu protected: 1485728Sgblack@eecs.umich.edu 1498707Sandreas.hansson@arm.com virtual bool recvTiming(PacketPtr pkt); 1508707Sandreas.hansson@arm.com 1518707Sandreas.hansson@arm.com virtual void recvRetry(); 1528707Sandreas.hansson@arm.com 1538707Sandreas.hansson@arm.com struct DTickEvent : public TickEvent 1548707Sandreas.hansson@arm.com { 1559608Sandreas.hansson@arm.com DTickEvent(TimingSimpleCPU *_cpu) 1562623SN/A : TickEvent(_cpu) {} 1572623SN/A void process(); 1582623SN/A const char *description() { return "Timing CPU dcache tick"; } 1598707Sandreas.hansson@arm.com }; 16010713Sandreas.hansson@arm.com 1612623SN/A DTickEvent tickEvent; 1622623SN/A 1632623SN/A }; 1642623SN/A 1658948Sandreas.hansson@arm.com IcachePort icachePort; 1668948Sandreas.hansson@arm.com DcachePort dcachePort; 1678948Sandreas.hansson@arm.com 16810030SAli.Saidi@ARM.com PacketPtr ifetch_pkt; 1698948Sandreas.hansson@arm.com PacketPtr dcache_pkt; 1708707Sandreas.hansson@arm.com 1712948Ssaidi@eecs.umich.edu Tick previousTick; 1722948Ssaidi@eecs.umich.edu 1732948Ssaidi@eecs.umich.edu public: 1743349Sbinkertn@umich.edu 1752948Ssaidi@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 1762948Ssaidi@eecs.umich.edu 1778707Sandreas.hansson@arm.com virtual void serialize(std::ostream &os); 1785336Shines@cs.fsu.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1793349Sbinkertn@umich.edu 1802948Ssaidi@eecs.umich.edu virtual unsigned int drain(Event *drain_event); 1812948Ssaidi@eecs.umich.edu virtual void resume(); 18210713Sandreas.hansson@arm.com 1832623SN/A void switchOut(); 1842623SN/A void takeOverFrom(BaseCPU *oldCPU); 1858707Sandreas.hansson@arm.com 1862623SN/A virtual void activateContext(int thread_num, int delay); 1872623SN/A virtual void suspendContext(int thread_num); 1882623SN/A 1898707Sandreas.hansson@arm.com template <class T> 1909095Sandreas.hansson@arm.com Fault read(Addr addr, T &data, unsigned flags); 1918707Sandreas.hansson@arm.com 1922623SN/A Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 1932623SN/A int size, unsigned flags); 1942623SN/A 1952623SN/A template <class T> 1968975Sandreas.hansson@arm.com Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1972623SN/A 19810713Sandreas.hansson@arm.com Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 1992948Ssaidi@eecs.umich.edu int size, unsigned flags); 2002948Ssaidi@eecs.umich.edu 2012948Ssaidi@eecs.umich.edu void fetch(); 2022948Ssaidi@eecs.umich.edu void completeIfetch(PacketPtr ); 2032948Ssaidi@eecs.umich.edu void completeDataAccess(PacketPtr ); 2042948Ssaidi@eecs.umich.edu void advanceInst(Fault fault); 2052948Ssaidi@eecs.umich.edu 2065336Shines@cs.fsu.edu /** 2072948Ssaidi@eecs.umich.edu * Print state of address in memory system via PrintReq (for 2082948Ssaidi@eecs.umich.edu * debugging). 2092948Ssaidi@eecs.umich.edu */ 2102948Ssaidi@eecs.umich.edu void printAddr(Addr a); 2112623SN/A 2122623SN/A private: 2138707Sandreas.hansson@arm.com 2142623SN/A typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 2152623SN/A FetchEvent *fetchEvent; 2162623SN/A 2178707Sandreas.hansson@arm.com struct IprEvent : Event { 2189095Sandreas.hansson@arm.com Packet *pkt; 2199095Sandreas.hansson@arm.com TimingSimpleCPU *cpu; 22010030SAli.Saidi@ARM.com IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 22110030SAli.Saidi@ARM.com virtual void process(); 22210030SAli.Saidi@ARM.com virtual const char *description(); 2232623SN/A }; 22410030SAli.Saidi@ARM.com 2252623SN/A void completeDrain(); 2262623SN/A}; 22710030SAli.Saidi@ARM.com 22810030SAli.Saidi@ARM.com#endif // __CPU_SIMPLE_TIMING_HH__ 22910030SAli.Saidi@ARM.com