timing.hh revision 4192
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 322623SN/A#define __CPU_SIMPLE_TIMING_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 352623SN/A 362623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 372623SN/A{ 382623SN/A public: 392623SN/A 402623SN/A struct Params : public BaseSimpleCPU::Params { 412623SN/A }; 422623SN/A 432623SN/A TimingSimpleCPU(Params *params); 442623SN/A virtual ~TimingSimpleCPU(); 452623SN/A 462623SN/A virtual void init(); 472623SN/A 482623SN/A public: 492623SN/A // 502623SN/A enum Status { 512623SN/A Idle, 522623SN/A Running, 532623SN/A IcacheRetry, 542623SN/A IcacheWaitResponse, 552623SN/A IcacheWaitSwitch, 562623SN/A DcacheRetry, 572623SN/A DcacheWaitResponse, 582623SN/A DcacheWaitSwitch, 592623SN/A SwitchedOut 602623SN/A }; 612623SN/A 622623SN/A protected: 632623SN/A Status _status; 642623SN/A 652623SN/A Status status() const { return _status; } 662623SN/A 672839Sktlim@umich.edu Event *drainEvent; 682798Sktlim@umich.edu 692867Sktlim@umich.edu Event *fetchEvent; 702867Sktlim@umich.edu 712623SN/A private: 722623SN/A 732623SN/A class CpuPort : public Port 742623SN/A { 752623SN/A protected: 762623SN/A TimingSimpleCPU *cpu; 772948Ssaidi@eecs.umich.edu Tick lat; 782623SN/A 792623SN/A public: 802623SN/A 812948Ssaidi@eecs.umich.edu CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 823401Sktlim@umich.edu : Port(_name, _cpu), cpu(_cpu), lat(_lat) 832623SN/A { } 842623SN/A 853647Srdreslin@umich.edu bool snoopRangeSent; 863647Srdreslin@umich.edu 872623SN/A protected: 882623SN/A 893349Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 902623SN/A 913349Sbinkertn@umich.edu virtual void recvFunctional(PacketPtr pkt); 922623SN/A 932623SN/A virtual void recvStatusChange(Status status); 942623SN/A 952623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 962623SN/A AddrRangeList &snoop) 973846Shsul@eecs.umich.edu { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } 982948Ssaidi@eecs.umich.edu 992948Ssaidi@eecs.umich.edu struct TickEvent : public Event 1002948Ssaidi@eecs.umich.edu { 1013349Sbinkertn@umich.edu PacketPtr pkt; 1022948Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 1032948Ssaidi@eecs.umich.edu 1042948Ssaidi@eecs.umich.edu TickEvent(TimingSimpleCPU *_cpu) 1052948Ssaidi@eecs.umich.edu :Event(&mainEventQueue), cpu(_cpu) {} 1062948Ssaidi@eecs.umich.edu const char *description() { return "Timing CPU clock event"; } 1073349Sbinkertn@umich.edu void schedule(PacketPtr _pkt, Tick t); 1082948Ssaidi@eecs.umich.edu }; 1092948Ssaidi@eecs.umich.edu 1102623SN/A }; 1112623SN/A 1122623SN/A class IcachePort : public CpuPort 1132623SN/A { 1142623SN/A public: 1152623SN/A 1162948Ssaidi@eecs.umich.edu IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1172948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 1182623SN/A { } 1192623SN/A 1202623SN/A protected: 1212623SN/A 1223349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 1232623SN/A 1242657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1252948Ssaidi@eecs.umich.edu 1262948Ssaidi@eecs.umich.edu struct ITickEvent : public TickEvent 1272948Ssaidi@eecs.umich.edu { 1282948Ssaidi@eecs.umich.edu 1292948Ssaidi@eecs.umich.edu ITickEvent(TimingSimpleCPU *_cpu) 1302948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 1312948Ssaidi@eecs.umich.edu void process(); 1322948Ssaidi@eecs.umich.edu const char *description() { return "Timing CPU clock event"; } 1332948Ssaidi@eecs.umich.edu }; 1342948Ssaidi@eecs.umich.edu 1352948Ssaidi@eecs.umich.edu ITickEvent tickEvent; 1362948Ssaidi@eecs.umich.edu 1372623SN/A }; 1382623SN/A 1392623SN/A class DcachePort : public CpuPort 1402623SN/A { 1412623SN/A public: 1422623SN/A 1432948Ssaidi@eecs.umich.edu DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1442948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 1452623SN/A { } 1462623SN/A 1474192Sktlim@umich.edu virtual void setPeer(Port *port); 1484192Sktlim@umich.edu 1492623SN/A protected: 1502623SN/A 1513349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 1522623SN/A 1532657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1542948Ssaidi@eecs.umich.edu 1552948Ssaidi@eecs.umich.edu struct DTickEvent : public TickEvent 1562948Ssaidi@eecs.umich.edu { 1572948Ssaidi@eecs.umich.edu DTickEvent(TimingSimpleCPU *_cpu) 1582948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 1592948Ssaidi@eecs.umich.edu void process(); 1602948Ssaidi@eecs.umich.edu const char *description() { return "Timing CPU clock event"; } 1612948Ssaidi@eecs.umich.edu }; 1622948Ssaidi@eecs.umich.edu 1632948Ssaidi@eecs.umich.edu DTickEvent tickEvent; 1642948Ssaidi@eecs.umich.edu 1652623SN/A }; 1662623SN/A 1672623SN/A IcachePort icachePort; 1682623SN/A DcachePort dcachePort; 1692623SN/A 1703349Sbinkertn@umich.edu PacketPtr ifetch_pkt; 1713349Sbinkertn@umich.edu PacketPtr dcache_pkt; 1722623SN/A 1733170Sstever@eecs.umich.edu int cpu_id; 1743222Sktlim@umich.edu Tick previousTick; 1753170Sstever@eecs.umich.edu 1762623SN/A public: 1772623SN/A 1782856Srdreslin@umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 1792856Srdreslin@umich.edu 1802623SN/A virtual void serialize(std::ostream &os); 1812623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1822623SN/A 1832901Ssaidi@eecs.umich.edu virtual unsigned int drain(Event *drain_event); 1842798Sktlim@umich.edu virtual void resume(); 1852798Sktlim@umich.edu 1862798Sktlim@umich.edu void switchOut(); 1872623SN/A void takeOverFrom(BaseCPU *oldCPU); 1882623SN/A 1892623SN/A virtual void activateContext(int thread_num, int delay); 1902623SN/A virtual void suspendContext(int thread_num); 1912623SN/A 1922623SN/A template <class T> 1932623SN/A Fault read(Addr addr, T &data, unsigned flags); 1942623SN/A 1952623SN/A template <class T> 1962623SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1972623SN/A 1982623SN/A void fetch(); 1993349Sbinkertn@umich.edu void completeIfetch(PacketPtr ); 2003349Sbinkertn@umich.edu void completeDataAccess(PacketPtr ); 2012644Sstever@eecs.umich.edu void advanceInst(Fault fault); 2022798Sktlim@umich.edu private: 2032839Sktlim@umich.edu void completeDrain(); 2042623SN/A}; 2052623SN/A 2062623SN/A#endif // __CPU_SIMPLE_TIMING_HH__ 207