timing.hh revision 3222
12SN/A/*
22190SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Steve Reinhardt
292SN/A */
302SN/A
312680Sktlim@umich.edu#ifndef __CPU_SIMPLE_TIMING_HH__
322680Sktlim@umich.edu#define __CPU_SIMPLE_TIMING_HH__
332SN/A
346329Sgblack@eecs.umich.edu#include "cpu/simple/base.hh"
353453Sgblack@eecs.umich.edu
366216Snate@binkert.orgclass TimingSimpleCPU : public BaseSimpleCPU
371858SN/A{
386658Snate@binkert.org  public:
392423SN/A
406216Snate@binkert.org    struct Params : public BaseSimpleCPU::Params {
412190SN/A    };
42217SN/A
432SN/A    TimingSimpleCPU(Params *params);
442190SN/A    virtual ~TimingSimpleCPU();
452190SN/A
463453Sgblack@eecs.umich.edu    virtual void init();
473453Sgblack@eecs.umich.edu
486022Sgblack@eecs.umich.edu  public:
493453Sgblack@eecs.umich.edu    //
502190SN/A    enum Status {
512313SN/A        Idle,
522235SN/A        Running,
532423SN/A        IcacheRetry,
542521SN/A        IcacheWaitResponse,
552521SN/A        IcacheWaitSwitch,
562190SN/A        DcacheRetry,
572190SN/A        DcacheWaitResponse,
583548Sgblack@eecs.umich.edu        DcacheWaitSwitch,
593548Sgblack@eecs.umich.edu        SwitchedOut
603548Sgblack@eecs.umich.edu    };
613548Sgblack@eecs.umich.edu
622330SN/A  protected:
632SN/A    Status _status;
642680Sktlim@umich.edu
652680Sktlim@umich.edu    Status status() const { return _status; }
662680Sktlim@umich.edu
672680Sktlim@umich.edu    Event *drainEvent;
682680Sktlim@umich.edu
692680Sktlim@umich.edu    Event *fetchEvent;
702680Sktlim@umich.edu
712680Sktlim@umich.edu  private:
722680Sktlim@umich.edu
732680Sktlim@umich.edu    class CpuPort : public Port
742680Sktlim@umich.edu    {
752682Sktlim@umich.edu      protected:
762680Sktlim@umich.edu        TimingSimpleCPU *cpu;
772680Sktlim@umich.edu        Tick lat;
782680Sktlim@umich.edu
792680Sktlim@umich.edu      public:
802680Sktlim@umich.edu
812SN/A        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
822107SN/A            : Port(_name), cpu(_cpu), lat(_lat)
832107SN/A        { }
842190SN/A
852455SN/A      protected:
862455SN/A
872159SN/A        virtual Tick recvAtomic(Packet *pkt);
882SN/A
896029Ssteve.reinhardt@amd.com        virtual void recvFunctional(Packet *pkt);
90246SN/A
91246SN/A        virtual void recvStatusChange(Status status);
92246SN/A
93246SN/A        virtual void getDeviceAddressRanges(AddrRangeList &resp,
94246SN/A            AddrRangeList &snoop)
95246SN/A        { resp.clear(); snoop.clear(); }
96246SN/A
972190SN/A        struct TickEvent : public Event
98246SN/A        {
99246SN/A            Packet *pkt;
100246SN/A            TimingSimpleCPU *cpu;
101246SN/A
102246SN/A            TickEvent(TimingSimpleCPU *_cpu)
103246SN/A                :Event(&mainEventQueue), cpu(_cpu) {}
104246SN/A            const char *description() { return "Timing CPU clock event"; }
1052SN/A            void schedule(Packet *_pkt, Tick t);
1062680Sktlim@umich.edu        };
1072423SN/A
1082190SN/A    };
109180SN/A
1105712Shsul@eecs.umich.edu    class IcachePort : public CpuPort
1112190SN/A    {
1125715Shsul@eecs.umich.edu      public:
1135715Shsul@eecs.umich.edu
1145715Shsul@eecs.umich.edu        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
1155714Shsul@eecs.umich.edu            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
1165714Shsul@eecs.umich.edu        { }
1175714Shsul@eecs.umich.edu
1185714Shsul@eecs.umich.edu      protected:
1195714Shsul@eecs.umich.edu
1206022Sgblack@eecs.umich.edu        virtual bool recvTiming(Packet *pkt);
1212190SN/A
1226022Sgblack@eecs.umich.edu        virtual void recvRetry();
1232521SN/A
1244997Sgblack@eecs.umich.edu        struct ITickEvent : public TickEvent
1254997Sgblack@eecs.umich.edu        {
1265803Snate@binkert.org
1273548Sgblack@eecs.umich.edu            ITickEvent(TimingSimpleCPU *_cpu)
1282654SN/A                : TickEvent(_cpu) {}
1292521SN/A            void process();
1302521SN/A            const char *description() { return "Timing CPU clock event"; }
1315499Ssaidi@eecs.umich.edu        };
1323673Srdreslin@umich.edu
1335497Ssaidi@eecs.umich.edu        ITickEvent tickEvent;
1342190SN/A
1352518SN/A    };
1362518SN/A
1372190SN/A    class DcachePort : public CpuPort
1382190SN/A    {
1392190SN/A      public:
1402190SN/A
1412159SN/A        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
1422235SN/A            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
1432103SN/A        { }
144393SN/A
145393SN/A      protected:
1462190SN/A
147393SN/A        virtual bool recvTiming(Packet *pkt);
148393SN/A
1495250Sksewell@umich.edu        virtual void recvRetry();
150393SN/A
151393SN/A        struct DTickEvent : public TickEvent
1525250Sksewell@umich.edu        {
1532159SN/A            DTickEvent(TimingSimpleCPU *_cpu)
1542159SN/A                : TickEvent(_cpu) {}
1552190SN/A            void process();
1562159SN/A            const char *description() { return "Timing CPU clock event"; }
1572159SN/A        };
1582680Sktlim@umich.edu
1592159SN/A        DTickEvent tickEvent;
1602190SN/A
1612159SN/A    };
1622190SN/A
1632190SN/A    IcachePort icachePort;
1642159SN/A    DcachePort dcachePort;
1652235SN/A
1662313SN/A    Packet *ifetch_pkt;
1672235SN/A    Packet *dcache_pkt;
1682235SN/A
1692235SN/A    Tick previousTick;
1702235SN/A
1712235SN/A  public:
1722254SN/A
1732254SN/A    virtual Port *getPort(const std::string &if_name, int idx = -1);
1742254SN/A
1752235SN/A    virtual void serialize(std::ostream &os);
1762235SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
1772235SN/A
1782254SN/A    virtual unsigned int drain(Event *drain_event);
1792190SN/A    virtual void resume();
1802159SN/A
1812680Sktlim@umich.edu    void switchOut();
1822159SN/A    void takeOverFrom(BaseCPU *oldCPU);
1832190SN/A
1842159SN/A    virtual void activateContext(int thread_num, int delay);
1852159SN/A    virtual void suspendContext(int thread_num);
1862159SN/A
1872159SN/A    template <class T>
1882190SN/A    Fault read(Addr addr, T &data, unsigned flags);
1892159SN/A
1902455SN/A    template <class T>
1912159SN/A    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
1922455SN/A
1932159SN/A    void fetch();
1942190SN/A    void completeIfetch(Packet *);
1952159SN/A    void completeDataAccess(Packet *);
1962455SN/A    void advanceInst(Fault fault);
1972159SN/A  private:
1982455SN/A    void completeDrain();
1992455SN/A};
2002190SN/A
2012159SN/A#endif // __CPU_SIMPLE_TIMING_HH__
2022190SN/A