timing.hh revision 2798
12889Sbinkertn@umich.edu/* 22889Sbinkertn@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32889Sbinkertn@umich.edu * All rights reserved. 42889Sbinkertn@umich.edu * 52889Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 62889Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 72889Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 82889Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 92889Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 102889Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 112889Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 122889Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 132889Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 142889Sbinkertn@umich.edu * this software without specific prior written permission. 152889Sbinkertn@umich.edu * 162889Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172889Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182889Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192889Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202889Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212889Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222889Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232889Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242889Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252889Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262889Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272889Sbinkertn@umich.edu * 282889Sbinkertn@umich.edu * Authors: Steve Reinhardt 292889Sbinkertn@umich.edu */ 302889Sbinkertn@umich.edu 312889Sbinkertn@umich.edu#ifndef __CPU_SIMPLE_TIMING_HH__ 324053Sbinkertn@umich.edu#define __CPU_SIMPLE_TIMING_HH__ 332889Sbinkertn@umich.edu 342889Sbinkertn@umich.edu#include "cpu/simple/base.hh" 352889Sbinkertn@umich.edu 362889Sbinkertn@umich.educlass TimingSimpleCPU : public BaseSimpleCPU 372889Sbinkertn@umich.edu{ 382889Sbinkertn@umich.edu public: 392889Sbinkertn@umich.edu 402889Sbinkertn@umich.edu struct Params : public BaseSimpleCPU::Params { 412889Sbinkertn@umich.edu }; 422889Sbinkertn@umich.edu 432889Sbinkertn@umich.edu TimingSimpleCPU(Params *params); 444053Sbinkertn@umich.edu virtual ~TimingSimpleCPU(); 454053Sbinkertn@umich.edu 464053Sbinkertn@umich.edu virtual void init(); 474053Sbinkertn@umich.edu 484053Sbinkertn@umich.edu public: 494053Sbinkertn@umich.edu // 504053Sbinkertn@umich.edu enum Status { 514053Sbinkertn@umich.edu Idle, 524053Sbinkertn@umich.edu Running, 534053Sbinkertn@umich.edu IcacheRetry, 544053Sbinkertn@umich.edu IcacheWaitResponse, 554053Sbinkertn@umich.edu IcacheWaitSwitch, 564053Sbinkertn@umich.edu DcacheRetry, 572889Sbinkertn@umich.edu DcacheWaitResponse, 582889Sbinkertn@umich.edu DcacheWaitSwitch, 592889Sbinkertn@umich.edu SwitchedOut 602889Sbinkertn@umich.edu }; 612889Sbinkertn@umich.edu 622890Sbinkertn@umich.edu protected: 632889Sbinkertn@umich.edu Status _status; 642889Sbinkertn@umich.edu 652889Sbinkertn@umich.edu Status status() const { return _status; } 662889Sbinkertn@umich.edu 672889Sbinkertn@umich.edu Event *quiesceEvent; 682889Sbinkertn@umich.edu 692889Sbinkertn@umich.edu private: 702889Sbinkertn@umich.edu 712889Sbinkertn@umich.edu class CpuPort : public Port 722889Sbinkertn@umich.edu { 732889Sbinkertn@umich.edu protected: 742889Sbinkertn@umich.edu TimingSimpleCPU *cpu; 752889Sbinkertn@umich.edu 762889Sbinkertn@umich.edu public: 772889Sbinkertn@umich.edu 782889Sbinkertn@umich.edu CpuPort(const std::string &_name, TimingSimpleCPU *_cpu) 792889Sbinkertn@umich.edu : Port(_name), cpu(_cpu) 802889Sbinkertn@umich.edu { } 812889Sbinkertn@umich.edu 822889Sbinkertn@umich.edu protected: 832889Sbinkertn@umich.edu 842889Sbinkertn@umich.edu virtual Tick recvAtomic(Packet *pkt); 852889Sbinkertn@umich.edu 862889Sbinkertn@umich.edu virtual void recvFunctional(Packet *pkt); 872889Sbinkertn@umich.edu 882889Sbinkertn@umich.edu virtual void recvStatusChange(Status status); 892889Sbinkertn@umich.edu 902889Sbinkertn@umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 912889Sbinkertn@umich.edu AddrRangeList &snoop) 922889Sbinkertn@umich.edu { resp.clear(); snoop.clear(); } 932889Sbinkertn@umich.edu }; 942889Sbinkertn@umich.edu 952889Sbinkertn@umich.edu class IcachePort : public CpuPort 962889Sbinkertn@umich.edu { 972889Sbinkertn@umich.edu public: 982889Sbinkertn@umich.edu 992889Sbinkertn@umich.edu IcachePort(TimingSimpleCPU *_cpu) 1002889Sbinkertn@umich.edu : CpuPort(_cpu->name() + "-iport", _cpu) 1012889Sbinkertn@umich.edu { } 1022889Sbinkertn@umich.edu 1032889Sbinkertn@umich.edu protected: 1042889Sbinkertn@umich.edu 1052889Sbinkertn@umich.edu virtual bool recvTiming(Packet *pkt); 1062889Sbinkertn@umich.edu 1072889Sbinkertn@umich.edu virtual void recvRetry(); 1082889Sbinkertn@umich.edu }; 1092889Sbinkertn@umich.edu 1102889Sbinkertn@umich.edu class DcachePort : public CpuPort 1112889Sbinkertn@umich.edu { 1122889Sbinkertn@umich.edu public: 1132889Sbinkertn@umich.edu 1142889Sbinkertn@umich.edu DcachePort(TimingSimpleCPU *_cpu) 1152889Sbinkertn@umich.edu : CpuPort(_cpu->name() + "-dport", _cpu) 1162889Sbinkertn@umich.edu { } 1172889Sbinkertn@umich.edu 1182889Sbinkertn@umich.edu protected: 1192889Sbinkertn@umich.edu 1202889Sbinkertn@umich.edu virtual bool recvTiming(Packet *pkt); 1212889Sbinkertn@umich.edu 1222889Sbinkertn@umich.edu virtual void recvRetry(); 1232889Sbinkertn@umich.edu }; 1242889Sbinkertn@umich.edu 1252889Sbinkertn@umich.edu IcachePort icachePort; 1262889Sbinkertn@umich.edu DcachePort dcachePort; 1272889Sbinkertn@umich.edu 1282889Sbinkertn@umich.edu Packet *ifetch_pkt; 1292889Sbinkertn@umich.edu Packet *dcache_pkt; 1302889Sbinkertn@umich.edu 1312899Sbinkertn@umich.edu public: 1322899Sbinkertn@umich.edu 1332889Sbinkertn@umich.edu virtual void serialize(std::ostream &os); 1342889Sbinkertn@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1352889Sbinkertn@umich.edu 1362889Sbinkertn@umich.edu virtual bool quiesce(Event *quiesce_event); 1372889Sbinkertn@umich.edu virtual void resume(); 1382889Sbinkertn@umich.edu virtual void setMemoryMode(State new_mode); 1392889Sbinkertn@umich.edu 1402889Sbinkertn@umich.edu void switchOut(); 1412889Sbinkertn@umich.edu void takeOverFrom(BaseCPU *oldCPU); 1422889Sbinkertn@umich.edu 1432889Sbinkertn@umich.edu virtual void activateContext(int thread_num, int delay); 1442889Sbinkertn@umich.edu virtual void suspendContext(int thread_num); 1452889Sbinkertn@umich.edu 1462889Sbinkertn@umich.edu template <class T> 1472889Sbinkertn@umich.edu Fault read(Addr addr, T &data, unsigned flags); 1482889Sbinkertn@umich.edu 1492889Sbinkertn@umich.edu template <class T> 1502889Sbinkertn@umich.edu Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1512889Sbinkertn@umich.edu 1524053Sbinkertn@umich.edu void fetch(); 1534053Sbinkertn@umich.edu void completeIfetch(Packet *); 1542889Sbinkertn@umich.edu void completeDataAccess(Packet *); 1554053Sbinkertn@umich.edu void advanceInst(Fault fault); 1564044Sbinkertn@umich.edu private: 1574044Sbinkertn@umich.edu void completeQuiesce(); 1582889Sbinkertn@umich.edu}; 1592889Sbinkertn@umich.edu 1602889Sbinkertn@umich.edu#endif // __CPU_SIMPLE_TIMING_HH__ 1612889Sbinkertn@umich.edu