timing.hh revision 2665
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 322623SN/A#define __CPU_SIMPLE_TIMING_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 352623SN/A 362623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 372623SN/A{ 382623SN/A public: 392623SN/A 402623SN/A struct Params : public BaseSimpleCPU::Params { 412623SN/A }; 422623SN/A 432623SN/A TimingSimpleCPU(Params *params); 442623SN/A virtual ~TimingSimpleCPU(); 452623SN/A 462623SN/A virtual void init(); 472623SN/A 482623SN/A public: 492623SN/A // 502623SN/A enum Status { 512623SN/A Idle, 522623SN/A Running, 532623SN/A IcacheRetry, 542623SN/A IcacheWaitResponse, 552623SN/A IcacheWaitSwitch, 562623SN/A DcacheRetry, 572623SN/A DcacheWaitResponse, 582623SN/A DcacheWaitSwitch, 592623SN/A SwitchedOut 602623SN/A }; 612623SN/A 622623SN/A protected: 632623SN/A Status _status; 642623SN/A 652623SN/A Status status() const { return _status; } 662623SN/A 672623SN/A private: 682623SN/A 692623SN/A class CpuPort : public Port 702623SN/A { 712623SN/A protected: 722623SN/A TimingSimpleCPU *cpu; 732623SN/A 742623SN/A public: 752623SN/A 762640Sstever@eecs.umich.edu CpuPort(const std::string &_name, TimingSimpleCPU *_cpu) 772640Sstever@eecs.umich.edu : Port(_name), cpu(_cpu) 782623SN/A { } 792623SN/A 802623SN/A protected: 812623SN/A 822630SN/A virtual Tick recvAtomic(Packet *pkt); 832623SN/A 842630SN/A virtual void recvFunctional(Packet *pkt); 852623SN/A 862623SN/A virtual void recvStatusChange(Status status); 872623SN/A 882623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 892623SN/A AddrRangeList &snoop) 902623SN/A { resp.clear(); snoop.clear(); } 912623SN/A }; 922623SN/A 932623SN/A class IcachePort : public CpuPort 942623SN/A { 952623SN/A public: 962623SN/A 972623SN/A IcachePort(TimingSimpleCPU *_cpu) 982640Sstever@eecs.umich.edu : CpuPort(_cpu->name() + "-iport", _cpu) 992623SN/A { } 1002623SN/A 1012623SN/A protected: 1022623SN/A 1032630SN/A virtual bool recvTiming(Packet *pkt); 1042623SN/A 1052657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1062623SN/A }; 1072623SN/A 1082623SN/A class DcachePort : public CpuPort 1092623SN/A { 1102623SN/A public: 1112623SN/A 1122623SN/A DcachePort(TimingSimpleCPU *_cpu) 1132640Sstever@eecs.umich.edu : CpuPort(_cpu->name() + "-dport", _cpu) 1142623SN/A { } 1152623SN/A 1162623SN/A protected: 1172623SN/A 1182630SN/A virtual bool recvTiming(Packet *pkt); 1192623SN/A 1202657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1212623SN/A }; 1222623SN/A 1232623SN/A IcachePort icachePort; 1242623SN/A DcachePort dcachePort; 1252623SN/A 1262623SN/A Packet *ifetch_pkt; 1272623SN/A Packet *dcache_pkt; 1282623SN/A 1292623SN/A public: 1302623SN/A 1312623SN/A virtual void serialize(std::ostream &os); 1322623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1332623SN/A 1342623SN/A void switchOut(Sampler *s); 1352623SN/A void takeOverFrom(BaseCPU *oldCPU); 1362623SN/A 1372623SN/A virtual void activateContext(int thread_num, int delay); 1382623SN/A virtual void suspendContext(int thread_num); 1392623SN/A 1402623SN/A template <class T> 1412623SN/A Fault read(Addr addr, T &data, unsigned flags); 1422623SN/A 1432623SN/A template <class T> 1442623SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1452623SN/A 1462623SN/A void fetch(); 1472644Sstever@eecs.umich.edu void completeIfetch(Packet *); 1482623SN/A void completeDataAccess(Packet *); 1492644Sstever@eecs.umich.edu void advanceInst(Fault fault); 1502623SN/A}; 1512623SN/A 1522623SN/A#endif // __CPU_SIMPLE_TIMING_HH__ 153