timing.hh revision 11148 
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_TIMING_HH__
44#define __CPU_SIMPLE_TIMING_HH__
45
46#include "cpu/simple/base.hh"
47#include "cpu/simple/exec_context.hh"
48#include "cpu/translation.hh"
49#include "params/TimingSimpleCPU.hh"
50
51class TimingSimpleCPU : public BaseSimpleCPU
52{
53  public:
54
55    TimingSimpleCPU(TimingSimpleCPUParams * params);
56    virtual ~TimingSimpleCPU();
57
58    virtual void init();
59
60  private:
61
62    /*
63     * If an access needs to be broken into fragments, currently at most two,
64     * the the following two classes are used as the sender state of the
65     * packets so the CPU can keep track of everything. In the main packet
66     * sender state, there's an array with a spot for each fragment. If a
67     * fragment has already been accepted by the CPU, aka isn't waiting for
68     * a retry, it's pointer is NULL. After each fragment has successfully
69     * been processed, the "outstanding" counter is decremented. Once the
70     * count is zero, the entire larger access is complete.
71     */
72    class SplitMainSenderState : public Packet::SenderState
73    {
74      public:
75        int outstanding;
76        PacketPtr fragments[2];
77
78        int
79        getPendingFragment()
80        {
81            if (fragments[0]) {
82                return 0;
83            } else if (fragments[1]) {
84                return 1;
85            } else {
86                return -1;
87            }
88        }
89    };
90
91    class SplitFragmentSenderState : public Packet::SenderState
92    {
93      public:
94        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
95            bigPkt(_bigPkt), index(_index)
96        {}
97        PacketPtr bigPkt;
98        int index;
99
100        void
101        clearFromParent()
102        {
103            SplitMainSenderState * main_send_state =
104                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
105            main_send_state->fragments[index] = NULL;
106        }
107    };
108
109    class FetchTranslation : public BaseTLB::Translation
110    {
111      protected:
112        TimingSimpleCPU *cpu;
113
114      public:
115        FetchTranslation(TimingSimpleCPU *_cpu)
116            : cpu(_cpu)
117        {}
118
119        void
120        markDelayed()
121        {
122            assert(cpu->_status == BaseSimpleCPU::Running);
123            cpu->_status = ITBWaitResponse;
124        }
125
126        void
127        finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
128               BaseTLB::Mode mode)
129        {
130            cpu->sendFetch(fault, req, tc);
131        }
132    };
133    FetchTranslation fetchTranslation;
134
135    void threadSnoop(PacketPtr pkt, ThreadID sender);
136    void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
137    void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
138                       uint8_t *data, bool read);
139
140    void translationFault(const Fault &fault);
141
142    PacketPtr buildPacket(RequestPtr req, bool read);
143    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
144            RequestPtr req1, RequestPtr req2, RequestPtr req,
145            uint8_t *data, bool read);
146
147    bool handleReadPacket(PacketPtr pkt);
148    // This function always implicitly uses dcache_pkt.
149    bool handleWritePacket();
150
151    /**
152     * A TimingCPUPort overrides the default behaviour of the
153     * recvTiming and recvRetry and implements events for the
154     * scheduling of handling of incoming packets in the following
155     * cycle.
156     */
157    class TimingCPUPort : public MasterPort
158    {
159      public:
160
161        TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
162            : MasterPort(_name, _cpu), cpu(_cpu), retryRespEvent(this)
163        { }
164
165      protected:
166
167        /**
168         * Snooping a coherence request, do nothing.
169         */
170        virtual void recvTimingSnoopReq(PacketPtr pkt) {}
171
172        TimingSimpleCPU* cpu;
173
174        struct TickEvent : public Event
175        {
176            PacketPtr pkt;
177            TimingSimpleCPU *cpu;
178
179            TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
180            const char *description() const { return "Timing CPU tick"; }
181            void schedule(PacketPtr _pkt, Tick t);
182        };
183
184        EventWrapper<MasterPort, &MasterPort::sendRetryResp> retryRespEvent;
185    };
186
187    class IcachePort : public TimingCPUPort
188    {
189      public:
190
191        IcachePort(TimingSimpleCPU *_cpu)
192            : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
193              tickEvent(_cpu)
194        { }
195
196      protected:
197
198        virtual bool recvTimingResp(PacketPtr pkt);
199
200        virtual void recvReqRetry();
201
202        struct ITickEvent : public TickEvent
203        {
204
205            ITickEvent(TimingSimpleCPU *_cpu)
206                : TickEvent(_cpu) {}
207            void process();
208            const char *description() const { return "Timing CPU icache tick"; }
209        };
210
211        ITickEvent tickEvent;
212
213    };
214
215    class DcachePort : public TimingCPUPort
216    {
217      public:
218
219        DcachePort(TimingSimpleCPU *_cpu)
220            : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
221              tickEvent(_cpu)
222        {
223           cacheBlockMask = ~(cpu->cacheLineSize() - 1);
224        }
225
226        Addr cacheBlockMask;
227      protected:
228
229        /** Snoop a coherence request, we need to check if this causes
230         * a wakeup event on a cpu that is monitoring an address
231         */
232        virtual void recvTimingSnoopReq(PacketPtr pkt);
233        virtual void recvFunctionalSnoop(PacketPtr pkt);
234
235        virtual bool recvTimingResp(PacketPtr pkt);
236
237        virtual void recvReqRetry();
238
239        virtual bool isSnooping() const {
240            return true;
241        }
242
243        struct DTickEvent : public TickEvent
244        {
245            DTickEvent(TimingSimpleCPU *_cpu)
246                : TickEvent(_cpu) {}
247            void process();
248            const char *description() const { return "Timing CPU dcache tick"; }
249        };
250
251        DTickEvent tickEvent;
252
253    };
254
255    void updateCycleCounts();
256
257    IcachePort icachePort;
258    DcachePort dcachePort;
259
260    PacketPtr ifetch_pkt;
261    PacketPtr dcache_pkt;
262
263    Cycles previousCycle;
264
265  protected:
266
267     /** Return a reference to the data port. */
268    virtual MasterPort &getDataPort() { return dcachePort; }
269
270    /** Return a reference to the instruction port. */
271    virtual MasterPort &getInstPort() { return icachePort; }
272
273  public:
274
275    DrainState drain() M5_ATTR_OVERRIDE;
276    void drainResume() M5_ATTR_OVERRIDE;
277
278    void switchOut();
279    void takeOverFrom(BaseCPU *oldCPU);
280
281    void verifyMemoryMode() const;
282
283    virtual void activateContext(ThreadID thread_num);
284    virtual void suspendContext(ThreadID thread_num);
285
286    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
287
288    Fault writeMem(uint8_t *data, unsigned size,
289                   Addr addr, unsigned flags, uint64_t *res);
290
291    void fetch();
292    void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
293    void completeIfetch(PacketPtr );
294    void completeDataAccess(PacketPtr pkt);
295    void advanceInst(const Fault &fault);
296
297    /** This function is used by the page table walker to determine if it could
298     * translate the a pending request or if the underlying request has been
299     * squashed. This always returns false for the simple timing CPU as it never
300     * executes any instructions speculatively.
301     * @ return Is the current instruction squashed?
302     */
303    bool isSquashed() const { return false; }
304
305    /**
306     * Print state of address in memory system via PrintReq (for
307     * debugging).
308     */
309    void printAddr(Addr a);
310
311    /**
312     * Finish a DTB translation.
313     * @param state The DTB translation state.
314     */
315    void finishTranslation(WholeTranslationState *state);
316
317  private:
318
319    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
320    FetchEvent fetchEvent;
321
322    struct IprEvent : Event {
323        Packet *pkt;
324        TimingSimpleCPU *cpu;
325        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
326        virtual void process();
327        virtual const char *description() const;
328    };
329
330    /**
331     * Check if a system is in a drained state.
332     *
333     * We need to drain if:
334     * <ul>
335     * <li>We are in the middle of a microcode sequence as some CPUs
336     *     (e.g., HW accelerated CPUs) can't be started in the middle
337     *     of a gem5 microcode sequence.
338     *
339     * <li>Stay at PC is true.
340     *
341     * <li>A fetch event is scheduled. Normally this would never be the
342     *     case with microPC() == 0, but right after a context is
343     *     activated it can happen.
344     * </ul>
345     */
346    bool isDrained() {
347        SimpleExecContext& t_info = *threadInfo[curThread];
348        SimpleThread* thread = t_info.thread;
349
350        return thread->microPC() == 0 && !t_info.stayAtPC &&
351               !fetchEvent.scheduled();
352    }
353
354    /**
355     * Try to complete a drain request.
356     *
357     * @returns true if the CPU is drained, false otherwise.
358     */
359    bool tryCompleteDrain();
360};
361
362#endif // __CPU_SIMPLE_TIMING_HH__
363