timing.cc revision 9152
112226Sgiacomo.travaglini@arm.com/* 212226Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2012 ARM Limited 312226Sgiacomo.travaglini@arm.com * All rights reserved 412226Sgiacomo.travaglini@arm.com * 512226Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612226Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712226Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812226Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912226Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012226Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112226Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212226Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312226Sgiacomo.travaglini@arm.com * 1412226Sgiacomo.travaglini@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1512226Sgiacomo.travaglini@arm.com * All rights reserved. 1612226Sgiacomo.travaglini@arm.com * 1712226Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1812226Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1912226Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 2012226Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 2112226Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 2212226Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2312226Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2412226Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2512226Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2612226Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2712226Sgiacomo.travaglini@arm.com * 2812226Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912226Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012226Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112226Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212226Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312226Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412226Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512226Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612226Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712226Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812226Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912226Sgiacomo.travaglini@arm.com * 4012226Sgiacomo.travaglini@arm.com * Authors: Steve Reinhardt 4112226Sgiacomo.travaglini@arm.com */ 4212226Sgiacomo.travaglini@arm.com 4312226Sgiacomo.travaglini@arm.com#include "arch/locked_mem.hh" 4412226Sgiacomo.travaglini@arm.com#include "arch/mmapped_ipr.hh" 4512226Sgiacomo.travaglini@arm.com#include "arch/utility.hh" 4612226Sgiacomo.travaglini@arm.com#include "base/bigint.hh" 4712226Sgiacomo.travaglini@arm.com#include "config/the_isa.hh" 4812226Sgiacomo.travaglini@arm.com#include "cpu/simple/timing.hh" 4912226Sgiacomo.travaglini@arm.com#include "cpu/exetrace.hh" 5012226Sgiacomo.travaglini@arm.com#include "debug/Config.hh" 5112226Sgiacomo.travaglini@arm.com#include "debug/Drain.hh" 5212226Sgiacomo.travaglini@arm.com#include "debug/ExecFaulting.hh" 5312226Sgiacomo.travaglini@arm.com#include "debug/SimpleCPU.hh" 5412226Sgiacomo.travaglini@arm.com#include "mem/packet.hh" 5512226Sgiacomo.travaglini@arm.com#include "mem/packet_access.hh" 5612226Sgiacomo.travaglini@arm.com#include "params/TimingSimpleCPU.hh" 5712226Sgiacomo.travaglini@arm.com#include "sim/faults.hh" 5812226Sgiacomo.travaglini@arm.com#include "sim/full_system.hh" 5912226Sgiacomo.travaglini@arm.com#include "sim/system.hh" 6012226Sgiacomo.travaglini@arm.com 6112226Sgiacomo.travaglini@arm.comusing namespace std; 6212226Sgiacomo.travaglini@arm.comusing namespace TheISA; 6312226Sgiacomo.travaglini@arm.com 6412226Sgiacomo.travaglini@arm.comvoid 6512226Sgiacomo.travaglini@arm.comTimingSimpleCPU::init() 6612226Sgiacomo.travaglini@arm.com{ 6712226Sgiacomo.travaglini@arm.com BaseCPU::init(); 68 69 // Initialise the ThreadContext's memory proxies 70 tcBase()->initMemProxies(tcBase()); 71 72 if (FullSystem && !params()->defer_registration) { 73 for (int i = 0; i < threadContexts.size(); ++i) { 74 ThreadContext *tc = threadContexts[i]; 75 // initialize CPU, including PC 76 TheISA::initCPU(tc, _cpuId); 77 } 78 } 79} 80 81void 82TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 83{ 84 pkt = _pkt; 85 cpu->schedule(this, t); 86} 87 88TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 89 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 90 dcachePort(this), fetchEvent(this) 91{ 92 _status = Idle; 93 94 ifetch_pkt = dcache_pkt = NULL; 95 drainEvent = NULL; 96 previousTick = 0; 97 changeState(SimObject::Running); 98 system->totalNumInsts = 0; 99} 100 101 102TimingSimpleCPU::~TimingSimpleCPU() 103{ 104} 105 106void 107TimingSimpleCPU::serialize(ostream &os) 108{ 109 SimObject::State so_state = SimObject::getState(); 110 SERIALIZE_ENUM(so_state); 111 BaseSimpleCPU::serialize(os); 112} 113 114void 115TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 116{ 117 SimObject::State so_state; 118 UNSERIALIZE_ENUM(so_state); 119 BaseSimpleCPU::unserialize(cp, section); 120} 121 122unsigned int 123TimingSimpleCPU::drain(Event *drain_event) 124{ 125 // TimingSimpleCPU is ready to drain if it's not waiting for 126 // an access to complete. 127 if (_status == Idle || _status == Running || _status == SwitchedOut) { 128 changeState(SimObject::Drained); 129 return 0; 130 } else { 131 changeState(SimObject::Draining); 132 drainEvent = drain_event; 133 DPRINTF(Drain, "CPU not drained\n"); 134 return 1; 135 } 136} 137 138void 139TimingSimpleCPU::resume() 140{ 141 DPRINTF(SimpleCPU, "Resume\n"); 142 if (_status != SwitchedOut && _status != Idle) { 143 assert(system->getMemoryMode() == Enums::timing); 144 145 if (fetchEvent.scheduled()) 146 deschedule(fetchEvent); 147 148 schedule(fetchEvent, nextCycle()); 149 } 150 151 changeState(SimObject::Running); 152} 153 154void 155TimingSimpleCPU::switchOut() 156{ 157 assert(_status == Running || _status == Idle); 158 _status = SwitchedOut; 159 numCycles += tickToCycles(curTick() - previousTick); 160 161 // If we've been scheduled to resume but are then told to switch out, 162 // we'll need to cancel it. 163 if (fetchEvent.scheduled()) 164 deschedule(fetchEvent); 165} 166 167 168void 169TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 170{ 171 BaseCPU::takeOverFrom(oldCPU); 172 173 // if any of this CPU's ThreadContexts are active, mark the CPU as 174 // running and schedule its tick event. 175 for (int i = 0; i < threadContexts.size(); ++i) { 176 ThreadContext *tc = threadContexts[i]; 177 if (tc->status() == ThreadContext::Active && _status != Running) { 178 _status = Running; 179 break; 180 } 181 } 182 183 if (_status != Running) { 184 _status = Idle; 185 } 186 assert(threadContexts.size() == 1); 187 previousTick = curTick(); 188} 189 190 191void 192TimingSimpleCPU::activateContext(ThreadID thread_num, int delay) 193{ 194 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 195 196 assert(thread_num == 0); 197 assert(thread); 198 199 assert(_status == Idle); 200 201 notIdleFraction++; 202 _status = Running; 203 204 // kick things off by initiating the fetch of the next instruction 205 schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 206} 207 208 209void 210TimingSimpleCPU::suspendContext(ThreadID thread_num) 211{ 212 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 213 214 assert(thread_num == 0); 215 assert(thread); 216 217 if (_status == Idle) 218 return; 219 220 assert(_status == Running); 221 222 // just change status to Idle... if status != Running, 223 // completeInst() will not initiate fetch of next instruction. 224 225 notIdleFraction--; 226 _status = Idle; 227} 228 229bool 230TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 231{ 232 RequestPtr req = pkt->req; 233 if (req->isMmappedIpr()) { 234 Tick delay; 235 delay = TheISA::handleIprRead(thread->getTC(), pkt); 236 new IprEvent(pkt, this, nextCycle(curTick() + delay)); 237 _status = DcacheWaitResponse; 238 dcache_pkt = NULL; 239 } else if (!dcachePort.sendTimingReq(pkt)) { 240 _status = DcacheRetry; 241 dcache_pkt = pkt; 242 } else { 243 _status = DcacheWaitResponse; 244 // memory system takes ownership of packet 245 dcache_pkt = NULL; 246 } 247 return dcache_pkt == NULL; 248} 249 250void 251TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 252 bool read) 253{ 254 PacketPtr pkt; 255 buildPacket(pkt, req, read); 256 pkt->dataDynamicArray<uint8_t>(data); 257 if (req->getFlags().isSet(Request::NO_ACCESS)) { 258 assert(!dcache_pkt); 259 pkt->makeResponse(); 260 completeDataAccess(pkt); 261 } else if (read) { 262 handleReadPacket(pkt); 263 } else { 264 bool do_access = true; // flag to suppress cache access 265 266 if (req->isLLSC()) { 267 do_access = TheISA::handleLockedWrite(thread, req); 268 } else if (req->isCondSwap()) { 269 assert(res); 270 req->setExtraData(*res); 271 } 272 273 if (do_access) { 274 dcache_pkt = pkt; 275 handleWritePacket(); 276 } else { 277 _status = DcacheWaitResponse; 278 completeDataAccess(pkt); 279 } 280 } 281} 282 283void 284TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 285 RequestPtr req, uint8_t *data, bool read) 286{ 287 PacketPtr pkt1, pkt2; 288 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 289 if (req->getFlags().isSet(Request::NO_ACCESS)) { 290 assert(!dcache_pkt); 291 pkt1->makeResponse(); 292 completeDataAccess(pkt1); 293 } else if (read) { 294 SplitFragmentSenderState * send_state = 295 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 296 if (handleReadPacket(pkt1)) { 297 send_state->clearFromParent(); 298 send_state = dynamic_cast<SplitFragmentSenderState *>( 299 pkt2->senderState); 300 if (handleReadPacket(pkt2)) { 301 send_state->clearFromParent(); 302 } 303 } 304 } else { 305 dcache_pkt = pkt1; 306 SplitFragmentSenderState * send_state = 307 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 308 if (handleWritePacket()) { 309 send_state->clearFromParent(); 310 dcache_pkt = pkt2; 311 send_state = dynamic_cast<SplitFragmentSenderState *>( 312 pkt2->senderState); 313 if (handleWritePacket()) { 314 send_state->clearFromParent(); 315 } 316 } 317 } 318} 319 320void 321TimingSimpleCPU::translationFault(Fault fault) 322{ 323 // fault may be NoFault in cases where a fault is suppressed, 324 // for instance prefetches. 325 numCycles += tickToCycles(curTick() - previousTick); 326 previousTick = curTick(); 327 328 if (traceData) { 329 // Since there was a fault, we shouldn't trace this instruction. 330 delete traceData; 331 traceData = NULL; 332 } 333 334 postExecute(); 335 336 if (getState() == SimObject::Draining) { 337 advancePC(fault); 338 completeDrain(); 339 } else { 340 advanceInst(fault); 341 } 342} 343 344void 345TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 346{ 347 MemCmd cmd; 348 if (read) { 349 cmd = MemCmd::ReadReq; 350 if (req->isLLSC()) 351 cmd = MemCmd::LoadLockedReq; 352 } else { 353 cmd = MemCmd::WriteReq; 354 if (req->isLLSC()) { 355 cmd = MemCmd::StoreCondReq; 356 } else if (req->isSwap()) { 357 cmd = MemCmd::SwapReq; 358 } 359 } 360 pkt = new Packet(req, cmd); 361} 362 363void 364TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 365 RequestPtr req1, RequestPtr req2, RequestPtr req, 366 uint8_t *data, bool read) 367{ 368 pkt1 = pkt2 = NULL; 369 370 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 371 372 if (req->getFlags().isSet(Request::NO_ACCESS)) { 373 buildPacket(pkt1, req, read); 374 return; 375 } 376 377 buildPacket(pkt1, req1, read); 378 buildPacket(pkt2, req2, read); 379 380 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 381 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 382 383 pkt->dataDynamicArray<uint8_t>(data); 384 pkt1->dataStatic<uint8_t>(data); 385 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 386 387 SplitMainSenderState * main_send_state = new SplitMainSenderState; 388 pkt->senderState = main_send_state; 389 main_send_state->fragments[0] = pkt1; 390 main_send_state->fragments[1] = pkt2; 391 main_send_state->outstanding = 2; 392 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 393 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 394} 395 396Fault 397TimingSimpleCPU::readMem(Addr addr, uint8_t *data, 398 unsigned size, unsigned flags) 399{ 400 Fault fault; 401 const int asid = 0; 402 const ThreadID tid = 0; 403 const Addr pc = thread->instAddr(); 404 unsigned block_size = dcachePort.peerBlockSize(); 405 BaseTLB::Mode mode = BaseTLB::Read; 406 407 if (traceData) { 408 traceData->setAddr(addr); 409 } 410 411 RequestPtr req = new Request(asid, addr, size, 412 flags, dataMasterId(), pc, _cpuId, tid); 413 414 Addr split_addr = roundDown(addr + size - 1, block_size); 415 assert(split_addr <= addr || split_addr - addr < block_size); 416 417 _status = DTBWaitResponse; 418 if (split_addr > addr) { 419 RequestPtr req1, req2; 420 assert(!req->isLLSC() && !req->isSwap()); 421 req->splitOnVaddr(split_addr, req1, req2); 422 423 WholeTranslationState *state = 424 new WholeTranslationState(req, req1, req2, new uint8_t[size], 425 NULL, mode); 426 DataTranslation<TimingSimpleCPU *> *trans1 = 427 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 428 DataTranslation<TimingSimpleCPU *> *trans2 = 429 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 430 431 thread->dtb->translateTiming(req1, tc, trans1, mode); 432 thread->dtb->translateTiming(req2, tc, trans2, mode); 433 } else { 434 WholeTranslationState *state = 435 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 436 DataTranslation<TimingSimpleCPU *> *translation 437 = new DataTranslation<TimingSimpleCPU *>(this, state); 438 thread->dtb->translateTiming(req, tc, translation, mode); 439 } 440 441 return NoFault; 442} 443 444bool 445TimingSimpleCPU::handleWritePacket() 446{ 447 RequestPtr req = dcache_pkt->req; 448 if (req->isMmappedIpr()) { 449 Tick delay; 450 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 451 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 452 _status = DcacheWaitResponse; 453 dcache_pkt = NULL; 454 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 455 _status = DcacheRetry; 456 } else { 457 _status = DcacheWaitResponse; 458 // memory system takes ownership of packet 459 dcache_pkt = NULL; 460 } 461 return dcache_pkt == NULL; 462} 463 464Fault 465TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 466 Addr addr, unsigned flags, uint64_t *res) 467{ 468 uint8_t *newData = new uint8_t[size]; 469 memcpy(newData, data, size); 470 471 const int asid = 0; 472 const ThreadID tid = 0; 473 const Addr pc = thread->instAddr(); 474 unsigned block_size = dcachePort.peerBlockSize(); 475 BaseTLB::Mode mode = BaseTLB::Write; 476 477 if (traceData) { 478 traceData->setAddr(addr); 479 } 480 481 RequestPtr req = new Request(asid, addr, size, 482 flags, dataMasterId(), pc, _cpuId, tid); 483 484 Addr split_addr = roundDown(addr + size - 1, block_size); 485 assert(split_addr <= addr || split_addr - addr < block_size); 486 487 _status = DTBWaitResponse; 488 if (split_addr > addr) { 489 RequestPtr req1, req2; 490 assert(!req->isLLSC() && !req->isSwap()); 491 req->splitOnVaddr(split_addr, req1, req2); 492 493 WholeTranslationState *state = 494 new WholeTranslationState(req, req1, req2, newData, res, mode); 495 DataTranslation<TimingSimpleCPU *> *trans1 = 496 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 497 DataTranslation<TimingSimpleCPU *> *trans2 = 498 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 499 500 thread->dtb->translateTiming(req1, tc, trans1, mode); 501 thread->dtb->translateTiming(req2, tc, trans2, mode); 502 } else { 503 WholeTranslationState *state = 504 new WholeTranslationState(req, newData, res, mode); 505 DataTranslation<TimingSimpleCPU *> *translation = 506 new DataTranslation<TimingSimpleCPU *>(this, state); 507 thread->dtb->translateTiming(req, tc, translation, mode); 508 } 509 510 // Translation faults will be returned via finishTranslation() 511 return NoFault; 512} 513 514 515void 516TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 517{ 518 _status = Running; 519 520 if (state->getFault() != NoFault) { 521 if (state->isPrefetch()) { 522 state->setNoFault(); 523 } 524 delete [] state->data; 525 state->deleteReqs(); 526 translationFault(state->getFault()); 527 } else { 528 if (!state->isSplit) { 529 sendData(state->mainReq, state->data, state->res, 530 state->mode == BaseTLB::Read); 531 } else { 532 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 533 state->data, state->mode == BaseTLB::Read); 534 } 535 } 536 537 delete state; 538} 539 540 541void 542TimingSimpleCPU::fetch() 543{ 544 DPRINTF(SimpleCPU, "Fetch\n"); 545 546 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 547 checkForInterrupts(); 548 549 checkPcEventQueue(); 550 551 // We must have just got suspended by a PC event 552 if (_status == Idle) 553 return; 554 555 TheISA::PCState pcState = thread->pcState(); 556 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 557 558 if (needToFetch) { 559 _status = Running; 560 Request *ifetch_req = new Request(); 561 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 562 setupFetchRequest(ifetch_req); 563 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 564 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 565 BaseTLB::Execute); 566 } else { 567 _status = IcacheWaitResponse; 568 completeIfetch(NULL); 569 570 numCycles += tickToCycles(curTick() - previousTick); 571 previousTick = curTick(); 572 } 573} 574 575 576void 577TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 578{ 579 if (fault == NoFault) { 580 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 581 req->getVaddr(), req->getPaddr()); 582 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 583 ifetch_pkt->dataStatic(&inst); 584 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 585 586 if (!icachePort.sendTimingReq(ifetch_pkt)) { 587 // Need to wait for retry 588 _status = IcacheRetry; 589 } else { 590 // Need to wait for cache to respond 591 _status = IcacheWaitResponse; 592 // ownership of packet transferred to memory system 593 ifetch_pkt = NULL; 594 } 595 } else { 596 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 597 delete req; 598 // fetch fault: advance directly to next instruction (fault handler) 599 _status = Running; 600 advanceInst(fault); 601 } 602 603 numCycles += tickToCycles(curTick() - previousTick); 604 previousTick = curTick(); 605} 606 607 608void 609TimingSimpleCPU::advanceInst(Fault fault) 610{ 611 612 if (_status == Faulting) 613 return; 614 615 if (fault != NoFault) { 616 advancePC(fault); 617 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 618 reschedule(fetchEvent, nextCycle(), true); 619 _status = Faulting; 620 return; 621 } 622 623 624 if (!stayAtPC) 625 advancePC(fault); 626 627 if (_status == Running) { 628 // kick off fetch of next instruction... callback from icache 629 // response will cause that instruction to be executed, 630 // keeping the CPU running. 631 fetch(); 632 } 633} 634 635 636void 637TimingSimpleCPU::completeIfetch(PacketPtr pkt) 638{ 639 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 640 pkt->getAddr() : 0); 641 642 // received a response from the icache: execute the received 643 // instruction 644 645 assert(!pkt || !pkt->isError()); 646 assert(_status == IcacheWaitResponse); 647 648 _status = Running; 649 650 numCycles += tickToCycles(curTick() - previousTick); 651 previousTick = curTick(); 652 653 if (getState() == SimObject::Draining) { 654 if (pkt) { 655 delete pkt->req; 656 delete pkt; 657 } 658 659 completeDrain(); 660 return; 661 } 662 663 preExecute(); 664 if (curStaticInst && curStaticInst->isMemRef()) { 665 // load or store: just send to dcache 666 Fault fault = curStaticInst->initiateAcc(this, traceData); 667 668 // If we're not running now the instruction will complete in a dcache 669 // response callback or the instruction faulted and has started an 670 // ifetch 671 if (_status == Running) { 672 if (fault != NoFault && traceData) { 673 // If there was a fault, we shouldn't trace this instruction. 674 delete traceData; 675 traceData = NULL; 676 } 677 678 postExecute(); 679 // @todo remove me after debugging with legion done 680 if (curStaticInst && (!curStaticInst->isMicroop() || 681 curStaticInst->isFirstMicroop())) 682 instCnt++; 683 advanceInst(fault); 684 } 685 } else if (curStaticInst) { 686 // non-memory instruction: execute completely now 687 Fault fault = curStaticInst->execute(this, traceData); 688 689 // keep an instruction count 690 if (fault == NoFault) 691 countInst(); 692 else if (traceData && !DTRACE(ExecFaulting)) { 693 delete traceData; 694 traceData = NULL; 695 } 696 697 postExecute(); 698 // @todo remove me after debugging with legion done 699 if (curStaticInst && (!curStaticInst->isMicroop() || 700 curStaticInst->isFirstMicroop())) 701 instCnt++; 702 advanceInst(fault); 703 } else { 704 advanceInst(NoFault); 705 } 706 707 if (pkt) { 708 delete pkt->req; 709 delete pkt; 710 } 711} 712 713void 714TimingSimpleCPU::IcachePort::ITickEvent::process() 715{ 716 cpu->completeIfetch(pkt); 717} 718 719bool 720TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 721{ 722 if (!pkt->wasNacked()) { 723 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 724 // delay processing of returned data until next CPU clock edge 725 Tick next_tick = cpu->nextCycle(curTick()); 726 727 if (next_tick == curTick()) 728 cpu->completeIfetch(pkt); 729 else 730 tickEvent.schedule(pkt, next_tick); 731 732 return true; 733 } else { 734 assert(cpu->_status == IcacheWaitResponse); 735 pkt->reinitNacked(); 736 if (!sendTimingReq(pkt)) { 737 cpu->_status = IcacheRetry; 738 cpu->ifetch_pkt = pkt; 739 } 740 } 741 742 return true; 743} 744 745void 746TimingSimpleCPU::IcachePort::recvRetry() 747{ 748 // we shouldn't get a retry unless we have a packet that we're 749 // waiting to transmit 750 assert(cpu->ifetch_pkt != NULL); 751 assert(cpu->_status == IcacheRetry); 752 PacketPtr tmp = cpu->ifetch_pkt; 753 if (sendTimingReq(tmp)) { 754 cpu->_status = IcacheWaitResponse; 755 cpu->ifetch_pkt = NULL; 756 } 757} 758 759void 760TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 761{ 762 // received a response from the dcache: complete the load or store 763 // instruction 764 assert(!pkt->isError()); 765 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 766 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 767 768 numCycles += tickToCycles(curTick() - previousTick); 769 previousTick = curTick(); 770 771 if (pkt->senderState) { 772 SplitFragmentSenderState * send_state = 773 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 774 assert(send_state); 775 delete pkt->req; 776 delete pkt; 777 PacketPtr big_pkt = send_state->bigPkt; 778 delete send_state; 779 780 SplitMainSenderState * main_send_state = 781 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 782 assert(main_send_state); 783 // Record the fact that this packet is no longer outstanding. 784 assert(main_send_state->outstanding != 0); 785 main_send_state->outstanding--; 786 787 if (main_send_state->outstanding) { 788 return; 789 } else { 790 delete main_send_state; 791 big_pkt->senderState = NULL; 792 pkt = big_pkt; 793 } 794 } 795 796 _status = Running; 797 798 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 799 800 // keep an instruction count 801 if (fault == NoFault) 802 countInst(); 803 else if (traceData) { 804 // If there was a fault, we shouldn't trace this instruction. 805 delete traceData; 806 traceData = NULL; 807 } 808 809 // the locked flag may be cleared on the response packet, so check 810 // pkt->req and not pkt to see if it was a load-locked 811 if (pkt->isRead() && pkt->req->isLLSC()) { 812 TheISA::handleLockedRead(thread, pkt->req); 813 } 814 815 delete pkt->req; 816 delete pkt; 817 818 postExecute(); 819 820 if (getState() == SimObject::Draining) { 821 advancePC(fault); 822 completeDrain(); 823 824 return; 825 } 826 827 advanceInst(fault); 828} 829 830 831void 832TimingSimpleCPU::completeDrain() 833{ 834 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 835 changeState(SimObject::Drained); 836 drainEvent->process(); 837} 838 839bool 840TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 841{ 842 if (!pkt->wasNacked()) { 843 // delay processing of returned data until next CPU clock edge 844 Tick next_tick = cpu->nextCycle(curTick()); 845 846 if (next_tick == curTick()) { 847 cpu->completeDataAccess(pkt); 848 } else { 849 if (!tickEvent.scheduled()) { 850 tickEvent.schedule(pkt, next_tick); 851 } else { 852 // In the case of a split transaction and a cache that is 853 // faster than a CPU we could get two responses before 854 // next_tick expires 855 if (!retryEvent.scheduled()) 856 cpu->schedule(retryEvent, next_tick); 857 return false; 858 } 859 } 860 861 return true; 862 } else { 863 assert(cpu->_status == DcacheWaitResponse); 864 pkt->reinitNacked(); 865 if (!sendTimingReq(pkt)) { 866 cpu->_status = DcacheRetry; 867 cpu->dcache_pkt = pkt; 868 } 869 } 870 871 return true; 872} 873 874void 875TimingSimpleCPU::DcachePort::DTickEvent::process() 876{ 877 cpu->completeDataAccess(pkt); 878} 879 880void 881TimingSimpleCPU::DcachePort::recvRetry() 882{ 883 // we shouldn't get a retry unless we have a packet that we're 884 // waiting to transmit 885 assert(cpu->dcache_pkt != NULL); 886 assert(cpu->_status == DcacheRetry); 887 PacketPtr tmp = cpu->dcache_pkt; 888 if (tmp->senderState) { 889 // This is a packet from a split access. 890 SplitFragmentSenderState * send_state = 891 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 892 assert(send_state); 893 PacketPtr big_pkt = send_state->bigPkt; 894 895 SplitMainSenderState * main_send_state = 896 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 897 assert(main_send_state); 898 899 if (sendTimingReq(tmp)) { 900 // If we were able to send without retrying, record that fact 901 // and try sending the other fragment. 902 send_state->clearFromParent(); 903 int other_index = main_send_state->getPendingFragment(); 904 if (other_index > 0) { 905 tmp = main_send_state->fragments[other_index]; 906 cpu->dcache_pkt = tmp; 907 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 908 (big_pkt->isWrite() && cpu->handleWritePacket())) { 909 main_send_state->fragments[other_index] = NULL; 910 } 911 } else { 912 cpu->_status = DcacheWaitResponse; 913 // memory system takes ownership of packet 914 cpu->dcache_pkt = NULL; 915 } 916 } 917 } else if (sendTimingReq(tmp)) { 918 cpu->_status = DcacheWaitResponse; 919 // memory system takes ownership of packet 920 cpu->dcache_pkt = NULL; 921 } 922} 923 924TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 925 Tick t) 926 : pkt(_pkt), cpu(_cpu) 927{ 928 cpu->schedule(this, t); 929} 930 931void 932TimingSimpleCPU::IprEvent::process() 933{ 934 cpu->completeDataAccess(pkt); 935} 936 937const char * 938TimingSimpleCPU::IprEvent::description() const 939{ 940 return "Timing Simple CPU Delay IPR event"; 941} 942 943 944void 945TimingSimpleCPU::printAddr(Addr a) 946{ 947 dcachePort.printAddr(a); 948} 949 950 951//////////////////////////////////////////////////////////////////////// 952// 953// TimingSimpleCPU Simulation Object 954// 955TimingSimpleCPU * 956TimingSimpleCPUParams::create() 957{ 958 numThreads = 1; 959 if (!FullSystem && workload.size() != 1) 960 panic("only one workload allowed"); 961 return new TimingSimpleCPU(this); 962} 963