timing.cc revision 8277:bfaab04cb292
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#include "arch/locked_mem.hh" 44#include "arch/mmapped_ipr.hh" 45#include "arch/utility.hh" 46#include "base/bigint.hh" 47#include "config/the_isa.hh" 48#include "cpu/simple/timing.hh" 49#include "cpu/exetrace.hh" 50#include "debug/Config.hh" 51#include "debug/ExecFaulting.hh" 52#include "debug/SimpleCPU.hh" 53#include "mem/packet.hh" 54#include "mem/packet_access.hh" 55#include "params/TimingSimpleCPU.hh" 56#include "sim/faults.hh" 57#include "sim/system.hh" 58 59using namespace std; 60using namespace TheISA; 61 62Port * 63TimingSimpleCPU::getPort(const std::string &if_name, int idx) 64{ 65 if (if_name == "dcache_port") 66 return &dcachePort; 67 else if (if_name == "icache_port") 68 return &icachePort; 69 else 70 panic("No Such Port\n"); 71} 72 73void 74TimingSimpleCPU::init() 75{ 76 BaseCPU::init(); 77#if FULL_SYSTEM 78 for (int i = 0; i < threadContexts.size(); ++i) { 79 ThreadContext *tc = threadContexts[i]; 80 81 // initialize CPU, including PC 82 TheISA::initCPU(tc, _cpuId); 83 } 84#endif 85} 86 87Tick 88TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 89{ 90 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 91 return curTick(); 92} 93 94void 95TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 96{ 97 //No internal storage to update, jusst return 98 return; 99} 100 101void 102TimingSimpleCPU::CpuPort::recvStatusChange(Status status) 103{ 104 if (status == RangeChange) { 105 if (!snoopRangeSent) { 106 snoopRangeSent = true; 107 sendStatusChange(Port::RangeChange); 108 } 109 return; 110 } 111 112 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 113} 114 115 116void 117TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 118{ 119 pkt = _pkt; 120 cpu->schedule(this, t); 121} 122 123TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 124 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 125 dcachePort(this, p->clock), fetchEvent(this) 126{ 127 _status = Idle; 128 129 icachePort.snoopRangeSent = false; 130 dcachePort.snoopRangeSent = false; 131 132 ifetch_pkt = dcache_pkt = NULL; 133 drainEvent = NULL; 134 previousTick = 0; 135 changeState(SimObject::Running); 136 system->totalNumInsts = 0; 137} 138 139 140TimingSimpleCPU::~TimingSimpleCPU() 141{ 142} 143 144void 145TimingSimpleCPU::serialize(ostream &os) 146{ 147 SimObject::State so_state = SimObject::getState(); 148 SERIALIZE_ENUM(so_state); 149 BaseSimpleCPU::serialize(os); 150} 151 152void 153TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 154{ 155 SimObject::State so_state; 156 UNSERIALIZE_ENUM(so_state); 157 BaseSimpleCPU::unserialize(cp, section); 158} 159 160unsigned int 161TimingSimpleCPU::drain(Event *drain_event) 162{ 163 // TimingSimpleCPU is ready to drain if it's not waiting for 164 // an access to complete. 165 if (_status == Idle || _status == Running || _status == SwitchedOut) { 166 changeState(SimObject::Drained); 167 return 0; 168 } else { 169 changeState(SimObject::Draining); 170 drainEvent = drain_event; 171 return 1; 172 } 173} 174 175void 176TimingSimpleCPU::resume() 177{ 178 DPRINTF(SimpleCPU, "Resume\n"); 179 if (_status != SwitchedOut && _status != Idle) { 180 assert(system->getMemoryMode() == Enums::timing); 181 182 if (fetchEvent.scheduled()) 183 deschedule(fetchEvent); 184 185 schedule(fetchEvent, nextCycle()); 186 } 187 188 changeState(SimObject::Running); 189} 190 191void 192TimingSimpleCPU::switchOut() 193{ 194 assert(_status == Running || _status == Idle); 195 _status = SwitchedOut; 196 numCycles += tickToCycles(curTick() - previousTick); 197 198 // If we've been scheduled to resume but are then told to switch out, 199 // we'll need to cancel it. 200 if (fetchEvent.scheduled()) 201 deschedule(fetchEvent); 202} 203 204 205void 206TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 207{ 208 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 209 210 // if any of this CPU's ThreadContexts are active, mark the CPU as 211 // running and schedule its tick event. 212 for (int i = 0; i < threadContexts.size(); ++i) { 213 ThreadContext *tc = threadContexts[i]; 214 if (tc->status() == ThreadContext::Active && _status != Running) { 215 _status = Running; 216 break; 217 } 218 } 219 220 if (_status != Running) { 221 _status = Idle; 222 } 223 assert(threadContexts.size() == 1); 224 previousTick = curTick(); 225} 226 227 228void 229TimingSimpleCPU::activateContext(int thread_num, int delay) 230{ 231 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 232 233 assert(thread_num == 0); 234 assert(thread); 235 236 assert(_status == Idle); 237 238 notIdleFraction++; 239 _status = Running; 240 241 // kick things off by initiating the fetch of the next instruction 242 schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 243} 244 245 246void 247TimingSimpleCPU::suspendContext(int thread_num) 248{ 249 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 250 251 assert(thread_num == 0); 252 assert(thread); 253 254 if (_status == Idle) 255 return; 256 257 assert(_status == Running); 258 259 // just change status to Idle... if status != Running, 260 // completeInst() will not initiate fetch of next instruction. 261 262 notIdleFraction--; 263 _status = Idle; 264} 265 266bool 267TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 268{ 269 RequestPtr req = pkt->req; 270 if (req->isMmappedIpr()) { 271 Tick delay; 272 delay = TheISA::handleIprRead(thread->getTC(), pkt); 273 new IprEvent(pkt, this, nextCycle(curTick() + delay)); 274 _status = DcacheWaitResponse; 275 dcache_pkt = NULL; 276 } else if (!dcachePort.sendTiming(pkt)) { 277 _status = DcacheRetry; 278 dcache_pkt = pkt; 279 } else { 280 _status = DcacheWaitResponse; 281 // memory system takes ownership of packet 282 dcache_pkt = NULL; 283 } 284 return dcache_pkt == NULL; 285} 286 287void 288TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 289 bool read) 290{ 291 PacketPtr pkt; 292 buildPacket(pkt, req, read); 293 pkt->dataDynamicArray<uint8_t>(data); 294 if (req->getFlags().isSet(Request::NO_ACCESS)) { 295 assert(!dcache_pkt); 296 pkt->makeResponse(); 297 completeDataAccess(pkt); 298 } else if (read) { 299 handleReadPacket(pkt); 300 } else { 301 bool do_access = true; // flag to suppress cache access 302 303 if (req->isLLSC()) { 304 do_access = TheISA::handleLockedWrite(thread, req); 305 } else if (req->isCondSwap()) { 306 assert(res); 307 req->setExtraData(*res); 308 } 309 310 if (do_access) { 311 dcache_pkt = pkt; 312 handleWritePacket(); 313 } else { 314 _status = DcacheWaitResponse; 315 completeDataAccess(pkt); 316 } 317 } 318} 319 320void 321TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 322 RequestPtr req, uint8_t *data, bool read) 323{ 324 PacketPtr pkt1, pkt2; 325 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 326 if (req->getFlags().isSet(Request::NO_ACCESS)) { 327 assert(!dcache_pkt); 328 pkt1->makeResponse(); 329 completeDataAccess(pkt1); 330 } else if (read) { 331 SplitFragmentSenderState * send_state = 332 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 333 if (handleReadPacket(pkt1)) { 334 send_state->clearFromParent(); 335 send_state = dynamic_cast<SplitFragmentSenderState *>( 336 pkt2->senderState); 337 if (handleReadPacket(pkt2)) { 338 send_state->clearFromParent(); 339 } 340 } 341 } else { 342 dcache_pkt = pkt1; 343 SplitFragmentSenderState * send_state = 344 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 345 if (handleWritePacket()) { 346 send_state->clearFromParent(); 347 dcache_pkt = pkt2; 348 send_state = dynamic_cast<SplitFragmentSenderState *>( 349 pkt2->senderState); 350 if (handleWritePacket()) { 351 send_state->clearFromParent(); 352 } 353 } 354 } 355} 356 357void 358TimingSimpleCPU::translationFault(Fault fault) 359{ 360 // fault may be NoFault in cases where a fault is suppressed, 361 // for instance prefetches. 362 numCycles += tickToCycles(curTick() - previousTick); 363 previousTick = curTick(); 364 365 if (traceData) { 366 // Since there was a fault, we shouldn't trace this instruction. 367 delete traceData; 368 traceData = NULL; 369 } 370 371 postExecute(); 372 373 if (getState() == SimObject::Draining) { 374 advancePC(fault); 375 completeDrain(); 376 } else { 377 advanceInst(fault); 378 } 379} 380 381void 382TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 383{ 384 MemCmd cmd; 385 if (read) { 386 cmd = MemCmd::ReadReq; 387 if (req->isLLSC()) 388 cmd = MemCmd::LoadLockedReq; 389 } else { 390 cmd = MemCmd::WriteReq; 391 if (req->isLLSC()) { 392 cmd = MemCmd::StoreCondReq; 393 } else if (req->isSwap()) { 394 cmd = MemCmd::SwapReq; 395 } 396 } 397 pkt = new Packet(req, cmd, Packet::Broadcast); 398} 399 400void 401TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 402 RequestPtr req1, RequestPtr req2, RequestPtr req, 403 uint8_t *data, bool read) 404{ 405 pkt1 = pkt2 = NULL; 406 407 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 408 409 if (req->getFlags().isSet(Request::NO_ACCESS)) { 410 buildPacket(pkt1, req, read); 411 return; 412 } 413 414 buildPacket(pkt1, req1, read); 415 buildPacket(pkt2, req2, read); 416 417 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 418 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 419 Packet::Broadcast); 420 421 pkt->dataDynamicArray<uint8_t>(data); 422 pkt1->dataStatic<uint8_t>(data); 423 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 424 425 SplitMainSenderState * main_send_state = new SplitMainSenderState; 426 pkt->senderState = main_send_state; 427 main_send_state->fragments[0] = pkt1; 428 main_send_state->fragments[1] = pkt2; 429 main_send_state->outstanding = 2; 430 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 431 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 432} 433 434Fault 435TimingSimpleCPU::readBytes(Addr addr, uint8_t *data, 436 unsigned size, unsigned flags) 437{ 438 Fault fault; 439 const int asid = 0; 440 const ThreadID tid = 0; 441 const Addr pc = thread->instAddr(); 442 unsigned block_size = dcachePort.peerBlockSize(); 443 BaseTLB::Mode mode = BaseTLB::Read; 444 445 if (traceData) { 446 traceData->setAddr(addr); 447 } 448 449 RequestPtr req = new Request(asid, addr, size, 450 flags, pc, _cpuId, tid); 451 452 Addr split_addr = roundDown(addr + size - 1, block_size); 453 assert(split_addr <= addr || split_addr - addr < block_size); 454 455 _status = DTBWaitResponse; 456 if (split_addr > addr) { 457 RequestPtr req1, req2; 458 assert(!req->isLLSC() && !req->isSwap()); 459 req->splitOnVaddr(split_addr, req1, req2); 460 461 WholeTranslationState *state = 462 new WholeTranslationState(req, req1, req2, new uint8_t[size], 463 NULL, mode); 464 DataTranslation<TimingSimpleCPU> *trans1 = 465 new DataTranslation<TimingSimpleCPU>(this, state, 0); 466 DataTranslation<TimingSimpleCPU> *trans2 = 467 new DataTranslation<TimingSimpleCPU>(this, state, 1); 468 469 thread->dtb->translateTiming(req1, tc, trans1, mode); 470 thread->dtb->translateTiming(req2, tc, trans2, mode); 471 } else { 472 WholeTranslationState *state = 473 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 474 DataTranslation<TimingSimpleCPU> *translation 475 = new DataTranslation<TimingSimpleCPU>(this, state); 476 thread->dtb->translateTiming(req, tc, translation, mode); 477 } 478 479 return NoFault; 480} 481 482template <class T> 483Fault 484TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 485{ 486 return readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 487} 488 489#ifndef DOXYGEN_SHOULD_SKIP_THIS 490 491template 492Fault 493TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 494 495template 496Fault 497TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 498 499template 500Fault 501TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 502 503template 504Fault 505TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 506 507template 508Fault 509TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 510 511template 512Fault 513TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 514 515#endif //DOXYGEN_SHOULD_SKIP_THIS 516 517template<> 518Fault 519TimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 520{ 521 return read(addr, *(uint64_t*)&data, flags); 522} 523 524template<> 525Fault 526TimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 527{ 528 return read(addr, *(uint32_t*)&data, flags); 529} 530 531template<> 532Fault 533TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 534{ 535 return read(addr, (uint32_t&)data, flags); 536} 537 538bool 539TimingSimpleCPU::handleWritePacket() 540{ 541 RequestPtr req = dcache_pkt->req; 542 if (req->isMmappedIpr()) { 543 Tick delay; 544 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 545 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 546 _status = DcacheWaitResponse; 547 dcache_pkt = NULL; 548 } else if (!dcachePort.sendTiming(dcache_pkt)) { 549 _status = DcacheRetry; 550 } else { 551 _status = DcacheWaitResponse; 552 // memory system takes ownership of packet 553 dcache_pkt = NULL; 554 } 555 return dcache_pkt == NULL; 556} 557 558Fault 559TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size, 560 Addr addr, unsigned flags, uint64_t *res) 561{ 562 const int asid = 0; 563 const ThreadID tid = 0; 564 const Addr pc = thread->instAddr(); 565 unsigned block_size = dcachePort.peerBlockSize(); 566 BaseTLB::Mode mode = BaseTLB::Write; 567 568 if (traceData) { 569 traceData->setAddr(addr); 570 } 571 572 RequestPtr req = new Request(asid, addr, size, 573 flags, pc, _cpuId, tid); 574 575 Addr split_addr = roundDown(addr + size - 1, block_size); 576 assert(split_addr <= addr || split_addr - addr < block_size); 577 578 _status = DTBWaitResponse; 579 if (split_addr > addr) { 580 RequestPtr req1, req2; 581 assert(!req->isLLSC() && !req->isSwap()); 582 req->splitOnVaddr(split_addr, req1, req2); 583 584 WholeTranslationState *state = 585 new WholeTranslationState(req, req1, req2, data, res, mode); 586 DataTranslation<TimingSimpleCPU> *trans1 = 587 new DataTranslation<TimingSimpleCPU>(this, state, 0); 588 DataTranslation<TimingSimpleCPU> *trans2 = 589 new DataTranslation<TimingSimpleCPU>(this, state, 1); 590 591 thread->dtb->translateTiming(req1, tc, trans1, mode); 592 thread->dtb->translateTiming(req2, tc, trans2, mode); 593 } else { 594 WholeTranslationState *state = 595 new WholeTranslationState(req, data, res, mode); 596 DataTranslation<TimingSimpleCPU> *translation = 597 new DataTranslation<TimingSimpleCPU>(this, state); 598 thread->dtb->translateTiming(req, tc, translation, mode); 599 } 600 601 // Translation faults will be returned via finishTranslation() 602 return NoFault; 603} 604 605Fault 606TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size, 607 Addr addr, unsigned flags, uint64_t *res) 608{ 609 uint8_t *newData = new uint8_t[size]; 610 memcpy(newData, data, size); 611 return writeTheseBytes(newData, size, addr, flags, res); 612} 613 614template <class T> 615Fault 616TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 617{ 618 if (traceData) { 619 traceData->setData(data); 620 } 621 T *dataP = (T*) new uint8_t[sizeof(T)]; 622 *dataP = TheISA::htog(data); 623 624 return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res); 625} 626 627 628#ifndef DOXYGEN_SHOULD_SKIP_THIS 629template 630Fault 631TimingSimpleCPU::write(Twin32_t data, Addr addr, 632 unsigned flags, uint64_t *res); 633 634template 635Fault 636TimingSimpleCPU::write(Twin64_t data, Addr addr, 637 unsigned flags, uint64_t *res); 638 639template 640Fault 641TimingSimpleCPU::write(uint64_t data, Addr addr, 642 unsigned flags, uint64_t *res); 643 644template 645Fault 646TimingSimpleCPU::write(uint32_t data, Addr addr, 647 unsigned flags, uint64_t *res); 648 649template 650Fault 651TimingSimpleCPU::write(uint16_t data, Addr addr, 652 unsigned flags, uint64_t *res); 653 654template 655Fault 656TimingSimpleCPU::write(uint8_t data, Addr addr, 657 unsigned flags, uint64_t *res); 658 659#endif //DOXYGEN_SHOULD_SKIP_THIS 660 661template<> 662Fault 663TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 664{ 665 return write(*(uint64_t*)&data, addr, flags, res); 666} 667 668template<> 669Fault 670TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 671{ 672 return write(*(uint32_t*)&data, addr, flags, res); 673} 674 675 676template<> 677Fault 678TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 679{ 680 return write((uint32_t)data, addr, flags, res); 681} 682 683 684void 685TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 686{ 687 _status = Running; 688 689 if (state->getFault() != NoFault) { 690 if (state->isPrefetch()) { 691 state->setNoFault(); 692 } 693 delete [] state->data; 694 state->deleteReqs(); 695 translationFault(state->getFault()); 696 } else { 697 if (!state->isSplit) { 698 sendData(state->mainReq, state->data, state->res, 699 state->mode == BaseTLB::Read); 700 } else { 701 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 702 state->data, state->mode == BaseTLB::Read); 703 } 704 } 705 706 delete state; 707} 708 709 710void 711TimingSimpleCPU::fetch() 712{ 713 DPRINTF(SimpleCPU, "Fetch\n"); 714 715 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 716 checkForInterrupts(); 717 718 checkPcEventQueue(); 719 720 // We must have just got suspended by a PC event 721 if (_status == Idle) 722 return; 723 724 TheISA::PCState pcState = thread->pcState(); 725 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 726 727 if (needToFetch) { 728 _status = Running; 729 Request *ifetch_req = new Request(); 730 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 731 setupFetchRequest(ifetch_req); 732 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 733 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 734 BaseTLB::Execute); 735 } else { 736 _status = IcacheWaitResponse; 737 completeIfetch(NULL); 738 739 numCycles += tickToCycles(curTick() - previousTick); 740 previousTick = curTick(); 741 } 742} 743 744 745void 746TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 747{ 748 if (fault == NoFault) { 749 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 750 req->getVaddr(), req->getPaddr()); 751 ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 752 ifetch_pkt->dataStatic(&inst); 753 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 754 755 if (!icachePort.sendTiming(ifetch_pkt)) { 756 // Need to wait for retry 757 _status = IcacheRetry; 758 } else { 759 // Need to wait for cache to respond 760 _status = IcacheWaitResponse; 761 // ownership of packet transferred to memory system 762 ifetch_pkt = NULL; 763 } 764 } else { 765 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 766 delete req; 767 // fetch fault: advance directly to next instruction (fault handler) 768 _status = Running; 769 advanceInst(fault); 770 } 771 772 numCycles += tickToCycles(curTick() - previousTick); 773 previousTick = curTick(); 774} 775 776 777void 778TimingSimpleCPU::advanceInst(Fault fault) 779{ 780 781 if (_status == Faulting) 782 return; 783 784 if (fault != NoFault) { 785 advancePC(fault); 786 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 787 reschedule(fetchEvent, nextCycle(), true); 788 _status = Faulting; 789 return; 790 } 791 792 793 if (!stayAtPC) 794 advancePC(fault); 795 796 if (_status == Running) { 797 // kick off fetch of next instruction... callback from icache 798 // response will cause that instruction to be executed, 799 // keeping the CPU running. 800 fetch(); 801 } 802} 803 804 805void 806TimingSimpleCPU::completeIfetch(PacketPtr pkt) 807{ 808 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 809 pkt->getAddr() : 0); 810 811 // received a response from the icache: execute the received 812 // instruction 813 814 assert(!pkt || !pkt->isError()); 815 assert(_status == IcacheWaitResponse); 816 817 _status = Running; 818 819 numCycles += tickToCycles(curTick() - previousTick); 820 previousTick = curTick(); 821 822 if (getState() == SimObject::Draining) { 823 if (pkt) { 824 delete pkt->req; 825 delete pkt; 826 } 827 828 completeDrain(); 829 return; 830 } 831 832 preExecute(); 833 if (curStaticInst && curStaticInst->isMemRef()) { 834 // load or store: just send to dcache 835 Fault fault = curStaticInst->initiateAcc(this, traceData); 836 837 // If we're not running now the instruction will complete in a dcache 838 // response callback or the instruction faulted and has started an 839 // ifetch 840 if (_status == Running) { 841 if (fault != NoFault && traceData) { 842 // If there was a fault, we shouldn't trace this instruction. 843 delete traceData; 844 traceData = NULL; 845 } 846 847 postExecute(); 848 // @todo remove me after debugging with legion done 849 if (curStaticInst && (!curStaticInst->isMicroop() || 850 curStaticInst->isFirstMicroop())) 851 instCnt++; 852 advanceInst(fault); 853 } 854 } else if (curStaticInst) { 855 // non-memory instruction: execute completely now 856 Fault fault = curStaticInst->execute(this, traceData); 857 858 // keep an instruction count 859 if (fault == NoFault) 860 countInst(); 861 else if (traceData && !DTRACE(ExecFaulting)) { 862 delete traceData; 863 traceData = NULL; 864 } 865 866 postExecute(); 867 // @todo remove me after debugging with legion done 868 if (curStaticInst && (!curStaticInst->isMicroop() || 869 curStaticInst->isFirstMicroop())) 870 instCnt++; 871 advanceInst(fault); 872 } else { 873 advanceInst(NoFault); 874 } 875 876 if (pkt) { 877 delete pkt->req; 878 delete pkt; 879 } 880} 881 882void 883TimingSimpleCPU::IcachePort::ITickEvent::process() 884{ 885 cpu->completeIfetch(pkt); 886} 887 888bool 889TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 890{ 891 if (pkt->isResponse() && !pkt->wasNacked()) { 892 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 893 // delay processing of returned data until next CPU clock edge 894 Tick next_tick = cpu->nextCycle(curTick()); 895 896 if (next_tick == curTick()) 897 cpu->completeIfetch(pkt); 898 else 899 tickEvent.schedule(pkt, next_tick); 900 901 return true; 902 } else if (pkt->wasNacked()) { 903 assert(cpu->_status == IcacheWaitResponse); 904 pkt->reinitNacked(); 905 if (!sendTiming(pkt)) { 906 cpu->_status = IcacheRetry; 907 cpu->ifetch_pkt = pkt; 908 } 909 } 910 //Snooping a Coherence Request, do nothing 911 return true; 912} 913 914void 915TimingSimpleCPU::IcachePort::recvRetry() 916{ 917 // we shouldn't get a retry unless we have a packet that we're 918 // waiting to transmit 919 assert(cpu->ifetch_pkt != NULL); 920 assert(cpu->_status == IcacheRetry); 921 PacketPtr tmp = cpu->ifetch_pkt; 922 if (sendTiming(tmp)) { 923 cpu->_status = IcacheWaitResponse; 924 cpu->ifetch_pkt = NULL; 925 } 926} 927 928void 929TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 930{ 931 // received a response from the dcache: complete the load or store 932 // instruction 933 assert(!pkt->isError()); 934 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 935 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 936 937 numCycles += tickToCycles(curTick() - previousTick); 938 previousTick = curTick(); 939 940 if (pkt->senderState) { 941 SplitFragmentSenderState * send_state = 942 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 943 assert(send_state); 944 delete pkt->req; 945 delete pkt; 946 PacketPtr big_pkt = send_state->bigPkt; 947 delete send_state; 948 949 SplitMainSenderState * main_send_state = 950 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 951 assert(main_send_state); 952 // Record the fact that this packet is no longer outstanding. 953 assert(main_send_state->outstanding != 0); 954 main_send_state->outstanding--; 955 956 if (main_send_state->outstanding) { 957 return; 958 } else { 959 delete main_send_state; 960 big_pkt->senderState = NULL; 961 pkt = big_pkt; 962 } 963 } 964 965 _status = Running; 966 967 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 968 969 // keep an instruction count 970 if (fault == NoFault) 971 countInst(); 972 else if (traceData) { 973 // If there was a fault, we shouldn't trace this instruction. 974 delete traceData; 975 traceData = NULL; 976 } 977 978 // the locked flag may be cleared on the response packet, so check 979 // pkt->req and not pkt to see if it was a load-locked 980 if (pkt->isRead() && pkt->req->isLLSC()) { 981 TheISA::handleLockedRead(thread, pkt->req); 982 } 983 984 delete pkt->req; 985 delete pkt; 986 987 postExecute(); 988 989 if (getState() == SimObject::Draining) { 990 advancePC(fault); 991 completeDrain(); 992 993 return; 994 } 995 996 advanceInst(fault); 997} 998 999 1000void 1001TimingSimpleCPU::completeDrain() 1002{ 1003 DPRINTF(Config, "Done draining\n"); 1004 changeState(SimObject::Drained); 1005 drainEvent->process(); 1006} 1007 1008void 1009TimingSimpleCPU::DcachePort::setPeer(Port *port) 1010{ 1011 Port::setPeer(port); 1012 1013#if FULL_SYSTEM 1014 // Update the ThreadContext's memory ports (Functional/Virtual 1015 // Ports) 1016 cpu->tcBase()->connectMemPorts(cpu->tcBase()); 1017#endif 1018} 1019 1020bool 1021TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 1022{ 1023 if (pkt->isResponse() && !pkt->wasNacked()) { 1024 // delay processing of returned data until next CPU clock edge 1025 Tick next_tick = cpu->nextCycle(curTick()); 1026 1027 if (next_tick == curTick()) { 1028 cpu->completeDataAccess(pkt); 1029 } else { 1030 if (!tickEvent.scheduled()) { 1031 tickEvent.schedule(pkt, next_tick); 1032 } else { 1033 // In the case of a split transaction and a cache that is 1034 // faster than a CPU we could get two responses before 1035 // next_tick expires 1036 if (!retryEvent.scheduled()) 1037 schedule(retryEvent, next_tick); 1038 return false; 1039 } 1040 } 1041 1042 return true; 1043 } 1044 else if (pkt->wasNacked()) { 1045 assert(cpu->_status == DcacheWaitResponse); 1046 pkt->reinitNacked(); 1047 if (!sendTiming(pkt)) { 1048 cpu->_status = DcacheRetry; 1049 cpu->dcache_pkt = pkt; 1050 } 1051 } 1052 //Snooping a Coherence Request, do nothing 1053 return true; 1054} 1055 1056void 1057TimingSimpleCPU::DcachePort::DTickEvent::process() 1058{ 1059 cpu->completeDataAccess(pkt); 1060} 1061 1062void 1063TimingSimpleCPU::DcachePort::recvRetry() 1064{ 1065 // we shouldn't get a retry unless we have a packet that we're 1066 // waiting to transmit 1067 assert(cpu->dcache_pkt != NULL); 1068 assert(cpu->_status == DcacheRetry); 1069 PacketPtr tmp = cpu->dcache_pkt; 1070 if (tmp->senderState) { 1071 // This is a packet from a split access. 1072 SplitFragmentSenderState * send_state = 1073 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 1074 assert(send_state); 1075 PacketPtr big_pkt = send_state->bigPkt; 1076 1077 SplitMainSenderState * main_send_state = 1078 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 1079 assert(main_send_state); 1080 1081 if (sendTiming(tmp)) { 1082 // If we were able to send without retrying, record that fact 1083 // and try sending the other fragment. 1084 send_state->clearFromParent(); 1085 int other_index = main_send_state->getPendingFragment(); 1086 if (other_index > 0) { 1087 tmp = main_send_state->fragments[other_index]; 1088 cpu->dcache_pkt = tmp; 1089 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 1090 (big_pkt->isWrite() && cpu->handleWritePacket())) { 1091 main_send_state->fragments[other_index] = NULL; 1092 } 1093 } else { 1094 cpu->_status = DcacheWaitResponse; 1095 // memory system takes ownership of packet 1096 cpu->dcache_pkt = NULL; 1097 } 1098 } 1099 } else if (sendTiming(tmp)) { 1100 cpu->_status = DcacheWaitResponse; 1101 // memory system takes ownership of packet 1102 cpu->dcache_pkt = NULL; 1103 } 1104} 1105 1106TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 1107 Tick t) 1108 : pkt(_pkt), cpu(_cpu) 1109{ 1110 cpu->schedule(this, t); 1111} 1112 1113void 1114TimingSimpleCPU::IprEvent::process() 1115{ 1116 cpu->completeDataAccess(pkt); 1117} 1118 1119const char * 1120TimingSimpleCPU::IprEvent::description() const 1121{ 1122 return "Timing Simple CPU Delay IPR event"; 1123} 1124 1125 1126void 1127TimingSimpleCPU::printAddr(Addr a) 1128{ 1129 dcachePort.printAddr(a); 1130} 1131 1132 1133//////////////////////////////////////////////////////////////////////// 1134// 1135// TimingSimpleCPU Simulation Object 1136// 1137TimingSimpleCPU * 1138TimingSimpleCPUParams::create() 1139{ 1140 numThreads = 1; 1141#if !FULL_SYSTEM 1142 if (workload.size() != 1) 1143 panic("only one workload allowed"); 1144#endif 1145 return new TimingSimpleCPU(this); 1146} 1147