timing.cc revision 3686:fa8d8b90cd8a
19913Ssteve.reinhardt@amd.com/* 29913Ssteve.reinhardt@amd.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 39913Ssteve.reinhardt@amd.com * All rights reserved. 49913Ssteve.reinhardt@amd.com * 59913Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 69913Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 79913Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 89913Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 99913Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 109913Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 119913Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 129913Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 139913Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 149913Ssteve.reinhardt@amd.com * this software without specific prior written permission. 159913Ssteve.reinhardt@amd.com * 169913Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179913Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189913Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199913Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209913Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219913Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229913Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239913Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249913Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259913Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269913Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279913Ssteve.reinhardt@amd.com * 289913Ssteve.reinhardt@amd.com * Authors: Steve Reinhardt 299913Ssteve.reinhardt@amd.com */ 309913Ssteve.reinhardt@amd.com 319913Ssteve.reinhardt@amd.com#include "arch/locked_mem.hh" 329913Ssteve.reinhardt@amd.com#include "arch/utility.hh" 339913Ssteve.reinhardt@amd.com#include "cpu/exetrace.hh" 349913Ssteve.reinhardt@amd.com#include "cpu/simple/timing.hh" 359913Ssteve.reinhardt@amd.com#include "mem/packet.hh" 369920Syasuko.eckert@amd.com#include "mem/packet_access.hh" 379913Ssteve.reinhardt@amd.com#include "sim/builder.hh" 389913Ssteve.reinhardt@amd.com#include "sim/system.hh" 39 40using namespace std; 41using namespace TheISA; 42 43Port * 44TimingSimpleCPU::getPort(const std::string &if_name, int idx) 45{ 46 if (if_name == "dcache_port") 47 return &dcachePort; 48 else if (if_name == "icache_port") 49 return &icachePort; 50 else 51 panic("No Such Port\n"); 52} 53 54void 55TimingSimpleCPU::init() 56{ 57 BaseCPU::init(); 58#if FULL_SYSTEM 59 for (int i = 0; i < threadContexts.size(); ++i) { 60 ThreadContext *tc = threadContexts[i]; 61 62 // initialize CPU, including PC 63 TheISA::initCPU(tc, tc->readCpuId()); 64 } 65#endif 66} 67 68Tick 69TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 70{ 71 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 72 return curTick; 73} 74 75void 76TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 77{ 78 //No internal storage to update, jusst return 79 return; 80} 81 82void 83TimingSimpleCPU::CpuPort::recvStatusChange(Status status) 84{ 85 if (status == RangeChange) { 86 if (!snoopRangeSent) { 87 snoopRangeSent = true; 88 sendStatusChange(Port::RangeChange); 89 } 90 return; 91 } 92 93 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 94} 95 96 97void 98TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 99{ 100 pkt = _pkt; 101 Event::schedule(t); 102} 103 104TimingSimpleCPU::TimingSimpleCPU(Params *p) 105 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 106 cpu_id(p->cpu_id) 107{ 108 _status = Idle; 109 110 icachePort.snoopRangeSent = false; 111 dcachePort.snoopRangeSent = false; 112 113 ifetch_pkt = dcache_pkt = NULL; 114 drainEvent = NULL; 115 fetchEvent = NULL; 116 previousTick = 0; 117 changeState(SimObject::Running); 118} 119 120 121TimingSimpleCPU::~TimingSimpleCPU() 122{ 123} 124 125void 126TimingSimpleCPU::serialize(ostream &os) 127{ 128 SimObject::State so_state = SimObject::getState(); 129 SERIALIZE_ENUM(so_state); 130 BaseSimpleCPU::serialize(os); 131} 132 133void 134TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 135{ 136 SimObject::State so_state; 137 UNSERIALIZE_ENUM(so_state); 138 BaseSimpleCPU::unserialize(cp, section); 139} 140 141unsigned int 142TimingSimpleCPU::drain(Event *drain_event) 143{ 144 // TimingSimpleCPU is ready to drain if it's not waiting for 145 // an access to complete. 146 if (status() == Idle || status() == Running || status() == SwitchedOut) { 147 changeState(SimObject::Drained); 148 return 0; 149 } else { 150 changeState(SimObject::Draining); 151 drainEvent = drain_event; 152 return 1; 153 } 154} 155 156void 157TimingSimpleCPU::resume() 158{ 159 if (_status != SwitchedOut && _status != Idle) { 160 assert(system->getMemoryMode() == System::Timing); 161 162 // Delete the old event if it existed. 163 if (fetchEvent) { 164 if (fetchEvent->scheduled()) 165 fetchEvent->deschedule(); 166 167 delete fetchEvent; 168 } 169 170 fetchEvent = 171 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 172 fetchEvent->schedule(nextCycle()); 173 } 174 175 changeState(SimObject::Running); 176 previousTick = curTick; 177} 178 179void 180TimingSimpleCPU::switchOut() 181{ 182 assert(status() == Running || status() == Idle); 183 _status = SwitchedOut; 184 numCycles += curTick - previousTick; 185 186 // If we've been scheduled to resume but are then told to switch out, 187 // we'll need to cancel it. 188 if (fetchEvent && fetchEvent->scheduled()) 189 fetchEvent->deschedule(); 190} 191 192 193void 194TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 195{ 196 BaseCPU::takeOverFrom(oldCPU); 197 198 // if any of this CPU's ThreadContexts are active, mark the CPU as 199 // running and schedule its tick event. 200 for (int i = 0; i < threadContexts.size(); ++i) { 201 ThreadContext *tc = threadContexts[i]; 202 if (tc->status() == ThreadContext::Active && _status != Running) { 203 _status = Running; 204 break; 205 } 206 } 207 208 if (_status != Running) { 209 _status = Idle; 210 } 211 212 Port *peer; 213 if (icachePort.getPeer() == NULL) { 214 peer = oldCPU->getPort("icache_port")->getPeer(); 215 icachePort.setPeer(peer); 216 } else { 217 peer = icachePort.getPeer(); 218 } 219 peer->setPeer(&icachePort); 220 221 if (dcachePort.getPeer() == NULL) { 222 peer = oldCPU->getPort("dcache_port")->getPeer(); 223 dcachePort.setPeer(peer); 224 } else { 225 peer = dcachePort.getPeer(); 226 } 227 peer->setPeer(&dcachePort); 228} 229 230 231void 232TimingSimpleCPU::activateContext(int thread_num, int delay) 233{ 234 assert(thread_num == 0); 235 assert(thread); 236 237 assert(_status == Idle); 238 239 notIdleFraction++; 240 _status = Running; 241 242#if FULL_SYSTEM 243 // Connect the ThreadContext's memory ports (Functional/Virtual 244 // Ports) 245 tc->connectMemPorts(); 246#endif 247 248 // kick things off by initiating the fetch of the next instruction 249 fetchEvent = 250 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 251 fetchEvent->schedule(nextCycle(curTick + cycles(delay))); 252} 253 254 255void 256TimingSimpleCPU::suspendContext(int thread_num) 257{ 258 assert(thread_num == 0); 259 assert(thread); 260 261 assert(_status == Running); 262 263 // just change status to Idle... if status != Running, 264 // completeInst() will not initiate fetch of next instruction. 265 266 notIdleFraction--; 267 _status = Idle; 268} 269 270 271template <class T> 272Fault 273TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 274{ 275 Request *req = 276 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 277 cpu_id, /* thread ID */ 0); 278 279 if (traceData) { 280 traceData->setAddr(req->getVaddr()); 281 } 282 283 // translate to physical address 284 Fault fault = thread->translateDataReadReq(req); 285 286 // Now do the access. 287 if (fault == NoFault) { 288 PacketPtr pkt = 289 new Packet(req, Packet::ReadReq, Packet::Broadcast); 290 pkt->dataDynamic<T>(new T); 291 292 if (!dcachePort.sendTiming(pkt)) { 293 _status = DcacheRetry; 294 dcache_pkt = pkt; 295 } else { 296 _status = DcacheWaitResponse; 297 // memory system takes ownership of packet 298 dcache_pkt = NULL; 299 } 300 } else { 301 delete req; 302 } 303 304 // This will need a new way to tell if it has a dcache attached. 305 if (req->isUncacheable()) 306 recordEvent("Uncached Read"); 307 308 return fault; 309} 310 311#ifndef DOXYGEN_SHOULD_SKIP_THIS 312 313template 314Fault 315TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 316 317template 318Fault 319TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 320 321template 322Fault 323TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 324 325template 326Fault 327TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 328 329#endif //DOXYGEN_SHOULD_SKIP_THIS 330 331template<> 332Fault 333TimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 334{ 335 return read(addr, *(uint64_t*)&data, flags); 336} 337 338template<> 339Fault 340TimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 341{ 342 return read(addr, *(uint32_t*)&data, flags); 343} 344 345 346template<> 347Fault 348TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 349{ 350 return read(addr, (uint32_t&)data, flags); 351} 352 353 354template <class T> 355Fault 356TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 357{ 358 Request *req = 359 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 360 cpu_id, /* thread ID */ 0); 361 362 // translate to physical address 363 Fault fault = thread->translateDataWriteReq(req); 364 365 // Now do the access. 366 if (fault == NoFault) { 367 assert(dcache_pkt == NULL); 368 dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 369 dcache_pkt->allocate(); 370 dcache_pkt->set(data); 371 372 bool do_access = true; // flag to suppress cache access 373 374 if (req->isLocked()) { 375 do_access = TheISA::handleLockedWrite(thread, req); 376 } 377 378 if (do_access) { 379 if (!dcachePort.sendTiming(dcache_pkt)) { 380 _status = DcacheRetry; 381 } else { 382 _status = DcacheWaitResponse; 383 // memory system takes ownership of packet 384 dcache_pkt = NULL; 385 } 386 } 387 } else { 388 delete req; 389 } 390 391 // This will need a new way to tell if it's hooked up to a cache or not. 392 if (req->isUncacheable()) 393 recordEvent("Uncached Write"); 394 395 // If the write needs to have a fault on the access, consider calling 396 // changeStatus() and changing it to "bad addr write" or something. 397 return fault; 398} 399 400 401#ifndef DOXYGEN_SHOULD_SKIP_THIS 402template 403Fault 404TimingSimpleCPU::write(uint64_t data, Addr addr, 405 unsigned flags, uint64_t *res); 406 407template 408Fault 409TimingSimpleCPU::write(uint32_t data, Addr addr, 410 unsigned flags, uint64_t *res); 411 412template 413Fault 414TimingSimpleCPU::write(uint16_t data, Addr addr, 415 unsigned flags, uint64_t *res); 416 417template 418Fault 419TimingSimpleCPU::write(uint8_t data, Addr addr, 420 unsigned flags, uint64_t *res); 421 422#endif //DOXYGEN_SHOULD_SKIP_THIS 423 424template<> 425Fault 426TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 427{ 428 return write(*(uint64_t*)&data, addr, flags, res); 429} 430 431template<> 432Fault 433TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 434{ 435 return write(*(uint32_t*)&data, addr, flags, res); 436} 437 438 439template<> 440Fault 441TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 442{ 443 return write((uint32_t)data, addr, flags, res); 444} 445 446 447void 448TimingSimpleCPU::fetch() 449{ 450 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 451 checkForInterrupts(); 452 453 Request *ifetch_req = new Request(); 454 ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 455 Fault fault = setupFetchRequest(ifetch_req); 456 457 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 458 ifetch_pkt->dataStatic(&inst); 459 460 if (fault == NoFault) { 461 if (!icachePort.sendTiming(ifetch_pkt)) { 462 // Need to wait for retry 463 _status = IcacheRetry; 464 } else { 465 // Need to wait for cache to respond 466 _status = IcacheWaitResponse; 467 // ownership of packet transferred to memory system 468 ifetch_pkt = NULL; 469 } 470 } else { 471 delete ifetch_req; 472 delete ifetch_pkt; 473 // fetch fault: advance directly to next instruction (fault handler) 474 advanceInst(fault); 475 } 476 477 numCycles += curTick - previousTick; 478 previousTick = curTick; 479} 480 481 482void 483TimingSimpleCPU::advanceInst(Fault fault) 484{ 485 advancePC(fault); 486 487 if (_status == Running) { 488 // kick off fetch of next instruction... callback from icache 489 // response will cause that instruction to be executed, 490 // keeping the CPU running. 491 fetch(); 492 } 493} 494 495 496void 497TimingSimpleCPU::completeIfetch(PacketPtr pkt) 498{ 499 // received a response from the icache: execute the received 500 // instruction 501 assert(pkt->result == Packet::Success); 502 assert(_status == IcacheWaitResponse); 503 504 _status = Running; 505 506 numCycles += curTick - previousTick; 507 previousTick = curTick; 508 509 if (getState() == SimObject::Draining) { 510 delete pkt->req; 511 delete pkt; 512 513 completeDrain(); 514 return; 515 } 516 517 preExecute(); 518 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 519 // load or store: just send to dcache 520 Fault fault = curStaticInst->initiateAcc(this, traceData); 521 if (_status != Running) { 522 // instruction will complete in dcache response callback 523 assert(_status == DcacheWaitResponse || _status == DcacheRetry); 524 assert(fault == NoFault); 525 } else { 526 if (fault == NoFault) { 527 // early fail on store conditional: complete now 528 assert(dcache_pkt != NULL); 529 fault = curStaticInst->completeAcc(dcache_pkt, this, 530 traceData); 531 delete dcache_pkt->req; 532 delete dcache_pkt; 533 dcache_pkt = NULL; 534 } 535 postExecute(); 536 advanceInst(fault); 537 } 538 } else { 539 // non-memory instruction: execute completely now 540 Fault fault = curStaticInst->execute(this, traceData); 541 postExecute(); 542 advanceInst(fault); 543 } 544 545 delete pkt->req; 546 delete pkt; 547} 548 549void 550TimingSimpleCPU::IcachePort::ITickEvent::process() 551{ 552 cpu->completeIfetch(pkt); 553} 554 555bool 556TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 557{ 558 if (pkt->isResponse()) { 559 // delay processing of returned data until next CPU clock edge 560 Tick mem_time = pkt->req->getTime(); 561 Tick next_tick = cpu->nextCycle(mem_time); 562 563 if (next_tick == curTick) 564 cpu->completeIfetch(pkt); 565 else 566 tickEvent.schedule(pkt, next_tick); 567 568 return true; 569 } 570 else { 571 //Snooping a Coherence Request, do nothing 572 return true; 573 } 574} 575 576void 577TimingSimpleCPU::IcachePort::recvRetry() 578{ 579 // we shouldn't get a retry unless we have a packet that we're 580 // waiting to transmit 581 assert(cpu->ifetch_pkt != NULL); 582 assert(cpu->_status == IcacheRetry); 583 PacketPtr tmp = cpu->ifetch_pkt; 584 if (sendTiming(tmp)) { 585 cpu->_status = IcacheWaitResponse; 586 cpu->ifetch_pkt = NULL; 587 } 588} 589 590void 591TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 592{ 593 // received a response from the dcache: complete the load or store 594 // instruction 595 assert(pkt->result == Packet::Success); 596 assert(_status == DcacheWaitResponse); 597 _status = Running; 598 599 numCycles += curTick - previousTick; 600 previousTick = curTick; 601 602 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 603 604 if (pkt->isRead() && pkt->req->isLocked()) { 605 TheISA::handleLockedRead(thread, pkt->req); 606 } 607 608 delete pkt->req; 609 delete pkt; 610 611 postExecute(); 612 613 if (getState() == SimObject::Draining) { 614 advancePC(fault); 615 completeDrain(); 616 617 return; 618 } 619 620 advanceInst(fault); 621} 622 623 624void 625TimingSimpleCPU::completeDrain() 626{ 627 DPRINTF(Config, "Done draining\n"); 628 changeState(SimObject::Drained); 629 drainEvent->process(); 630} 631 632bool 633TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 634{ 635 if (pkt->isResponse()) { 636 // delay processing of returned data until next CPU clock edge 637 Tick mem_time = pkt->req->getTime(); 638 Tick next_tick = cpu->nextCycle(mem_time); 639 640 if (next_tick == curTick) 641 cpu->completeDataAccess(pkt); 642 else 643 tickEvent.schedule(pkt, next_tick); 644 645 return true; 646 } 647 else { 648 //Snooping a coherence req, do nothing 649 return true; 650 } 651} 652 653void 654TimingSimpleCPU::DcachePort::DTickEvent::process() 655{ 656 cpu->completeDataAccess(pkt); 657} 658 659void 660TimingSimpleCPU::DcachePort::recvRetry() 661{ 662 // we shouldn't get a retry unless we have a packet that we're 663 // waiting to transmit 664 assert(cpu->dcache_pkt != NULL); 665 assert(cpu->_status == DcacheRetry); 666 PacketPtr tmp = cpu->dcache_pkt; 667 if (sendTiming(tmp)) { 668 cpu->_status = DcacheWaitResponse; 669 // memory system takes ownership of packet 670 cpu->dcache_pkt = NULL; 671 } 672} 673 674 675//////////////////////////////////////////////////////////////////////// 676// 677// TimingSimpleCPU Simulation Object 678// 679BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 680 681 Param<Counter> max_insts_any_thread; 682 Param<Counter> max_insts_all_threads; 683 Param<Counter> max_loads_any_thread; 684 Param<Counter> max_loads_all_threads; 685 Param<Tick> progress_interval; 686 SimObjectParam<System *> system; 687 Param<int> cpu_id; 688 689#if FULL_SYSTEM 690 SimObjectParam<TheISA::ITB *> itb; 691 SimObjectParam<TheISA::DTB *> dtb; 692 Param<Tick> profile; 693 694 Param<bool> do_quiesce; 695 Param<bool> do_checkpoint_insts; 696 Param<bool> do_statistics_insts; 697#else 698 SimObjectParam<Process *> workload; 699#endif // FULL_SYSTEM 700 701 Param<int> clock; 702 Param<int> phase; 703 704 Param<bool> defer_registration; 705 Param<int> width; 706 Param<bool> function_trace; 707 Param<Tick> function_trace_start; 708 Param<bool> simulate_stalls; 709 710END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 711 712BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 713 714 INIT_PARAM(max_insts_any_thread, 715 "terminate when any thread reaches this inst count"), 716 INIT_PARAM(max_insts_all_threads, 717 "terminate when all threads have reached this inst count"), 718 INIT_PARAM(max_loads_any_thread, 719 "terminate when any thread reaches this load count"), 720 INIT_PARAM(max_loads_all_threads, 721 "terminate when all threads have reached this load count"), 722 INIT_PARAM(progress_interval, "Progress interval"), 723 INIT_PARAM(system, "system object"), 724 INIT_PARAM(cpu_id, "processor ID"), 725 726#if FULL_SYSTEM 727 INIT_PARAM(itb, "Instruction TLB"), 728 INIT_PARAM(dtb, "Data TLB"), 729 INIT_PARAM(profile, ""), 730 INIT_PARAM(do_quiesce, ""), 731 INIT_PARAM(do_checkpoint_insts, ""), 732 INIT_PARAM(do_statistics_insts, ""), 733#else 734 INIT_PARAM(workload, "processes to run"), 735#endif // FULL_SYSTEM 736 737 INIT_PARAM(clock, "clock speed"), 738 INIT_PARAM_DFLT(phase, "clock phase", 0), 739 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 740 INIT_PARAM(width, "cpu width"), 741 INIT_PARAM(function_trace, "Enable function trace"), 742 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 743 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 744 745END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 746 747 748CREATE_SIM_OBJECT(TimingSimpleCPU) 749{ 750 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 751 params->name = getInstanceName(); 752 params->numberOfThreads = 1; 753 params->max_insts_any_thread = max_insts_any_thread; 754 params->max_insts_all_threads = max_insts_all_threads; 755 params->max_loads_any_thread = max_loads_any_thread; 756 params->max_loads_all_threads = max_loads_all_threads; 757 params->progress_interval = progress_interval; 758 params->deferRegistration = defer_registration; 759 params->clock = clock; 760 params->phase = phase; 761 params->functionTrace = function_trace; 762 params->functionTraceStart = function_trace_start; 763 params->system = system; 764 params->cpu_id = cpu_id; 765 766#if FULL_SYSTEM 767 params->itb = itb; 768 params->dtb = dtb; 769 params->profile = profile; 770 params->do_quiesce = do_quiesce; 771 params->do_checkpoint_insts = do_checkpoint_insts; 772 params->do_statistics_insts = do_statistics_insts; 773#else 774 params->process = workload; 775#endif 776 777 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 778 return cpu; 779} 780 781REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 782 783