timing.cc revision 2869:4dbf4770df29
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/utility.hh" 32#include "cpu/exetrace.hh" 33#include "cpu/simple/timing.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" 36 37using namespace std; 38using namespace TheISA; 39 40Port * 41TimingSimpleCPU::getPort(const std::string &if_name, int idx) 42{ 43 if (if_name == "dcache_port") 44 return &dcachePort; 45 else if (if_name == "icache_port") 46 return &icachePort; 47 else 48 panic("No Such Port\n"); 49} 50 51void 52TimingSimpleCPU::init() 53{ 54 BaseCPU::init(); 55#if FULL_SYSTEM 56 for (int i = 0; i < threadContexts.size(); ++i) { 57 ThreadContext *tc = threadContexts[i]; 58 59 // initialize CPU, including PC 60 TheISA::initCPU(tc, tc->readCpuId()); 61 } 62#endif 63} 64 65Tick 66TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 67{ 68 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 69 return curTick; 70} 71 72void 73TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 74{ 75 panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 76} 77 78void 79TimingSimpleCPU::CpuPort::recvStatusChange(Status status) 80{ 81 if (status == RangeChange) 82 return; 83 84 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 85} 86 87TimingSimpleCPU::TimingSimpleCPU(Params *p) 88 : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 89{ 90 _status = Idle; 91 ifetch_pkt = dcache_pkt = NULL; 92 drainEvent = NULL; 93 fetchEvent = NULL; 94 state = SimObject::Timing; 95} 96 97 98TimingSimpleCPU::~TimingSimpleCPU() 99{ 100} 101 102void 103TimingSimpleCPU::serialize(ostream &os) 104{ 105 SERIALIZE_ENUM(_status); 106 BaseSimpleCPU::serialize(os); 107} 108 109void 110TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 111{ 112 UNSERIALIZE_ENUM(_status); 113 BaseSimpleCPU::unserialize(cp, section); 114} 115 116bool 117TimingSimpleCPU::drain(Event *drain_event) 118{ 119 // TimingSimpleCPU is ready to drain if it's not waiting for 120 // an access to complete. 121 if (status() == Idle || status() == Running || status() == SwitchedOut) { 122 changeState(SimObject::DrainedTiming); 123 return true; 124 } else { 125 changeState(SimObject::Draining); 126 drainEvent = drain_event; 127 return false; 128 } 129} 130 131void 132TimingSimpleCPU::resume() 133{ 134 if (_status != SwitchedOut && _status != Idle) { 135 // Delete the old event if it existed. 136 if (fetchEvent) { 137 assert(!fetchEvent->scheduled()); 138 delete fetchEvent; 139 } 140 141 fetchEvent = 142 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 143 fetchEvent->schedule(curTick); 144 } 145} 146 147void 148TimingSimpleCPU::setMemoryMode(State new_mode) 149{ 150 assert(new_mode == SimObject::Timing); 151} 152 153void 154TimingSimpleCPU::switchOut() 155{ 156 assert(status() == Running || status() == Idle); 157 _status = SwitchedOut; 158 159 // If we've been scheduled to resume but are then told to switch out, 160 // we'll need to cancel it. 161 if (fetchEvent && fetchEvent->scheduled()) 162 fetchEvent->deschedule(); 163} 164 165 166void 167TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 168{ 169 BaseCPU::takeOverFrom(oldCPU); 170 171 // if any of this CPU's ThreadContexts are active, mark the CPU as 172 // running and schedule its tick event. 173 for (int i = 0; i < threadContexts.size(); ++i) { 174 ThreadContext *tc = threadContexts[i]; 175 if (tc->status() == ThreadContext::Active && _status != Running) { 176 _status = Running; 177 break; 178 } 179 } 180} 181 182 183void 184TimingSimpleCPU::activateContext(int thread_num, int delay) 185{ 186 assert(thread_num == 0); 187 assert(thread); 188 189 assert(_status == Idle); 190 191 notIdleFraction++; 192 _status = Running; 193 // kick things off by initiating the fetch of the next instruction 194 fetchEvent = 195 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 196 fetchEvent->schedule(curTick + cycles(delay)); 197} 198 199 200void 201TimingSimpleCPU::suspendContext(int thread_num) 202{ 203 assert(thread_num == 0); 204 assert(thread); 205 206 assert(_status == Running); 207 208 // just change status to Idle... if status != Running, 209 // completeInst() will not initiate fetch of next instruction. 210 211 notIdleFraction--; 212 _status = Idle; 213} 214 215 216template <class T> 217Fault 218TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 219{ 220 // need to fill in CPU & thread IDs here 221 Request *data_read_req = new Request(); 222 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 223 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 224 225 if (traceData) { 226 traceData->setAddr(data_read_req->getVaddr()); 227 } 228 229 // translate to physical address 230 Fault fault = thread->translateDataReadReq(data_read_req); 231 232 // Now do the access. 233 if (fault == NoFault) { 234 Packet *data_read_pkt = 235 new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast); 236 data_read_pkt->dataDynamic<T>(new T); 237 238 if (!dcachePort.sendTiming(data_read_pkt)) { 239 _status = DcacheRetry; 240 dcache_pkt = data_read_pkt; 241 } else { 242 _status = DcacheWaitResponse; 243 dcache_pkt = NULL; 244 } 245 } 246 247 // This will need a new way to tell if it has a dcache attached. 248 if (data_read_req->getFlags() & UNCACHEABLE) 249 recordEvent("Uncached Read"); 250 251 return fault; 252} 253 254#ifndef DOXYGEN_SHOULD_SKIP_THIS 255 256template 257Fault 258TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 259 260template 261Fault 262TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 263 264template 265Fault 266TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 267 268template 269Fault 270TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 271 272#endif //DOXYGEN_SHOULD_SKIP_THIS 273 274template<> 275Fault 276TimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 277{ 278 return read(addr, *(uint64_t*)&data, flags); 279} 280 281template<> 282Fault 283TimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 284{ 285 return read(addr, *(uint32_t*)&data, flags); 286} 287 288 289template<> 290Fault 291TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 292{ 293 return read(addr, (uint32_t&)data, flags); 294} 295 296 297template <class T> 298Fault 299TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 300{ 301 // need to fill in CPU & thread IDs here 302 Request *data_write_req = new Request(); 303 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 304 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 305 306 // translate to physical address 307 Fault fault = thread->translateDataWriteReq(data_write_req); 308 // Now do the access. 309 if (fault == NoFault) { 310 Packet *data_write_pkt = 311 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast); 312 data_write_pkt->allocate(); 313 data_write_pkt->set(data); 314 315 if (!dcachePort.sendTiming(data_write_pkt)) { 316 _status = DcacheRetry; 317 dcache_pkt = data_write_pkt; 318 } else { 319 _status = DcacheWaitResponse; 320 dcache_pkt = NULL; 321 } 322 } 323 324 // This will need a new way to tell if it's hooked up to a cache or not. 325 if (data_write_req->getFlags() & UNCACHEABLE) 326 recordEvent("Uncached Write"); 327 328 // If the write needs to have a fault on the access, consider calling 329 // changeStatus() and changing it to "bad addr write" or something. 330 return fault; 331} 332 333 334#ifndef DOXYGEN_SHOULD_SKIP_THIS 335template 336Fault 337TimingSimpleCPU::write(uint64_t data, Addr addr, 338 unsigned flags, uint64_t *res); 339 340template 341Fault 342TimingSimpleCPU::write(uint32_t data, Addr addr, 343 unsigned flags, uint64_t *res); 344 345template 346Fault 347TimingSimpleCPU::write(uint16_t data, Addr addr, 348 unsigned flags, uint64_t *res); 349 350template 351Fault 352TimingSimpleCPU::write(uint8_t data, Addr addr, 353 unsigned flags, uint64_t *res); 354 355#endif //DOXYGEN_SHOULD_SKIP_THIS 356 357template<> 358Fault 359TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 360{ 361 return write(*(uint64_t*)&data, addr, flags, res); 362} 363 364template<> 365Fault 366TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 367{ 368 return write(*(uint32_t*)&data, addr, flags, res); 369} 370 371 372template<> 373Fault 374TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 375{ 376 return write((uint32_t)data, addr, flags, res); 377} 378 379 380void 381TimingSimpleCPU::fetch() 382{ 383 checkForInterrupts(); 384 385 // need to fill in CPU & thread IDs here 386 Request *ifetch_req = new Request(); 387 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 388 Fault fault = setupFetchRequest(ifetch_req); 389 390 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 391 ifetch_pkt->dataStatic(&inst); 392 393 if (fault == NoFault) { 394 if (!icachePort.sendTiming(ifetch_pkt)) { 395 // Need to wait for retry 396 _status = IcacheRetry; 397 } else { 398 // Need to wait for cache to respond 399 _status = IcacheWaitResponse; 400 // ownership of packet transferred to memory system 401 ifetch_pkt = NULL; 402 } 403 } else { 404 // fetch fault: advance directly to next instruction (fault handler) 405 advanceInst(fault); 406 } 407} 408 409 410void 411TimingSimpleCPU::advanceInst(Fault fault) 412{ 413 advancePC(fault); 414 415 if (_status == Running) { 416 // kick off fetch of next instruction... callback from icache 417 // response will cause that instruction to be executed, 418 // keeping the CPU running. 419 fetch(); 420 } 421} 422 423 424void 425TimingSimpleCPU::completeIfetch(Packet *pkt) 426{ 427 // received a response from the icache: execute the received 428 // instruction 429 assert(pkt->result == Packet::Success); 430 assert(_status == IcacheWaitResponse); 431 432 _status = Running; 433 434 delete pkt->req; 435 delete pkt; 436 437 if (getState() == SimObject::Draining) { 438 completeDrain(); 439 return; 440 } 441 442 preExecute(); 443 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 444 // load or store: just send to dcache 445 Fault fault = curStaticInst->initiateAcc(this, traceData); 446 if (fault == NoFault) { 447 // successfully initiated access: instruction will 448 // complete in dcache response callback 449 assert(_status == DcacheWaitResponse); 450 } else { 451 // fault: complete now to invoke fault handler 452 postExecute(); 453 advanceInst(fault); 454 } 455 } else { 456 // non-memory instruction: execute completely now 457 Fault fault = curStaticInst->execute(this, traceData); 458 postExecute(); 459 advanceInst(fault); 460 } 461} 462 463 464bool 465TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 466{ 467 cpu->completeIfetch(pkt); 468 return true; 469} 470 471void 472TimingSimpleCPU::IcachePort::recvRetry() 473{ 474 // we shouldn't get a retry unless we have a packet that we're 475 // waiting to transmit 476 assert(cpu->ifetch_pkt != NULL); 477 assert(cpu->_status == IcacheRetry); 478 Packet *tmp = cpu->ifetch_pkt; 479 if (sendTiming(tmp)) { 480 cpu->_status = IcacheWaitResponse; 481 cpu->ifetch_pkt = NULL; 482 } 483} 484 485void 486TimingSimpleCPU::completeDataAccess(Packet *pkt) 487{ 488 // received a response from the dcache: complete the load or store 489 // instruction 490 assert(pkt->result == Packet::Success); 491 assert(_status == DcacheWaitResponse); 492 _status = Running; 493 494 if (getState() == SimObject::Draining) { 495 completeDrain(); 496 497 delete pkt->req; 498 delete pkt; 499 500 return; 501 } 502 503 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 504 505 delete pkt->req; 506 delete pkt; 507 508 postExecute(); 509 advanceInst(fault); 510} 511 512 513void 514TimingSimpleCPU::completeDrain() 515{ 516 DPRINTF(Config, "Done draining\n"); 517 changeState(SimObject::DrainedTiming); 518 drainEvent->process(); 519} 520 521bool 522TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 523{ 524 cpu->completeDataAccess(pkt); 525 return true; 526} 527 528void 529TimingSimpleCPU::DcachePort::recvRetry() 530{ 531 // we shouldn't get a retry unless we have a packet that we're 532 // waiting to transmit 533 assert(cpu->dcache_pkt != NULL); 534 assert(cpu->_status == DcacheRetry); 535 Packet *tmp = cpu->dcache_pkt; 536 if (sendTiming(tmp)) { 537 cpu->_status = DcacheWaitResponse; 538 cpu->dcache_pkt = NULL; 539 } 540} 541 542 543//////////////////////////////////////////////////////////////////////// 544// 545// TimingSimpleCPU Simulation Object 546// 547BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 548 549 Param<Counter> max_insts_any_thread; 550 Param<Counter> max_insts_all_threads; 551 Param<Counter> max_loads_any_thread; 552 Param<Counter> max_loads_all_threads; 553 SimObjectParam<MemObject *> mem; 554 555#if FULL_SYSTEM 556 SimObjectParam<AlphaITB *> itb; 557 SimObjectParam<AlphaDTB *> dtb; 558 SimObjectParam<System *> system; 559 Param<int> cpu_id; 560 Param<Tick> profile; 561#else 562 SimObjectParam<Process *> workload; 563#endif // FULL_SYSTEM 564 565 Param<int> clock; 566 567 Param<bool> defer_registration; 568 Param<int> width; 569 Param<bool> function_trace; 570 Param<Tick> function_trace_start; 571 Param<bool> simulate_stalls; 572 573END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 574 575BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 576 577 INIT_PARAM(max_insts_any_thread, 578 "terminate when any thread reaches this inst count"), 579 INIT_PARAM(max_insts_all_threads, 580 "terminate when all threads have reached this inst count"), 581 INIT_PARAM(max_loads_any_thread, 582 "terminate when any thread reaches this load count"), 583 INIT_PARAM(max_loads_all_threads, 584 "terminate when all threads have reached this load count"), 585 INIT_PARAM(mem, "memory"), 586 587#if FULL_SYSTEM 588 INIT_PARAM(itb, "Instruction TLB"), 589 INIT_PARAM(dtb, "Data TLB"), 590 INIT_PARAM(system, "system object"), 591 INIT_PARAM(cpu_id, "processor ID"), 592 INIT_PARAM(profile, ""), 593#else 594 INIT_PARAM(workload, "processes to run"), 595#endif // FULL_SYSTEM 596 597 INIT_PARAM(clock, "clock speed"), 598 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 599 INIT_PARAM(width, "cpu width"), 600 INIT_PARAM(function_trace, "Enable function trace"), 601 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 602 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 603 604END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 605 606 607CREATE_SIM_OBJECT(TimingSimpleCPU) 608{ 609 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 610 params->name = getInstanceName(); 611 params->numberOfThreads = 1; 612 params->max_insts_any_thread = max_insts_any_thread; 613 params->max_insts_all_threads = max_insts_all_threads; 614 params->max_loads_any_thread = max_loads_any_thread; 615 params->max_loads_all_threads = max_loads_all_threads; 616 params->deferRegistration = defer_registration; 617 params->clock = clock; 618 params->functionTrace = function_trace; 619 params->functionTraceStart = function_trace_start; 620 params->mem = mem; 621 622#if FULL_SYSTEM 623 params->itb = itb; 624 params->dtb = dtb; 625 params->system = system; 626 params->cpu_id = cpu_id; 627 params->profile = profile; 628#else 629 params->process = workload; 630#endif 631 632 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 633 return cpu; 634} 635 636REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 637 638