timing.cc revision 2856:89691405ec9c
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/utility.hh" 32#include "cpu/exetrace.hh" 33#include "cpu/simple/timing.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" 36 37using namespace std; 38using namespace TheISA; 39 40Port * 41TimingSimpleCPU::getPort(const std::string &if_name, int idx) 42{ 43 if (if_name == "dcache_port") 44 return &dcachePort; 45 else if (if_name == "icache_port") 46 return &icachePort; 47 else 48 panic("No Such Port\n"); 49} 50 51void 52TimingSimpleCPU::init() 53{ 54 BaseCPU::init(); 55#if FULL_SYSTEM 56 for (int i = 0; i < threadContexts.size(); ++i) { 57 ThreadContext *tc = threadContexts[i]; 58 59 // initialize CPU, including PC 60 TheISA::initCPU(tc, tc->readCpuId()); 61 } 62#endif 63} 64 65Tick 66TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 67{ 68 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 69 return curTick; 70} 71 72void 73TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 74{ 75 panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 76} 77 78void 79TimingSimpleCPU::CpuPort::recvStatusChange(Status status) 80{ 81 if (status == RangeChange) 82 return; 83 84 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 85} 86 87TimingSimpleCPU::TimingSimpleCPU(Params *p) 88 : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 89{ 90 _status = Idle; 91 ifetch_pkt = dcache_pkt = NULL; 92 drainEvent = NULL; 93 state = SimObject::Timing; 94} 95 96 97TimingSimpleCPU::~TimingSimpleCPU() 98{ 99} 100 101void 102TimingSimpleCPU::serialize(ostream &os) 103{ 104 SERIALIZE_ENUM(_status); 105 BaseSimpleCPU::serialize(os); 106} 107 108void 109TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 110{ 111 UNSERIALIZE_ENUM(_status); 112 BaseSimpleCPU::unserialize(cp, section); 113} 114 115bool 116TimingSimpleCPU::drain(Event *drain_event) 117{ 118 // TimingSimpleCPU is ready to drain if it's not waiting for 119 // an access to complete. 120 if (status() == Idle || status() == Running || status() == SwitchedOut) { 121 changeState(SimObject::DrainedTiming); 122 return false; 123 } else { 124 changeState(SimObject::Draining); 125 drainEvent = drain_event; 126 return true; 127 } 128} 129 130void 131TimingSimpleCPU::resume() 132{ 133 if (_status != SwitchedOut && _status != Idle) { 134 Event *e = 135 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true); 136 e->schedule(curTick); 137 } 138} 139 140void 141TimingSimpleCPU::setMemoryMode(State new_mode) 142{ 143 assert(new_mode == SimObject::Timing); 144} 145 146void 147TimingSimpleCPU::switchOut() 148{ 149 assert(status() == Running || status() == Idle); 150 _status = SwitchedOut; 151} 152 153 154void 155TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 156{ 157 BaseCPU::takeOverFrom(oldCPU); 158 159 // if any of this CPU's ThreadContexts are active, mark the CPU as 160 // running and schedule its tick event. 161 for (int i = 0; i < threadContexts.size(); ++i) { 162 ThreadContext *tc = threadContexts[i]; 163 if (tc->status() == ThreadContext::Active && _status != Running) { 164 _status = Running; 165 break; 166 } 167 } 168} 169 170 171void 172TimingSimpleCPU::activateContext(int thread_num, int delay) 173{ 174 assert(thread_num == 0); 175 assert(thread); 176 177 assert(_status == Idle); 178 179 notIdleFraction++; 180 _status = Running; 181 // kick things off by initiating the fetch of the next instruction 182 Event *e = 183 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true); 184 e->schedule(curTick + cycles(delay)); 185} 186 187 188void 189TimingSimpleCPU::suspendContext(int thread_num) 190{ 191 assert(thread_num == 0); 192 assert(thread); 193 194 assert(_status == Running); 195 196 // just change status to Idle... if status != Running, 197 // completeInst() will not initiate fetch of next instruction. 198 199 notIdleFraction--; 200 _status = Idle; 201} 202 203 204template <class T> 205Fault 206TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 207{ 208 // need to fill in CPU & thread IDs here 209 Request *data_read_req = new Request(); 210 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 211 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 212 213 if (traceData) { 214 traceData->setAddr(data_read_req->getVaddr()); 215 } 216 217 // translate to physical address 218 Fault fault = thread->translateDataReadReq(data_read_req); 219 220 // Now do the access. 221 if (fault == NoFault) { 222 Packet *data_read_pkt = 223 new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast); 224 data_read_pkt->dataDynamic<T>(new T); 225 226 if (!dcachePort.sendTiming(data_read_pkt)) { 227 _status = DcacheRetry; 228 dcache_pkt = data_read_pkt; 229 } else { 230 _status = DcacheWaitResponse; 231 dcache_pkt = NULL; 232 } 233 } 234 235 // This will need a new way to tell if it has a dcache attached. 236 if (data_read_req->getFlags() & UNCACHEABLE) 237 recordEvent("Uncached Read"); 238 239 return fault; 240} 241 242#ifndef DOXYGEN_SHOULD_SKIP_THIS 243 244template 245Fault 246TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 247 248template 249Fault 250TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 251 252template 253Fault 254TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 255 256template 257Fault 258TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 259 260#endif //DOXYGEN_SHOULD_SKIP_THIS 261 262template<> 263Fault 264TimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 265{ 266 return read(addr, *(uint64_t*)&data, flags); 267} 268 269template<> 270Fault 271TimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 272{ 273 return read(addr, *(uint32_t*)&data, flags); 274} 275 276 277template<> 278Fault 279TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 280{ 281 return read(addr, (uint32_t&)data, flags); 282} 283 284 285template <class T> 286Fault 287TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 288{ 289 // need to fill in CPU & thread IDs here 290 Request *data_write_req = new Request(); 291 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 292 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 293 294 // translate to physical address 295 Fault fault = thread->translateDataWriteReq(data_write_req); 296 // Now do the access. 297 if (fault == NoFault) { 298 Packet *data_write_pkt = 299 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast); 300 data_write_pkt->allocate(); 301 data_write_pkt->set(data); 302 303 if (!dcachePort.sendTiming(data_write_pkt)) { 304 _status = DcacheRetry; 305 dcache_pkt = data_write_pkt; 306 } else { 307 _status = DcacheWaitResponse; 308 dcache_pkt = NULL; 309 } 310 } 311 312 // This will need a new way to tell if it's hooked up to a cache or not. 313 if (data_write_req->getFlags() & UNCACHEABLE) 314 recordEvent("Uncached Write"); 315 316 // If the write needs to have a fault on the access, consider calling 317 // changeStatus() and changing it to "bad addr write" or something. 318 return fault; 319} 320 321 322#ifndef DOXYGEN_SHOULD_SKIP_THIS 323template 324Fault 325TimingSimpleCPU::write(uint64_t data, Addr addr, 326 unsigned flags, uint64_t *res); 327 328template 329Fault 330TimingSimpleCPU::write(uint32_t data, Addr addr, 331 unsigned flags, uint64_t *res); 332 333template 334Fault 335TimingSimpleCPU::write(uint16_t data, Addr addr, 336 unsigned flags, uint64_t *res); 337 338template 339Fault 340TimingSimpleCPU::write(uint8_t data, Addr addr, 341 unsigned flags, uint64_t *res); 342 343#endif //DOXYGEN_SHOULD_SKIP_THIS 344 345template<> 346Fault 347TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 348{ 349 return write(*(uint64_t*)&data, addr, flags, res); 350} 351 352template<> 353Fault 354TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 355{ 356 return write(*(uint32_t*)&data, addr, flags, res); 357} 358 359 360template<> 361Fault 362TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 363{ 364 return write((uint32_t)data, addr, flags, res); 365} 366 367 368void 369TimingSimpleCPU::fetch() 370{ 371 checkForInterrupts(); 372 373 // need to fill in CPU & thread IDs here 374 Request *ifetch_req = new Request(); 375 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 376 Fault fault = setupFetchRequest(ifetch_req); 377 378 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 379 ifetch_pkt->dataStatic(&inst); 380 381 if (fault == NoFault) { 382 if (!icachePort.sendTiming(ifetch_pkt)) { 383 // Need to wait for retry 384 _status = IcacheRetry; 385 } else { 386 // Need to wait for cache to respond 387 _status = IcacheWaitResponse; 388 // ownership of packet transferred to memory system 389 ifetch_pkt = NULL; 390 } 391 } else { 392 // fetch fault: advance directly to next instruction (fault handler) 393 advanceInst(fault); 394 } 395} 396 397 398void 399TimingSimpleCPU::advanceInst(Fault fault) 400{ 401 advancePC(fault); 402 403 if (_status == Running) { 404 // kick off fetch of next instruction... callback from icache 405 // response will cause that instruction to be executed, 406 // keeping the CPU running. 407 fetch(); 408 } 409} 410 411 412void 413TimingSimpleCPU::completeIfetch(Packet *pkt) 414{ 415 // received a response from the icache: execute the received 416 // instruction 417 assert(pkt->result == Packet::Success); 418 assert(_status == IcacheWaitResponse); 419 420 _status = Running; 421 422 delete pkt->req; 423 delete pkt; 424 425 if (getState() == SimObject::Draining) { 426 completeDrain(); 427 return; 428 } 429 430 preExecute(); 431 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 432 // load or store: just send to dcache 433 Fault fault = curStaticInst->initiateAcc(this, traceData); 434 if (fault == NoFault) { 435 // successfully initiated access: instruction will 436 // complete in dcache response callback 437 assert(_status == DcacheWaitResponse); 438 } else { 439 // fault: complete now to invoke fault handler 440 postExecute(); 441 advanceInst(fault); 442 } 443 } else { 444 // non-memory instruction: execute completely now 445 Fault fault = curStaticInst->execute(this, traceData); 446 postExecute(); 447 advanceInst(fault); 448 } 449} 450 451 452bool 453TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 454{ 455 if (cpu->_status == DcacheWaitResponse) 456 cpu->completeDataAccess(pkt); 457 else if (cpu->_status == IcacheWaitResponse) 458 cpu->completeIfetch(pkt); 459 else 460 assert("OOPS" && 0); 461 return true; 462} 463 464void 465TimingSimpleCPU::IcachePort::recvRetry() 466{ 467 // we shouldn't get a retry unless we have a packet that we're 468 // waiting to transmit 469 assert(cpu->ifetch_pkt != NULL); 470 assert(cpu->_status == IcacheRetry); 471 Packet *tmp = cpu->ifetch_pkt; 472 if (sendTiming(tmp)) { 473 cpu->_status = IcacheWaitResponse; 474 cpu->ifetch_pkt = NULL; 475 } 476} 477 478void 479TimingSimpleCPU::completeDataAccess(Packet *pkt) 480{ 481 // received a response from the dcache: complete the load or store 482 // instruction 483 assert(pkt->result == Packet::Success); 484 assert(_status == DcacheWaitResponse); 485 _status = Running; 486 487 if (getState() == SimObject::Draining) { 488 completeDrain(); 489 490 delete pkt->req; 491 delete pkt; 492 493 return; 494 } 495 496 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 497 498 delete pkt->req; 499 delete pkt; 500 501 postExecute(); 502 advanceInst(fault); 503} 504 505 506void 507TimingSimpleCPU::completeDrain() 508{ 509 DPRINTF(Config, "Done draining\n"); 510 changeState(SimObject::DrainedTiming); 511 drainEvent->process(); 512} 513 514bool 515TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 516{ 517 cpu->completeDataAccess(pkt); 518 return true; 519} 520 521void 522TimingSimpleCPU::DcachePort::recvRetry() 523{ 524 // we shouldn't get a retry unless we have a packet that we're 525 // waiting to transmit 526 assert(cpu->dcache_pkt != NULL); 527 assert(cpu->_status == DcacheRetry); 528 Packet *tmp = cpu->dcache_pkt; 529 if (sendTiming(tmp)) { 530 cpu->_status = DcacheWaitResponse; 531 cpu->dcache_pkt = NULL; 532 } 533} 534 535 536//////////////////////////////////////////////////////////////////////// 537// 538// TimingSimpleCPU Simulation Object 539// 540BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 541 542 Param<Counter> max_insts_any_thread; 543 Param<Counter> max_insts_all_threads; 544 Param<Counter> max_loads_any_thread; 545 Param<Counter> max_loads_all_threads; 546 SimObjectParam<MemObject *> mem; 547 548#if FULL_SYSTEM 549 SimObjectParam<AlphaITB *> itb; 550 SimObjectParam<AlphaDTB *> dtb; 551 SimObjectParam<System *> system; 552 Param<int> cpu_id; 553 Param<Tick> profile; 554#else 555 SimObjectParam<Process *> workload; 556#endif // FULL_SYSTEM 557 558 Param<int> clock; 559 560 Param<bool> defer_registration; 561 Param<int> width; 562 Param<bool> function_trace; 563 Param<Tick> function_trace_start; 564 Param<bool> simulate_stalls; 565 566END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 567 568BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 569 570 INIT_PARAM(max_insts_any_thread, 571 "terminate when any thread reaches this inst count"), 572 INIT_PARAM(max_insts_all_threads, 573 "terminate when all threads have reached this inst count"), 574 INIT_PARAM(max_loads_any_thread, 575 "terminate when any thread reaches this load count"), 576 INIT_PARAM(max_loads_all_threads, 577 "terminate when all threads have reached this load count"), 578 INIT_PARAM(mem, "memory"), 579 580#if FULL_SYSTEM 581 INIT_PARAM(itb, "Instruction TLB"), 582 INIT_PARAM(dtb, "Data TLB"), 583 INIT_PARAM(system, "system object"), 584 INIT_PARAM(cpu_id, "processor ID"), 585 INIT_PARAM(profile, ""), 586#else 587 INIT_PARAM(workload, "processes to run"), 588#endif // FULL_SYSTEM 589 590 INIT_PARAM(clock, "clock speed"), 591 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 592 INIT_PARAM(width, "cpu width"), 593 INIT_PARAM(function_trace, "Enable function trace"), 594 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 595 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 596 597END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 598 599 600CREATE_SIM_OBJECT(TimingSimpleCPU) 601{ 602 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 603 params->name = getInstanceName(); 604 params->numberOfThreads = 1; 605 params->max_insts_any_thread = max_insts_any_thread; 606 params->max_insts_all_threads = max_insts_all_threads; 607 params->max_loads_any_thread = max_loads_any_thread; 608 params->max_loads_all_threads = max_loads_all_threads; 609 params->deferRegistration = defer_registration; 610 params->clock = clock; 611 params->functionTrace = function_trace; 612 params->functionTraceStart = function_trace_start; 613 params->mem = mem; 614 615#if FULL_SYSTEM 616 params->itb = itb; 617 params->dtb = dtb; 618 params->system = system; 619 params->cpu_id = cpu_id; 620 params->profile = profile; 621#else 622 params->process = workload; 623#endif 624 625 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 626 return cpu; 627} 628 629REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 630 631