timing.cc revision 2641:6d9d837e2032
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "arch/utility.hh" 30#include "cpu/exetrace.hh" 31#include "cpu/simple/timing.hh" 32#include "mem/packet_impl.hh" 33#include "sim/builder.hh" 34 35using namespace std; 36using namespace TheISA; 37 38 39void 40TimingSimpleCPU::init() 41{ 42 //Create Memory Ports (conect them up) 43 Port *mem_dport = mem->getPort(""); 44 dcachePort.setPeer(mem_dport); 45 mem_dport->setPeer(&dcachePort); 46 47 Port *mem_iport = mem->getPort(""); 48 icachePort.setPeer(mem_iport); 49 mem_iport->setPeer(&icachePort); 50 51 BaseCPU::init(); 52#if FULL_SYSTEM 53 for (int i = 0; i < execContexts.size(); ++i) { 54 ExecContext *xc = execContexts[i]; 55 56 // initialize CPU, including PC 57 TheISA::initCPU(xc, xc->readCpuId()); 58 } 59#endif 60} 61 62Tick 63TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 64{ 65 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 66 return curTick; 67} 68 69void 70TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 71{ 72 panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 73} 74 75void 76TimingSimpleCPU::CpuPort::recvStatusChange(Status status) 77{ 78 if (status == RangeChange) 79 return; 80 81 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 82} 83 84TimingSimpleCPU::TimingSimpleCPU(Params *p) 85 : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 86{ 87 _status = Idle; 88 ifetch_pkt = dcache_pkt = NULL; 89} 90 91 92TimingSimpleCPU::~TimingSimpleCPU() 93{ 94} 95 96void 97TimingSimpleCPU::serialize(ostream &os) 98{ 99 BaseSimpleCPU::serialize(os); 100 SERIALIZE_ENUM(_status); 101} 102 103void 104TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 105{ 106 BaseSimpleCPU::unserialize(cp, section); 107 UNSERIALIZE_ENUM(_status); 108} 109 110void 111TimingSimpleCPU::switchOut(Sampler *s) 112{ 113 sampler = s; 114 if (status() == Running) { 115 _status = SwitchedOut; 116 } 117 sampler->signalSwitched(); 118} 119 120 121void 122TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 123{ 124 BaseCPU::takeOverFrom(oldCPU); 125 126 // if any of this CPU's ExecContexts are active, mark the CPU as 127 // running and schedule its tick event. 128 for (int i = 0; i < execContexts.size(); ++i) { 129 ExecContext *xc = execContexts[i]; 130 if (xc->status() == ExecContext::Active && _status != Running) { 131 _status = Running; 132 break; 133 } 134 } 135} 136 137 138void 139TimingSimpleCPU::activateContext(int thread_num, int delay) 140{ 141 assert(thread_num == 0); 142 assert(cpuXC); 143 144 assert(_status == Idle); 145 146 notIdleFraction++; 147 _status = Running; 148 // kick things off by initiating the fetch of the next instruction 149 Event *e = 150 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true); 151 e->schedule(curTick + cycles(delay)); 152} 153 154 155void 156TimingSimpleCPU::suspendContext(int thread_num) 157{ 158 assert(thread_num == 0); 159 assert(cpuXC); 160 161 panic("TimingSimpleCPU::suspendContext not implemented"); 162 163 assert(_status == Running); 164 165 notIdleFraction--; 166 _status = Idle; 167} 168 169 170template <class T> 171Fault 172TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 173{ 174 Request *data_read_req = new Request(true); 175 176 data_read_req->setVaddr(addr); 177 data_read_req->setSize(sizeof(T)); 178 data_read_req->setFlags(flags); 179 data_read_req->setTime(curTick); 180 181 if (traceData) { 182 traceData->setAddr(data_read_req->getVaddr()); 183 } 184 185 // translate to physical address 186 Fault fault = cpuXC->translateDataReadReq(data_read_req); 187 188 // Now do the access. 189 if (fault == NoFault) { 190 Packet *data_read_pkt = 191 new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast); 192 data_read_pkt->dataDynamic<T>(new T); 193 194 if (!dcachePort.sendTiming(data_read_pkt)) { 195 _status = DcacheRetry; 196 dcache_pkt = data_read_pkt; 197 } else { 198 _status = DcacheWaitResponse; 199 dcache_pkt = NULL; 200 } 201 } 202 203 // This will need a new way to tell if it has a dcache attached. 204 if (data_read_req->getFlags() & UNCACHEABLE) 205 recordEvent("Uncached Read"); 206 207 return fault; 208} 209 210#ifndef DOXYGEN_SHOULD_SKIP_THIS 211 212template 213Fault 214TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 215 216template 217Fault 218TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 219 220template 221Fault 222TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 223 224template 225Fault 226TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 227 228#endif //DOXYGEN_SHOULD_SKIP_THIS 229 230template<> 231Fault 232TimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 233{ 234 return read(addr, *(uint64_t*)&data, flags); 235} 236 237template<> 238Fault 239TimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 240{ 241 return read(addr, *(uint32_t*)&data, flags); 242} 243 244 245template<> 246Fault 247TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 248{ 249 return read(addr, (uint32_t&)data, flags); 250} 251 252 253template <class T> 254Fault 255TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 256{ 257 Request *data_write_req = new Request(true); 258 data_write_req->setVaddr(addr); 259 data_write_req->setTime(curTick); 260 data_write_req->setSize(sizeof(T)); 261 data_write_req->setFlags(flags); 262 263 // translate to physical address 264 Fault fault = cpuXC->translateDataWriteReq(data_write_req); 265 // Now do the access. 266 if (fault == NoFault) { 267 Packet *data_write_pkt = 268 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast); 269 data_write_pkt->allocate(); 270 data_write_pkt->set(data); 271 272 if (!dcachePort.sendTiming(data_write_pkt)) { 273 _status = DcacheRetry; 274 dcache_pkt = data_write_pkt; 275 } else { 276 _status = DcacheWaitResponse; 277 dcache_pkt = NULL; 278 } 279 } 280 281 // This will need a new way to tell if it's hooked up to a cache or not. 282 if (data_write_req->getFlags() & UNCACHEABLE) 283 recordEvent("Uncached Write"); 284 285 // If the write needs to have a fault on the access, consider calling 286 // changeStatus() and changing it to "bad addr write" or something. 287 return fault; 288} 289 290 291#ifndef DOXYGEN_SHOULD_SKIP_THIS 292template 293Fault 294TimingSimpleCPU::write(uint64_t data, Addr addr, 295 unsigned flags, uint64_t *res); 296 297template 298Fault 299TimingSimpleCPU::write(uint32_t data, Addr addr, 300 unsigned flags, uint64_t *res); 301 302template 303Fault 304TimingSimpleCPU::write(uint16_t data, Addr addr, 305 unsigned flags, uint64_t *res); 306 307template 308Fault 309TimingSimpleCPU::write(uint8_t data, Addr addr, 310 unsigned flags, uint64_t *res); 311 312#endif //DOXYGEN_SHOULD_SKIP_THIS 313 314template<> 315Fault 316TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 317{ 318 return write(*(uint64_t*)&data, addr, flags, res); 319} 320 321template<> 322Fault 323TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 324{ 325 return write(*(uint32_t*)&data, addr, flags, res); 326} 327 328 329template<> 330Fault 331TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 332{ 333 return write((uint32_t)data, addr, flags, res); 334} 335 336 337void 338TimingSimpleCPU::fetch() 339{ 340 checkForInterrupts(); 341 342 Request *ifetch_req = new Request(true); 343 ifetch_req->setSize(sizeof(MachInst)); 344 345 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 346 ifetch_pkt->dataStatic(&inst); 347 348 Fault fault = setupFetchPacket(ifetch_pkt); 349 if (fault == NoFault) { 350 if (!icachePort.sendTiming(ifetch_pkt)) { 351 // Need to wait for retry 352 _status = IcacheRetry; 353 } else { 354 // Need to wait for cache to respond 355 _status = IcacheWaitResponse; 356 // ownership of packet transferred to memory system 357 ifetch_pkt = NULL; 358 } 359 } else { 360 panic("TimingSimpleCPU fetch fault handling not implemented"); 361 } 362} 363 364 365void 366TimingSimpleCPU::completeInst(Fault fault) 367{ 368 postExecute(); 369 370 if (traceData) { 371 traceData->finalize(); 372 } 373 374 advancePC(fault); 375 376 if (_status == Running) { 377 // kick off fetch of next instruction... callback from icache 378 // response will cause that instruction to be executed, 379 // keeping the CPU running. 380 fetch(); 381 } 382} 383 384 385void 386TimingSimpleCPU::completeIfetch() 387{ 388 // received a response from the icache: execute the received 389 // instruction 390 assert(_status == IcacheWaitResponse); 391 _status = Running; 392 preExecute(); 393 if (curStaticInst->isMemRef()) { 394 // load or store: just send to dcache 395 Fault fault = curStaticInst->initiateAcc(this, traceData); 396 assert(fault == NoFault); 397 assert(_status == DcacheWaitResponse); 398 // instruction will complete in dcache response callback 399 } else { 400 // non-memory instruction: execute completely now 401 Fault fault = curStaticInst->execute(this, traceData); 402 completeInst(fault); 403 } 404} 405 406 407bool 408TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 409{ 410 cpu->completeIfetch(); 411 return true; 412} 413 414Packet * 415TimingSimpleCPU::IcachePort::recvRetry() 416{ 417 // we shouldn't get a retry unless we have a packet that we're 418 // waiting to transmit 419 assert(cpu->ifetch_pkt != NULL); 420 assert(cpu->_status == IcacheRetry); 421 cpu->_status = IcacheWaitResponse; 422 Packet *tmp = cpu->ifetch_pkt; 423 cpu->ifetch_pkt = NULL; 424 return tmp; 425} 426 427void 428TimingSimpleCPU::completeDataAccess(Packet *pkt) 429{ 430 // received a response from the dcache: complete the load or store 431 // instruction 432 assert(pkt->result == Packet::Success); 433 assert(_status == DcacheWaitResponse); 434 _status = Running; 435 436 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 437 438 completeInst(fault); 439} 440 441 442 443bool 444TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 445{ 446 cpu->completeDataAccess(pkt); 447 return true; 448} 449 450Packet * 451TimingSimpleCPU::DcachePort::recvRetry() 452{ 453 // we shouldn't get a retry unless we have a packet that we're 454 // waiting to transmit 455 assert(cpu->dcache_pkt != NULL); 456 assert(cpu->_status == DcacheRetry); 457 cpu->_status = DcacheWaitResponse; 458 Packet *tmp = cpu->dcache_pkt; 459 cpu->dcache_pkt = NULL; 460 return tmp; 461} 462 463 464//////////////////////////////////////////////////////////////////////// 465// 466// TimingSimpleCPU Simulation Object 467// 468BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 469 470 Param<Counter> max_insts_any_thread; 471 Param<Counter> max_insts_all_threads; 472 Param<Counter> max_loads_any_thread; 473 Param<Counter> max_loads_all_threads; 474 SimObjectParam<MemObject *> mem; 475 476#if FULL_SYSTEM 477 SimObjectParam<AlphaITB *> itb; 478 SimObjectParam<AlphaDTB *> dtb; 479 SimObjectParam<System *> system; 480 Param<int> cpu_id; 481 Param<Tick> profile; 482#else 483 SimObjectParam<Process *> workload; 484#endif // FULL_SYSTEM 485 486 Param<int> clock; 487 488 Param<bool> defer_registration; 489 Param<int> width; 490 Param<bool> function_trace; 491 Param<Tick> function_trace_start; 492 Param<bool> simulate_stalls; 493 494END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 495 496BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 497 498 INIT_PARAM(max_insts_any_thread, 499 "terminate when any thread reaches this inst count"), 500 INIT_PARAM(max_insts_all_threads, 501 "terminate when all threads have reached this inst count"), 502 INIT_PARAM(max_loads_any_thread, 503 "terminate when any thread reaches this load count"), 504 INIT_PARAM(max_loads_all_threads, 505 "terminate when all threads have reached this load count"), 506 INIT_PARAM(mem, "memory"), 507 508#if FULL_SYSTEM 509 INIT_PARAM(itb, "Instruction TLB"), 510 INIT_PARAM(dtb, "Data TLB"), 511 INIT_PARAM(system, "system object"), 512 INIT_PARAM(cpu_id, "processor ID"), 513 INIT_PARAM(profile, ""), 514#else 515 INIT_PARAM(workload, "processes to run"), 516#endif // FULL_SYSTEM 517 518 INIT_PARAM(clock, "clock speed"), 519 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 520 INIT_PARAM(width, "cpu width"), 521 INIT_PARAM(function_trace, "Enable function trace"), 522 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 523 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 524 525END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 526 527 528CREATE_SIM_OBJECT(TimingSimpleCPU) 529{ 530 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 531 params->name = getInstanceName(); 532 params->numberOfThreads = 1; 533 params->max_insts_any_thread = max_insts_any_thread; 534 params->max_insts_all_threads = max_insts_all_threads; 535 params->max_loads_any_thread = max_loads_any_thread; 536 params->max_loads_all_threads = max_loads_all_threads; 537 params->deferRegistration = defer_registration; 538 params->clock = clock; 539 params->functionTrace = function_trace; 540 params->functionTraceStart = function_trace_start; 541 params->mem = mem; 542 543#if FULL_SYSTEM 544 params->itb = itb; 545 params->dtb = dtb; 546 params->system = system; 547 params->cpu_id = cpu_id; 548 params->profile = profile; 549#else 550 params->process = workload; 551#endif 552 553 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 554 return cpu; 555} 556 557REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 558 559