timing.cc revision 13954:2f400a5f2627
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013,2015,2017-2018 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "cpu/simple/timing.hh" 45 46#include "arch/locked_mem.hh" 47#include "arch/mmapped_ipr.hh" 48#include "arch/utility.hh" 49#include "config/the_isa.hh" 50#include "cpu/exetrace.hh" 51#include "debug/Config.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/Mwait.hh" 55#include "debug/SimpleCPU.hh" 56#include "mem/packet.hh" 57#include "mem/packet_access.hh" 58#include "params/TimingSimpleCPU.hh" 59#include "sim/faults.hh" 60#include "sim/full_system.hh" 61#include "sim/system.hh" 62 63using namespace std; 64using namespace TheISA; 65 66void 67TimingSimpleCPU::init() 68{ 69 BaseSimpleCPU::init(); 70} 71 72void 73TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 74{ 75 pkt = _pkt; 76 cpu->schedule(this, t); 77} 78 79TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 80 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 81 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 82 fetchEvent([this]{ fetch(); }, name()) 83{ 84 _status = Idle; 85} 86 87 88 89TimingSimpleCPU::~TimingSimpleCPU() 90{ 91} 92 93DrainState 94TimingSimpleCPU::drain() 95{ 96 // Deschedule any power gating event (if any) 97 deschedulePowerGatingEvent(); 98 99 if (switchedOut()) 100 return DrainState::Drained; 101 102 if (_status == Idle || 103 (_status == BaseSimpleCPU::Running && isDrained())) { 104 DPRINTF(Drain, "No need to drain.\n"); 105 activeThreads.clear(); 106 return DrainState::Drained; 107 } else { 108 DPRINTF(Drain, "Requesting drain.\n"); 109 110 // The fetch event can become descheduled if a drain didn't 111 // succeed on the first attempt. We need to reschedule it if 112 // the CPU is waiting for a microcode routine to complete. 113 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 114 schedule(fetchEvent, clockEdge()); 115 116 return DrainState::Draining; 117 } 118} 119 120void 121TimingSimpleCPU::drainResume() 122{ 123 assert(!fetchEvent.scheduled()); 124 if (switchedOut()) 125 return; 126 127 DPRINTF(SimpleCPU, "Resume\n"); 128 verifyMemoryMode(); 129 130 assert(!threadContexts.empty()); 131 132 _status = BaseSimpleCPU::Idle; 133 134 for (ThreadID tid = 0; tid < numThreads; tid++) { 135 if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 136 threadInfo[tid]->notIdleFraction = 1; 137 138 activeThreads.push_back(tid); 139 140 _status = BaseSimpleCPU::Running; 141 142 // Fetch if any threads active 143 if (!fetchEvent.scheduled()) { 144 schedule(fetchEvent, nextCycle()); 145 } 146 } else { 147 threadInfo[tid]->notIdleFraction = 0; 148 } 149 } 150 151 // Reschedule any power gating event (if any) 152 schedulePowerGatingEvent(); 153 154 system->totalNumInsts = 0; 155} 156 157bool 158TimingSimpleCPU::tryCompleteDrain() 159{ 160 if (drainState() != DrainState::Draining) 161 return false; 162 163 DPRINTF(Drain, "tryCompleteDrain.\n"); 164 if (!isDrained()) 165 return false; 166 167 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 168 signalDrainDone(); 169 170 return true; 171} 172 173void 174TimingSimpleCPU::switchOut() 175{ 176 SimpleExecContext& t_info = *threadInfo[curThread]; 177 M5_VAR_USED SimpleThread* thread = t_info.thread; 178 179 BaseSimpleCPU::switchOut(); 180 181 assert(!fetchEvent.scheduled()); 182 assert(_status == BaseSimpleCPU::Running || _status == Idle); 183 assert(!t_info.stayAtPC); 184 assert(thread->microPC() == 0); 185 186 updateCycleCounts(); 187 updateCycleCounters(BaseCPU::CPU_STATE_ON); 188} 189 190 191void 192TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 193{ 194 BaseSimpleCPU::takeOverFrom(oldCPU); 195 196 previousCycle = curCycle(); 197} 198 199void 200TimingSimpleCPU::verifyMemoryMode() const 201{ 202 if (!system->isTimingMode()) { 203 fatal("The timing CPU requires the memory system to be in " 204 "'timing' mode.\n"); 205 } 206} 207 208void 209TimingSimpleCPU::activateContext(ThreadID thread_num) 210{ 211 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 212 213 assert(thread_num < numThreads); 214 215 threadInfo[thread_num]->notIdleFraction = 1; 216 if (_status == BaseSimpleCPU::Idle) 217 _status = BaseSimpleCPU::Running; 218 219 // kick things off by initiating the fetch of the next instruction 220 if (!fetchEvent.scheduled()) 221 schedule(fetchEvent, clockEdge(Cycles(0))); 222 223 if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 224 == activeThreads.end()) { 225 activeThreads.push_back(thread_num); 226 } 227 228 BaseCPU::activateContext(thread_num); 229} 230 231 232void 233TimingSimpleCPU::suspendContext(ThreadID thread_num) 234{ 235 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 236 237 assert(thread_num < numThreads); 238 activeThreads.remove(thread_num); 239 240 if (_status == Idle) 241 return; 242 243 assert(_status == BaseSimpleCPU::Running); 244 245 threadInfo[thread_num]->notIdleFraction = 0; 246 247 if (activeThreads.empty()) { 248 _status = Idle; 249 250 if (fetchEvent.scheduled()) { 251 deschedule(fetchEvent); 252 } 253 } 254 255 BaseCPU::suspendContext(thread_num); 256} 257 258bool 259TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 260{ 261 SimpleExecContext &t_info = *threadInfo[curThread]; 262 SimpleThread* thread = t_info.thread; 263 264 const RequestPtr &req = pkt->req; 265 266 // We're about the issues a locked load, so tell the monitor 267 // to start caring about this address 268 if (pkt->isRead() && pkt->req->isLLSC()) { 269 TheISA::handleLockedRead(thread, pkt->req); 270 } 271 if (req->isMmappedIpr()) { 272 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 273 new IprEvent(pkt, this, clockEdge(delay)); 274 _status = DcacheWaitResponse; 275 dcache_pkt = NULL; 276 } else if (!dcachePort.sendTimingReq(pkt)) { 277 _status = DcacheRetry; 278 dcache_pkt = pkt; 279 } else { 280 _status = DcacheWaitResponse; 281 // memory system takes ownership of packet 282 dcache_pkt = NULL; 283 } 284 return dcache_pkt == NULL; 285} 286 287void 288TimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, 289 bool read) 290{ 291 SimpleExecContext &t_info = *threadInfo[curThread]; 292 SimpleThread* thread = t_info.thread; 293 294 PacketPtr pkt = buildPacket(req, read); 295 pkt->dataDynamic<uint8_t>(data); 296 297 if (req->getFlags().isSet(Request::NO_ACCESS)) { 298 assert(!dcache_pkt); 299 pkt->makeResponse(); 300 completeDataAccess(pkt); 301 } else if (read) { 302 handleReadPacket(pkt); 303 } else { 304 bool do_access = true; // flag to suppress cache access 305 306 if (req->isLLSC()) { 307 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 308 } else if (req->isCondSwap()) { 309 assert(res); 310 req->setExtraData(*res); 311 } 312 313 if (do_access) { 314 dcache_pkt = pkt; 315 handleWritePacket(); 316 threadSnoop(pkt, curThread); 317 } else { 318 _status = DcacheWaitResponse; 319 completeDataAccess(pkt); 320 } 321 } 322} 323 324void 325TimingSimpleCPU::sendSplitData(const RequestPtr &req1, const RequestPtr &req2, 326 const RequestPtr &req, uint8_t *data, bool read) 327{ 328 PacketPtr pkt1, pkt2; 329 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 330 if (req->getFlags().isSet(Request::NO_ACCESS)) { 331 assert(!dcache_pkt); 332 pkt1->makeResponse(); 333 completeDataAccess(pkt1); 334 } else if (read) { 335 SplitFragmentSenderState * send_state = 336 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 337 if (handleReadPacket(pkt1)) { 338 send_state->clearFromParent(); 339 send_state = dynamic_cast<SplitFragmentSenderState *>( 340 pkt2->senderState); 341 if (handleReadPacket(pkt2)) { 342 send_state->clearFromParent(); 343 } 344 } 345 } else { 346 dcache_pkt = pkt1; 347 SplitFragmentSenderState * send_state = 348 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 349 if (handleWritePacket()) { 350 send_state->clearFromParent(); 351 dcache_pkt = pkt2; 352 send_state = dynamic_cast<SplitFragmentSenderState *>( 353 pkt2->senderState); 354 if (handleWritePacket()) { 355 send_state->clearFromParent(); 356 } 357 } 358 } 359} 360 361void 362TimingSimpleCPU::translationFault(const Fault &fault) 363{ 364 // fault may be NoFault in cases where a fault is suppressed, 365 // for instance prefetches. 366 updateCycleCounts(); 367 updateCycleCounters(BaseCPU::CPU_STATE_ON); 368 369 if (traceData) { 370 // Since there was a fault, we shouldn't trace this instruction. 371 delete traceData; 372 traceData = NULL; 373 } 374 375 postExecute(); 376 377 advanceInst(fault); 378} 379 380PacketPtr 381TimingSimpleCPU::buildPacket(const RequestPtr &req, bool read) 382{ 383 return read ? Packet::createRead(req) : Packet::createWrite(req); 384} 385 386void 387TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 388 const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, 389 uint8_t *data, bool read) 390{ 391 pkt1 = pkt2 = NULL; 392 393 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 394 395 if (req->getFlags().isSet(Request::NO_ACCESS)) { 396 pkt1 = buildPacket(req, read); 397 return; 398 } 399 400 pkt1 = buildPacket(req1, read); 401 pkt2 = buildPacket(req2, read); 402 403 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 404 405 pkt->dataDynamic<uint8_t>(data); 406 pkt1->dataStatic<uint8_t>(data); 407 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 408 409 SplitMainSenderState * main_send_state = new SplitMainSenderState; 410 pkt->senderState = main_send_state; 411 main_send_state->fragments[0] = pkt1; 412 main_send_state->fragments[1] = pkt2; 413 main_send_state->outstanding = 2; 414 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 415 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 416} 417 418Fault 419TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, 420 Request::Flags flags, 421 const std::vector<bool>& byteEnable) 422{ 423 SimpleExecContext &t_info = *threadInfo[curThread]; 424 SimpleThread* thread = t_info.thread; 425 426 Fault fault; 427 const int asid = 0; 428 const Addr pc = thread->instAddr(); 429 unsigned block_size = cacheLineSize(); 430 BaseTLB::Mode mode = BaseTLB::Read; 431 432 if (traceData) 433 traceData->setMem(addr, size, flags); 434 435 RequestPtr req = std::make_shared<Request>( 436 asid, addr, size, flags, dataMasterId(), pc, 437 thread->contextId()); 438 if (!byteEnable.empty()) { 439 req->setByteEnable(byteEnable); 440 } 441 442 req->taskId(taskId()); 443 444 Addr split_addr = roundDown(addr + size - 1, block_size); 445 assert(split_addr <= addr || split_addr - addr < block_size); 446 447 _status = DTBWaitResponse; 448 if (split_addr > addr) { 449 RequestPtr req1, req2; 450 assert(!req->isLLSC() && !req->isSwap()); 451 req->splitOnVaddr(split_addr, req1, req2); 452 453 WholeTranslationState *state = 454 new WholeTranslationState(req, req1, req2, new uint8_t[size], 455 NULL, mode); 456 DataTranslation<TimingSimpleCPU *> *trans1 = 457 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 458 DataTranslation<TimingSimpleCPU *> *trans2 = 459 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 460 461 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 462 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 463 } else { 464 WholeTranslationState *state = 465 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 466 DataTranslation<TimingSimpleCPU *> *translation 467 = new DataTranslation<TimingSimpleCPU *>(this, state); 468 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 469 } 470 471 return NoFault; 472} 473 474bool 475TimingSimpleCPU::handleWritePacket() 476{ 477 SimpleExecContext &t_info = *threadInfo[curThread]; 478 SimpleThread* thread = t_info.thread; 479 480 const RequestPtr &req = dcache_pkt->req; 481 if (req->isMmappedIpr()) { 482 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 483 new IprEvent(dcache_pkt, this, clockEdge(delay)); 484 _status = DcacheWaitResponse; 485 dcache_pkt = NULL; 486 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 487 _status = DcacheRetry; 488 } else { 489 _status = DcacheWaitResponse; 490 // memory system takes ownership of packet 491 dcache_pkt = NULL; 492 } 493 return dcache_pkt == NULL; 494} 495 496Fault 497TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 498 Addr addr, Request::Flags flags, uint64_t *res, 499 const std::vector<bool>& byteEnable) 500{ 501 SimpleExecContext &t_info = *threadInfo[curThread]; 502 SimpleThread* thread = t_info.thread; 503 504 uint8_t *newData = new uint8_t[size]; 505 const int asid = 0; 506 const Addr pc = thread->instAddr(); 507 unsigned block_size = cacheLineSize(); 508 BaseTLB::Mode mode = BaseTLB::Write; 509 510 if (data == NULL) { 511 assert(flags & Request::STORE_NO_DATA); 512 // This must be a cache block cleaning request 513 memset(newData, 0, size); 514 } else { 515 memcpy(newData, data, size); 516 } 517 518 if (traceData) 519 traceData->setMem(addr, size, flags); 520 521 RequestPtr req = std::make_shared<Request>( 522 asid, addr, size, flags, dataMasterId(), pc, 523 thread->contextId()); 524 if (!byteEnable.empty()) { 525 req->setByteEnable(byteEnable); 526 } 527 528 req->taskId(taskId()); 529 530 Addr split_addr = roundDown(addr + size - 1, block_size); 531 assert(split_addr <= addr || split_addr - addr < block_size); 532 533 _status = DTBWaitResponse; 534 535 // TODO: TimingSimpleCPU doesn't support arbitrarily long multi-line mem. 536 // accesses yet 537 538 if (split_addr > addr) { 539 RequestPtr req1, req2; 540 assert(!req->isLLSC() && !req->isSwap()); 541 req->splitOnVaddr(split_addr, req1, req2); 542 543 WholeTranslationState *state = 544 new WholeTranslationState(req, req1, req2, newData, res, mode); 545 DataTranslation<TimingSimpleCPU *> *trans1 = 546 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 547 DataTranslation<TimingSimpleCPU *> *trans2 = 548 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 549 550 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 551 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 552 } else { 553 WholeTranslationState *state = 554 new WholeTranslationState(req, newData, res, mode); 555 DataTranslation<TimingSimpleCPU *> *translation = 556 new DataTranslation<TimingSimpleCPU *>(this, state); 557 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 558 } 559 560 // Translation faults will be returned via finishTranslation() 561 return NoFault; 562} 563 564Fault 565TimingSimpleCPU::initiateMemAMO(Addr addr, unsigned size, 566 Request::Flags flags, 567 AtomicOpFunctor *amo_op) 568{ 569 SimpleExecContext &t_info = *threadInfo[curThread]; 570 SimpleThread* thread = t_info.thread; 571 572 Fault fault; 573 const int asid = 0; 574 const Addr pc = thread->instAddr(); 575 unsigned block_size = cacheLineSize(); 576 BaseTLB::Mode mode = BaseTLB::Write; 577 578 if (traceData) 579 traceData->setMem(addr, size, flags); 580 581 RequestPtr req = make_shared<Request>(asid, addr, size, flags, 582 dataMasterId(), pc, thread->contextId(), amo_op); 583 584 assert(req->hasAtomicOpFunctor()); 585 586 req->taskId(taskId()); 587 588 Addr split_addr = roundDown(addr + size - 1, block_size); 589 590 // AMO requests that access across a cache line boundary are not 591 // allowed since the cache does not guarantee AMO ops to be executed 592 // atomically in two cache lines 593 // For ISAs such as x86 that requires AMO operations to work on 594 // accesses that cross cache-line boundaries, the cache needs to be 595 // modified to support locking both cache lines to guarantee the 596 // atomicity. 597 if (split_addr > addr) { 598 panic("AMO requests should not access across a cache line boundary\n"); 599 } 600 601 _status = DTBWaitResponse; 602 603 WholeTranslationState *state = 604 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 605 DataTranslation<TimingSimpleCPU *> *translation 606 = new DataTranslation<TimingSimpleCPU *>(this, state); 607 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 608 609 return NoFault; 610} 611 612void 613TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 614{ 615 for (ThreadID tid = 0; tid < numThreads; tid++) { 616 if (tid != sender) { 617 if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 618 wakeup(tid); 619 } 620 TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 621 dcachePort.cacheBlockMask); 622 } 623 } 624} 625 626void 627TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 628{ 629 _status = BaseSimpleCPU::Running; 630 631 if (state->getFault() != NoFault) { 632 if (state->isPrefetch()) { 633 state->setNoFault(); 634 } 635 delete [] state->data; 636 state->deleteReqs(); 637 translationFault(state->getFault()); 638 } else { 639 if (!state->isSplit) { 640 sendData(state->mainReq, state->data, state->res, 641 state->mode == BaseTLB::Read); 642 } else { 643 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 644 state->data, state->mode == BaseTLB::Read); 645 } 646 } 647 648 delete state; 649} 650 651 652void 653TimingSimpleCPU::fetch() 654{ 655 // Change thread if multi-threaded 656 swapActiveThread(); 657 658 SimpleExecContext &t_info = *threadInfo[curThread]; 659 SimpleThread* thread = t_info.thread; 660 661 DPRINTF(SimpleCPU, "Fetch\n"); 662 663 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 664 checkForInterrupts(); 665 checkPcEventQueue(); 666 } 667 668 // We must have just got suspended by a PC event 669 if (_status == Idle) 670 return; 671 672 TheISA::PCState pcState = thread->pcState(); 673 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 674 !curMacroStaticInst; 675 676 if (needToFetch) { 677 _status = BaseSimpleCPU::Running; 678 RequestPtr ifetch_req = std::make_shared<Request>(); 679 ifetch_req->taskId(taskId()); 680 ifetch_req->setContext(thread->contextId()); 681 setupFetchRequest(ifetch_req); 682 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 683 thread->itb->translateTiming(ifetch_req, thread->getTC(), 684 &fetchTranslation, BaseTLB::Execute); 685 } else { 686 _status = IcacheWaitResponse; 687 completeIfetch(NULL); 688 689 updateCycleCounts(); 690 updateCycleCounters(BaseCPU::CPU_STATE_ON); 691 } 692} 693 694 695void 696TimingSimpleCPU::sendFetch(const Fault &fault, const RequestPtr &req, 697 ThreadContext *tc) 698{ 699 if (fault == NoFault) { 700 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 701 req->getVaddr(), req->getPaddr()); 702 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 703 ifetch_pkt->dataStatic(&inst); 704 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 705 706 if (!icachePort.sendTimingReq(ifetch_pkt)) { 707 // Need to wait for retry 708 _status = IcacheRetry; 709 } else { 710 // Need to wait for cache to respond 711 _status = IcacheWaitResponse; 712 // ownership of packet transferred to memory system 713 ifetch_pkt = NULL; 714 } 715 } else { 716 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 717 // fetch fault: advance directly to next instruction (fault handler) 718 _status = BaseSimpleCPU::Running; 719 advanceInst(fault); 720 } 721 722 updateCycleCounts(); 723 updateCycleCounters(BaseCPU::CPU_STATE_ON); 724} 725 726 727void 728TimingSimpleCPU::advanceInst(const Fault &fault) 729{ 730 SimpleExecContext &t_info = *threadInfo[curThread]; 731 732 if (_status == Faulting) 733 return; 734 735 if (fault != NoFault) { 736 DPRINTF(SimpleCPU, "Fault occured. Handling the fault\n"); 737 738 advancePC(fault); 739 740 // A syscall fault could suspend this CPU (e.g., futex_wait) 741 // If the _status is not Idle, schedule an event to fetch the next 742 // instruction after 'stall' ticks. 743 // If the cpu has been suspended (i.e., _status == Idle), another 744 // cpu will wake this cpu up later. 745 if (_status != Idle) { 746 DPRINTF(SimpleCPU, "Scheduling fetch event after the Fault\n"); 747 748 Tick stall = dynamic_pointer_cast<SyscallRetryFault>(fault) ? 749 clockEdge(syscallRetryLatency) : clockEdge(); 750 reschedule(fetchEvent, stall, true); 751 _status = Faulting; 752 } 753 754 return; 755 } 756 757 if (!t_info.stayAtPC) 758 advancePC(fault); 759 760 if (tryCompleteDrain()) 761 return; 762 763 if (_status == BaseSimpleCPU::Running) { 764 // kick off fetch of next instruction... callback from icache 765 // response will cause that instruction to be executed, 766 // keeping the CPU running. 767 fetch(); 768 } 769} 770 771 772void 773TimingSimpleCPU::completeIfetch(PacketPtr pkt) 774{ 775 SimpleExecContext& t_info = *threadInfo[curThread]; 776 777 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 778 pkt->getAddr() : 0); 779 780 // received a response from the icache: execute the received 781 // instruction 782 assert(!pkt || !pkt->isError()); 783 assert(_status == IcacheWaitResponse); 784 785 _status = BaseSimpleCPU::Running; 786 787 updateCycleCounts(); 788 updateCycleCounters(BaseCPU::CPU_STATE_ON); 789 790 if (pkt) 791 pkt->req->setAccessLatency(); 792 793 794 preExecute(); 795 if (curStaticInst && curStaticInst->isMemRef()) { 796 // load or store: just send to dcache 797 Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 798 799 // If we're not running now the instruction will complete in a dcache 800 // response callback or the instruction faulted and has started an 801 // ifetch 802 if (_status == BaseSimpleCPU::Running) { 803 if (fault != NoFault && traceData) { 804 // If there was a fault, we shouldn't trace this instruction. 805 delete traceData; 806 traceData = NULL; 807 } 808 809 postExecute(); 810 // @todo remove me after debugging with legion done 811 if (curStaticInst && (!curStaticInst->isMicroop() || 812 curStaticInst->isFirstMicroop())) 813 instCnt++; 814 advanceInst(fault); 815 } 816 } else if (curStaticInst) { 817 // non-memory instruction: execute completely now 818 Fault fault = curStaticInst->execute(&t_info, traceData); 819 820 // keep an instruction count 821 if (fault == NoFault) 822 countInst(); 823 else if (traceData && !DTRACE(ExecFaulting)) { 824 delete traceData; 825 traceData = NULL; 826 } 827 828 postExecute(); 829 // @todo remove me after debugging with legion done 830 if (curStaticInst && (!curStaticInst->isMicroop() || 831 curStaticInst->isFirstMicroop())) 832 instCnt++; 833 advanceInst(fault); 834 } else { 835 advanceInst(NoFault); 836 } 837 838 if (pkt) { 839 delete pkt; 840 } 841} 842 843void 844TimingSimpleCPU::IcachePort::ITickEvent::process() 845{ 846 cpu->completeIfetch(pkt); 847} 848 849bool 850TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 851{ 852 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 853 // we should only ever see one response per cycle since we only 854 // issue a new request once this response is sunk 855 assert(!tickEvent.scheduled()); 856 // delay processing of returned data until next CPU clock edge 857 tickEvent.schedule(pkt, cpu->clockEdge()); 858 859 return true; 860} 861 862void 863TimingSimpleCPU::IcachePort::recvReqRetry() 864{ 865 // we shouldn't get a retry unless we have a packet that we're 866 // waiting to transmit 867 assert(cpu->ifetch_pkt != NULL); 868 assert(cpu->_status == IcacheRetry); 869 PacketPtr tmp = cpu->ifetch_pkt; 870 if (sendTimingReq(tmp)) { 871 cpu->_status = IcacheWaitResponse; 872 cpu->ifetch_pkt = NULL; 873 } 874} 875 876void 877TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 878{ 879 // received a response from the dcache: complete the load or store 880 // instruction 881 assert(!pkt->isError()); 882 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 883 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 884 885 pkt->req->setAccessLatency(); 886 887 updateCycleCounts(); 888 updateCycleCounters(BaseCPU::CPU_STATE_ON); 889 890 if (pkt->senderState) { 891 SplitFragmentSenderState * send_state = 892 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 893 assert(send_state); 894 delete pkt; 895 PacketPtr big_pkt = send_state->bigPkt; 896 delete send_state; 897 898 SplitMainSenderState * main_send_state = 899 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 900 assert(main_send_state); 901 // Record the fact that this packet is no longer outstanding. 902 assert(main_send_state->outstanding != 0); 903 main_send_state->outstanding--; 904 905 if (main_send_state->outstanding) { 906 return; 907 } else { 908 delete main_send_state; 909 big_pkt->senderState = NULL; 910 pkt = big_pkt; 911 } 912 } 913 914 _status = BaseSimpleCPU::Running; 915 916 Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 917 traceData); 918 919 // keep an instruction count 920 if (fault == NoFault) 921 countInst(); 922 else if (traceData) { 923 // If there was a fault, we shouldn't trace this instruction. 924 delete traceData; 925 traceData = NULL; 926 } 927 928 delete pkt; 929 930 postExecute(); 931 932 advanceInst(fault); 933} 934 935void 936TimingSimpleCPU::updateCycleCounts() 937{ 938 const Cycles delta(curCycle() - previousCycle); 939 940 numCycles += delta; 941 942 previousCycle = curCycle(); 943} 944 945void 946TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 947{ 948 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 949 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 950 cpu->wakeup(tid); 951 } 952 } 953 954 // Making it uniform across all CPUs: 955 // The CPUs need to be woken up only on an invalidation packet (when using caches) 956 // or on an incoming write packet (when not using caches) 957 // It is not necessary to wake up the processor on all incoming packets 958 if (pkt->isInvalidate() || pkt->isWrite()) { 959 for (auto &t_info : cpu->threadInfo) { 960 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 961 } 962 } 963} 964 965void 966TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 967{ 968 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 969 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 970 cpu->wakeup(tid); 971 } 972 } 973} 974 975bool 976TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 977{ 978 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 979 980 // The timing CPU is not really ticked, instead it relies on the 981 // memory system (fetch and load/store) to set the pace. 982 if (!tickEvent.scheduled()) { 983 // Delay processing of returned data until next CPU clock edge 984 tickEvent.schedule(pkt, cpu->clockEdge()); 985 return true; 986 } else { 987 // In the case of a split transaction and a cache that is 988 // faster than a CPU we could get two responses in the 989 // same tick, delay the second one 990 if (!retryRespEvent.scheduled()) 991 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 992 return false; 993 } 994} 995 996void 997TimingSimpleCPU::DcachePort::DTickEvent::process() 998{ 999 cpu->completeDataAccess(pkt); 1000} 1001 1002void 1003TimingSimpleCPU::DcachePort::recvReqRetry() 1004{ 1005 // we shouldn't get a retry unless we have a packet that we're 1006 // waiting to transmit 1007 assert(cpu->dcache_pkt != NULL); 1008 assert(cpu->_status == DcacheRetry); 1009 PacketPtr tmp = cpu->dcache_pkt; 1010 if (tmp->senderState) { 1011 // This is a packet from a split access. 1012 SplitFragmentSenderState * send_state = 1013 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 1014 assert(send_state); 1015 PacketPtr big_pkt = send_state->bigPkt; 1016 1017 SplitMainSenderState * main_send_state = 1018 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 1019 assert(main_send_state); 1020 1021 if (sendTimingReq(tmp)) { 1022 // If we were able to send without retrying, record that fact 1023 // and try sending the other fragment. 1024 send_state->clearFromParent(); 1025 int other_index = main_send_state->getPendingFragment(); 1026 if (other_index > 0) { 1027 tmp = main_send_state->fragments[other_index]; 1028 cpu->dcache_pkt = tmp; 1029 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 1030 (big_pkt->isWrite() && cpu->handleWritePacket())) { 1031 main_send_state->fragments[other_index] = NULL; 1032 } 1033 } else { 1034 cpu->_status = DcacheWaitResponse; 1035 // memory system takes ownership of packet 1036 cpu->dcache_pkt = NULL; 1037 } 1038 } 1039 } else if (sendTimingReq(tmp)) { 1040 cpu->_status = DcacheWaitResponse; 1041 // memory system takes ownership of packet 1042 cpu->dcache_pkt = NULL; 1043 } 1044} 1045 1046TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 1047 Tick t) 1048 : pkt(_pkt), cpu(_cpu) 1049{ 1050 cpu->schedule(this, t); 1051} 1052 1053void 1054TimingSimpleCPU::IprEvent::process() 1055{ 1056 cpu->completeDataAccess(pkt); 1057} 1058 1059const char * 1060TimingSimpleCPU::IprEvent::description() const 1061{ 1062 return "Timing Simple CPU Delay IPR event"; 1063} 1064 1065 1066void 1067TimingSimpleCPU::printAddr(Addr a) 1068{ 1069 dcachePort.printAddr(a); 1070} 1071 1072 1073//////////////////////////////////////////////////////////////////////// 1074// 1075// TimingSimpleCPU Simulation Object 1076// 1077TimingSimpleCPU * 1078TimingSimpleCPUParams::create() 1079{ 1080 return new TimingSimpleCPU(this); 1081} 1082