timing.cc revision 12355:568ec3a0c614
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013,2015,2017 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "cpu/simple/timing.hh" 45 46#include "arch/locked_mem.hh" 47#include "arch/mmapped_ipr.hh" 48#include "arch/utility.hh" 49#include "base/bigint.hh" 50#include "config/the_isa.hh" 51#include "cpu/exetrace.hh" 52#include "debug/Config.hh" 53#include "debug/Drain.hh" 54#include "debug/ExecFaulting.hh" 55#include "debug/Mwait.hh" 56#include "debug/SimpleCPU.hh" 57#include "mem/packet.hh" 58#include "mem/packet_access.hh" 59#include "params/TimingSimpleCPU.hh" 60#include "sim/faults.hh" 61#include "sim/full_system.hh" 62#include "sim/system.hh" 63 64using namespace std; 65using namespace TheISA; 66 67void 68TimingSimpleCPU::init() 69{ 70 BaseSimpleCPU::init(); 71} 72 73void 74TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 75{ 76 pkt = _pkt; 77 cpu->schedule(this, t); 78} 79 80TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 81 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 82 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 83 fetchEvent([this]{ fetch(); }, name()) 84{ 85 _status = Idle; 86} 87 88 89 90TimingSimpleCPU::~TimingSimpleCPU() 91{ 92} 93 94DrainState 95TimingSimpleCPU::drain() 96{ 97 // Deschedule any power gating event (if any) 98 deschedulePowerGatingEvent(); 99 100 if (switchedOut()) 101 return DrainState::Drained; 102 103 if (_status == Idle || 104 (_status == BaseSimpleCPU::Running && isDrained())) { 105 DPRINTF(Drain, "No need to drain.\n"); 106 activeThreads.clear(); 107 return DrainState::Drained; 108 } else { 109 DPRINTF(Drain, "Requesting drain.\n"); 110 111 // The fetch event can become descheduled if a drain didn't 112 // succeed on the first attempt. We need to reschedule it if 113 // the CPU is waiting for a microcode routine to complete. 114 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 115 schedule(fetchEvent, clockEdge()); 116 117 return DrainState::Draining; 118 } 119} 120 121void 122TimingSimpleCPU::drainResume() 123{ 124 assert(!fetchEvent.scheduled()); 125 if (switchedOut()) 126 return; 127 128 DPRINTF(SimpleCPU, "Resume\n"); 129 verifyMemoryMode(); 130 131 assert(!threadContexts.empty()); 132 133 _status = BaseSimpleCPU::Idle; 134 135 for (ThreadID tid = 0; tid < numThreads; tid++) { 136 if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 137 threadInfo[tid]->notIdleFraction = 1; 138 139 activeThreads.push_back(tid); 140 141 _status = BaseSimpleCPU::Running; 142 143 // Fetch if any threads active 144 if (!fetchEvent.scheduled()) { 145 schedule(fetchEvent, nextCycle()); 146 } 147 } else { 148 threadInfo[tid]->notIdleFraction = 0; 149 } 150 } 151 152 // Reschedule any power gating event (if any) 153 schedulePowerGatingEvent(); 154 155 system->totalNumInsts = 0; 156} 157 158bool 159TimingSimpleCPU::tryCompleteDrain() 160{ 161 if (drainState() != DrainState::Draining) 162 return false; 163 164 DPRINTF(Drain, "tryCompleteDrain.\n"); 165 if (!isDrained()) 166 return false; 167 168 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 169 signalDrainDone(); 170 171 return true; 172} 173 174void 175TimingSimpleCPU::switchOut() 176{ 177 SimpleExecContext& t_info = *threadInfo[curThread]; 178 M5_VAR_USED SimpleThread* thread = t_info.thread; 179 180 BaseSimpleCPU::switchOut(); 181 182 assert(!fetchEvent.scheduled()); 183 assert(_status == BaseSimpleCPU::Running || _status == Idle); 184 assert(!t_info.stayAtPC); 185 assert(thread->microPC() == 0); 186 187 updateCycleCounts(); 188 updateCycleCounters(BaseCPU::CPU_STATE_ON); 189} 190 191 192void 193TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 194{ 195 BaseSimpleCPU::takeOverFrom(oldCPU); 196 197 previousCycle = curCycle(); 198} 199 200void 201TimingSimpleCPU::verifyMemoryMode() const 202{ 203 if (!system->isTimingMode()) { 204 fatal("The timing CPU requires the memory system to be in " 205 "'timing' mode.\n"); 206 } 207} 208 209void 210TimingSimpleCPU::activateContext(ThreadID thread_num) 211{ 212 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 213 214 assert(thread_num < numThreads); 215 216 threadInfo[thread_num]->notIdleFraction = 1; 217 if (_status == BaseSimpleCPU::Idle) 218 _status = BaseSimpleCPU::Running; 219 220 // kick things off by initiating the fetch of the next instruction 221 if (!fetchEvent.scheduled()) 222 schedule(fetchEvent, clockEdge(Cycles(0))); 223 224 if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 225 == activeThreads.end()) { 226 activeThreads.push_back(thread_num); 227 } 228 229 BaseCPU::activateContext(thread_num); 230} 231 232 233void 234TimingSimpleCPU::suspendContext(ThreadID thread_num) 235{ 236 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 237 238 assert(thread_num < numThreads); 239 activeThreads.remove(thread_num); 240 241 if (_status == Idle) 242 return; 243 244 assert(_status == BaseSimpleCPU::Running); 245 246 threadInfo[thread_num]->notIdleFraction = 0; 247 248 if (activeThreads.empty()) { 249 _status = Idle; 250 251 if (fetchEvent.scheduled()) { 252 deschedule(fetchEvent); 253 } 254 } 255 256 BaseCPU::suspendContext(thread_num); 257} 258 259bool 260TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 261{ 262 SimpleExecContext &t_info = *threadInfo[curThread]; 263 SimpleThread* thread = t_info.thread; 264 265 RequestPtr req = pkt->req; 266 267 // We're about the issues a locked load, so tell the monitor 268 // to start caring about this address 269 if (pkt->isRead() && pkt->req->isLLSC()) { 270 TheISA::handleLockedRead(thread, pkt->req); 271 } 272 if (req->isMmappedIpr()) { 273 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 274 new IprEvent(pkt, this, clockEdge(delay)); 275 _status = DcacheWaitResponse; 276 dcache_pkt = NULL; 277 } else if (!dcachePort.sendTimingReq(pkt)) { 278 _status = DcacheRetry; 279 dcache_pkt = pkt; 280 } else { 281 _status = DcacheWaitResponse; 282 // memory system takes ownership of packet 283 dcache_pkt = NULL; 284 } 285 return dcache_pkt == NULL; 286} 287 288void 289TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 290 bool read) 291{ 292 SimpleExecContext &t_info = *threadInfo[curThread]; 293 SimpleThread* thread = t_info.thread; 294 295 PacketPtr pkt = buildPacket(req, read); 296 pkt->dataDynamic<uint8_t>(data); 297 if (req->getFlags().isSet(Request::NO_ACCESS)) { 298 assert(!dcache_pkt); 299 pkt->makeResponse(); 300 completeDataAccess(pkt); 301 } else if (read) { 302 handleReadPacket(pkt); 303 } else { 304 bool do_access = true; // flag to suppress cache access 305 306 if (req->isLLSC()) { 307 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 308 } else if (req->isCondSwap()) { 309 assert(res); 310 req->setExtraData(*res); 311 } 312 313 if (do_access) { 314 dcache_pkt = pkt; 315 handleWritePacket(); 316 threadSnoop(pkt, curThread); 317 } else { 318 _status = DcacheWaitResponse; 319 completeDataAccess(pkt); 320 } 321 } 322} 323 324void 325TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 326 RequestPtr req, uint8_t *data, bool read) 327{ 328 PacketPtr pkt1, pkt2; 329 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 330 if (req->getFlags().isSet(Request::NO_ACCESS)) { 331 assert(!dcache_pkt); 332 pkt1->makeResponse(); 333 completeDataAccess(pkt1); 334 } else if (read) { 335 SplitFragmentSenderState * send_state = 336 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 337 if (handleReadPacket(pkt1)) { 338 send_state->clearFromParent(); 339 send_state = dynamic_cast<SplitFragmentSenderState *>( 340 pkt2->senderState); 341 if (handleReadPacket(pkt2)) { 342 send_state->clearFromParent(); 343 } 344 } 345 } else { 346 dcache_pkt = pkt1; 347 SplitFragmentSenderState * send_state = 348 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 349 if (handleWritePacket()) { 350 send_state->clearFromParent(); 351 dcache_pkt = pkt2; 352 send_state = dynamic_cast<SplitFragmentSenderState *>( 353 pkt2->senderState); 354 if (handleWritePacket()) { 355 send_state->clearFromParent(); 356 } 357 } 358 } 359} 360 361void 362TimingSimpleCPU::translationFault(const Fault &fault) 363{ 364 // fault may be NoFault in cases where a fault is suppressed, 365 // for instance prefetches. 366 updateCycleCounts(); 367 updateCycleCounters(BaseCPU::CPU_STATE_ON); 368 369 if (traceData) { 370 // Since there was a fault, we shouldn't trace this instruction. 371 delete traceData; 372 traceData = NULL; 373 } 374 375 postExecute(); 376 377 advanceInst(fault); 378} 379 380PacketPtr 381TimingSimpleCPU::buildPacket(RequestPtr req, bool read) 382{ 383 return read ? Packet::createRead(req) : Packet::createWrite(req); 384} 385 386void 387TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 388 RequestPtr req1, RequestPtr req2, RequestPtr req, 389 uint8_t *data, bool read) 390{ 391 pkt1 = pkt2 = NULL; 392 393 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 394 395 if (req->getFlags().isSet(Request::NO_ACCESS)) { 396 pkt1 = buildPacket(req, read); 397 return; 398 } 399 400 pkt1 = buildPacket(req1, read); 401 pkt2 = buildPacket(req2, read); 402 403 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 404 405 pkt->dataDynamic<uint8_t>(data); 406 pkt1->dataStatic<uint8_t>(data); 407 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 408 409 SplitMainSenderState * main_send_state = new SplitMainSenderState; 410 pkt->senderState = main_send_state; 411 main_send_state->fragments[0] = pkt1; 412 main_send_state->fragments[1] = pkt2; 413 main_send_state->outstanding = 2; 414 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 415 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 416} 417 418Fault 419TimingSimpleCPU::readMem(Addr addr, uint8_t *data, 420 unsigned size, Request::Flags flags) 421{ 422 panic("readMem() is for atomic accesses, and should " 423 "never be called on TimingSimpleCPU.\n"); 424} 425 426Fault 427TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, 428 Request::Flags flags) 429{ 430 SimpleExecContext &t_info = *threadInfo[curThread]; 431 SimpleThread* thread = t_info.thread; 432 433 Fault fault; 434 const int asid = 0; 435 const Addr pc = thread->instAddr(); 436 unsigned block_size = cacheLineSize(); 437 BaseTLB::Mode mode = BaseTLB::Read; 438 439 if (traceData) 440 traceData->setMem(addr, size, flags); 441 442 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 443 thread->contextId()); 444 445 req->taskId(taskId()); 446 447 Addr split_addr = roundDown(addr + size - 1, block_size); 448 assert(split_addr <= addr || split_addr - addr < block_size); 449 450 _status = DTBWaitResponse; 451 if (split_addr > addr) { 452 RequestPtr req1, req2; 453 assert(!req->isLLSC() && !req->isSwap()); 454 req->splitOnVaddr(split_addr, req1, req2); 455 456 WholeTranslationState *state = 457 new WholeTranslationState(req, req1, req2, new uint8_t[size], 458 NULL, mode); 459 DataTranslation<TimingSimpleCPU *> *trans1 = 460 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 461 DataTranslation<TimingSimpleCPU *> *trans2 = 462 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 463 464 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 465 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 466 } else { 467 WholeTranslationState *state = 468 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 469 DataTranslation<TimingSimpleCPU *> *translation 470 = new DataTranslation<TimingSimpleCPU *>(this, state); 471 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 472 } 473 474 return NoFault; 475} 476 477bool 478TimingSimpleCPU::handleWritePacket() 479{ 480 SimpleExecContext &t_info = *threadInfo[curThread]; 481 SimpleThread* thread = t_info.thread; 482 483 RequestPtr req = dcache_pkt->req; 484 if (req->isMmappedIpr()) { 485 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 486 new IprEvent(dcache_pkt, this, clockEdge(delay)); 487 _status = DcacheWaitResponse; 488 dcache_pkt = NULL; 489 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 490 _status = DcacheRetry; 491 } else { 492 _status = DcacheWaitResponse; 493 // memory system takes ownership of packet 494 dcache_pkt = NULL; 495 } 496 return dcache_pkt == NULL; 497} 498 499Fault 500TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 501 Addr addr, Request::Flags flags, uint64_t *res) 502{ 503 SimpleExecContext &t_info = *threadInfo[curThread]; 504 SimpleThread* thread = t_info.thread; 505 506 uint8_t *newData = new uint8_t[size]; 507 const int asid = 0; 508 const Addr pc = thread->instAddr(); 509 unsigned block_size = cacheLineSize(); 510 BaseTLB::Mode mode = BaseTLB::Write; 511 512 if (data == NULL) { 513 assert(flags & Request::STORE_NO_DATA); 514 // This must be a cache block cleaning request 515 memset(newData, 0, size); 516 } else { 517 memcpy(newData, data, size); 518 } 519 520 if (traceData) 521 traceData->setMem(addr, size, flags); 522 523 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 524 thread->contextId()); 525 526 req->taskId(taskId()); 527 528 Addr split_addr = roundDown(addr + size - 1, block_size); 529 assert(split_addr <= addr || split_addr - addr < block_size); 530 531 _status = DTBWaitResponse; 532 if (split_addr > addr) { 533 RequestPtr req1, req2; 534 assert(!req->isLLSC() && !req->isSwap()); 535 req->splitOnVaddr(split_addr, req1, req2); 536 537 WholeTranslationState *state = 538 new WholeTranslationState(req, req1, req2, newData, res, mode); 539 DataTranslation<TimingSimpleCPU *> *trans1 = 540 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 541 DataTranslation<TimingSimpleCPU *> *trans2 = 542 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 543 544 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 545 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 546 } else { 547 WholeTranslationState *state = 548 new WholeTranslationState(req, newData, res, mode); 549 DataTranslation<TimingSimpleCPU *> *translation = 550 new DataTranslation<TimingSimpleCPU *>(this, state); 551 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 552 } 553 554 // Translation faults will be returned via finishTranslation() 555 return NoFault; 556} 557 558void 559TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 560{ 561 for (ThreadID tid = 0; tid < numThreads; tid++) { 562 if (tid != sender) { 563 if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 564 wakeup(tid); 565 } 566 TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 567 dcachePort.cacheBlockMask); 568 } 569 } 570} 571 572void 573TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 574{ 575 _status = BaseSimpleCPU::Running; 576 577 if (state->getFault() != NoFault) { 578 if (state->isPrefetch()) { 579 state->setNoFault(); 580 } 581 delete [] state->data; 582 state->deleteReqs(); 583 translationFault(state->getFault()); 584 } else { 585 if (!state->isSplit) { 586 sendData(state->mainReq, state->data, state->res, 587 state->mode == BaseTLB::Read); 588 } else { 589 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 590 state->data, state->mode == BaseTLB::Read); 591 } 592 } 593 594 delete state; 595} 596 597 598void 599TimingSimpleCPU::fetch() 600{ 601 // Change thread if multi-threaded 602 swapActiveThread(); 603 604 SimpleExecContext &t_info = *threadInfo[curThread]; 605 SimpleThread* thread = t_info.thread; 606 607 DPRINTF(SimpleCPU, "Fetch\n"); 608 609 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 610 checkForInterrupts(); 611 checkPcEventQueue(); 612 } 613 614 // We must have just got suspended by a PC event 615 if (_status == Idle) 616 return; 617 618 TheISA::PCState pcState = thread->pcState(); 619 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 620 !curMacroStaticInst; 621 622 if (needToFetch) { 623 _status = BaseSimpleCPU::Running; 624 Request *ifetch_req = new Request(); 625 ifetch_req->taskId(taskId()); 626 ifetch_req->setContext(thread->contextId()); 627 setupFetchRequest(ifetch_req); 628 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 629 thread->itb->translateTiming(ifetch_req, thread->getTC(), 630 &fetchTranslation, BaseTLB::Execute); 631 } else { 632 _status = IcacheWaitResponse; 633 completeIfetch(NULL); 634 635 updateCycleCounts(); 636 updateCycleCounters(BaseCPU::CPU_STATE_ON); 637 } 638} 639 640 641void 642TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 643 ThreadContext *tc) 644{ 645 if (fault == NoFault) { 646 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 647 req->getVaddr(), req->getPaddr()); 648 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 649 ifetch_pkt->dataStatic(&inst); 650 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 651 652 if (!icachePort.sendTimingReq(ifetch_pkt)) { 653 // Need to wait for retry 654 _status = IcacheRetry; 655 } else { 656 // Need to wait for cache to respond 657 _status = IcacheWaitResponse; 658 // ownership of packet transferred to memory system 659 ifetch_pkt = NULL; 660 } 661 } else { 662 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 663 delete req; 664 // fetch fault: advance directly to next instruction (fault handler) 665 _status = BaseSimpleCPU::Running; 666 advanceInst(fault); 667 } 668 669 updateCycleCounts(); 670 updateCycleCounters(BaseCPU::CPU_STATE_ON); 671} 672 673 674void 675TimingSimpleCPU::advanceInst(const Fault &fault) 676{ 677 SimpleExecContext &t_info = *threadInfo[curThread]; 678 679 if (_status == Faulting) 680 return; 681 682 if (fault != NoFault) { 683 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 684 685 advancePC(fault); 686 687 Tick stall = dynamic_pointer_cast<SyscallRetryFault>(fault) ? 688 clockEdge(syscallRetryLatency) : clockEdge(); 689 690 reschedule(fetchEvent, stall, true); 691 692 _status = Faulting; 693 return; 694 } 695 696 697 if (!t_info.stayAtPC) 698 advancePC(fault); 699 700 if (tryCompleteDrain()) 701 return; 702 703 if (_status == BaseSimpleCPU::Running) { 704 // kick off fetch of next instruction... callback from icache 705 // response will cause that instruction to be executed, 706 // keeping the CPU running. 707 fetch(); 708 } 709} 710 711 712void 713TimingSimpleCPU::completeIfetch(PacketPtr pkt) 714{ 715 SimpleExecContext& t_info = *threadInfo[curThread]; 716 717 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 718 pkt->getAddr() : 0); 719 720 // received a response from the icache: execute the received 721 // instruction 722 assert(!pkt || !pkt->isError()); 723 assert(_status == IcacheWaitResponse); 724 725 _status = BaseSimpleCPU::Running; 726 727 updateCycleCounts(); 728 updateCycleCounters(BaseCPU::CPU_STATE_ON); 729 730 if (pkt) 731 pkt->req->setAccessLatency(); 732 733 734 preExecute(); 735 if (curStaticInst && curStaticInst->isMemRef()) { 736 // load or store: just send to dcache 737 Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 738 739 // If we're not running now the instruction will complete in a dcache 740 // response callback or the instruction faulted and has started an 741 // ifetch 742 if (_status == BaseSimpleCPU::Running) { 743 if (fault != NoFault && traceData) { 744 // If there was a fault, we shouldn't trace this instruction. 745 delete traceData; 746 traceData = NULL; 747 } 748 749 postExecute(); 750 // @todo remove me after debugging with legion done 751 if (curStaticInst && (!curStaticInst->isMicroop() || 752 curStaticInst->isFirstMicroop())) 753 instCnt++; 754 advanceInst(fault); 755 } 756 } else if (curStaticInst) { 757 // non-memory instruction: execute completely now 758 Fault fault = curStaticInst->execute(&t_info, traceData); 759 760 // keep an instruction count 761 if (fault == NoFault) 762 countInst(); 763 else if (traceData && !DTRACE(ExecFaulting)) { 764 delete traceData; 765 traceData = NULL; 766 } 767 768 postExecute(); 769 // @todo remove me after debugging with legion done 770 if (curStaticInst && (!curStaticInst->isMicroop() || 771 curStaticInst->isFirstMicroop())) 772 instCnt++; 773 advanceInst(fault); 774 } else { 775 advanceInst(NoFault); 776 } 777 778 if (pkt) { 779 delete pkt->req; 780 delete pkt; 781 } 782} 783 784void 785TimingSimpleCPU::IcachePort::ITickEvent::process() 786{ 787 cpu->completeIfetch(pkt); 788} 789 790bool 791TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 792{ 793 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 794 // we should only ever see one response per cycle since we only 795 // issue a new request once this response is sunk 796 assert(!tickEvent.scheduled()); 797 // delay processing of returned data until next CPU clock edge 798 tickEvent.schedule(pkt, cpu->clockEdge()); 799 800 return true; 801} 802 803void 804TimingSimpleCPU::IcachePort::recvReqRetry() 805{ 806 // we shouldn't get a retry unless we have a packet that we're 807 // waiting to transmit 808 assert(cpu->ifetch_pkt != NULL); 809 assert(cpu->_status == IcacheRetry); 810 PacketPtr tmp = cpu->ifetch_pkt; 811 if (sendTimingReq(tmp)) { 812 cpu->_status = IcacheWaitResponse; 813 cpu->ifetch_pkt = NULL; 814 } 815} 816 817void 818TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 819{ 820 // received a response from the dcache: complete the load or store 821 // instruction 822 assert(!pkt->isError()); 823 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 824 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 825 826 pkt->req->setAccessLatency(); 827 828 updateCycleCounts(); 829 updateCycleCounters(BaseCPU::CPU_STATE_ON); 830 831 if (pkt->senderState) { 832 SplitFragmentSenderState * send_state = 833 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 834 assert(send_state); 835 delete pkt->req; 836 delete pkt; 837 PacketPtr big_pkt = send_state->bigPkt; 838 delete send_state; 839 840 SplitMainSenderState * main_send_state = 841 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 842 assert(main_send_state); 843 // Record the fact that this packet is no longer outstanding. 844 assert(main_send_state->outstanding != 0); 845 main_send_state->outstanding--; 846 847 if (main_send_state->outstanding) { 848 return; 849 } else { 850 delete main_send_state; 851 big_pkt->senderState = NULL; 852 pkt = big_pkt; 853 } 854 } 855 856 _status = BaseSimpleCPU::Running; 857 858 Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 859 traceData); 860 861 // keep an instruction count 862 if (fault == NoFault) 863 countInst(); 864 else if (traceData) { 865 // If there was a fault, we shouldn't trace this instruction. 866 delete traceData; 867 traceData = NULL; 868 } 869 870 delete pkt->req; 871 delete pkt; 872 873 postExecute(); 874 875 advanceInst(fault); 876} 877 878void 879TimingSimpleCPU::updateCycleCounts() 880{ 881 const Cycles delta(curCycle() - previousCycle); 882 883 numCycles += delta; 884 885 previousCycle = curCycle(); 886} 887 888void 889TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 890{ 891 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 892 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 893 cpu->wakeup(tid); 894 } 895 } 896 897 // Making it uniform across all CPUs: 898 // The CPUs need to be woken up only on an invalidation packet (when using caches) 899 // or on an incoming write packet (when not using caches) 900 // It is not necessary to wake up the processor on all incoming packets 901 if (pkt->isInvalidate() || pkt->isWrite()) { 902 for (auto &t_info : cpu->threadInfo) { 903 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 904 } 905 } 906} 907 908void 909TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 910{ 911 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 912 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 913 cpu->wakeup(tid); 914 } 915 } 916} 917 918bool 919TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 920{ 921 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 922 923 // The timing CPU is not really ticked, instead it relies on the 924 // memory system (fetch and load/store) to set the pace. 925 if (!tickEvent.scheduled()) { 926 // Delay processing of returned data until next CPU clock edge 927 tickEvent.schedule(pkt, cpu->clockEdge()); 928 return true; 929 } else { 930 // In the case of a split transaction and a cache that is 931 // faster than a CPU we could get two responses in the 932 // same tick, delay the second one 933 if (!retryRespEvent.scheduled()) 934 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 935 return false; 936 } 937} 938 939void 940TimingSimpleCPU::DcachePort::DTickEvent::process() 941{ 942 cpu->completeDataAccess(pkt); 943} 944 945void 946TimingSimpleCPU::DcachePort::recvReqRetry() 947{ 948 // we shouldn't get a retry unless we have a packet that we're 949 // waiting to transmit 950 assert(cpu->dcache_pkt != NULL); 951 assert(cpu->_status == DcacheRetry); 952 PacketPtr tmp = cpu->dcache_pkt; 953 if (tmp->senderState) { 954 // This is a packet from a split access. 955 SplitFragmentSenderState * send_state = 956 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 957 assert(send_state); 958 PacketPtr big_pkt = send_state->bigPkt; 959 960 SplitMainSenderState * main_send_state = 961 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 962 assert(main_send_state); 963 964 if (sendTimingReq(tmp)) { 965 // If we were able to send without retrying, record that fact 966 // and try sending the other fragment. 967 send_state->clearFromParent(); 968 int other_index = main_send_state->getPendingFragment(); 969 if (other_index > 0) { 970 tmp = main_send_state->fragments[other_index]; 971 cpu->dcache_pkt = tmp; 972 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 973 (big_pkt->isWrite() && cpu->handleWritePacket())) { 974 main_send_state->fragments[other_index] = NULL; 975 } 976 } else { 977 cpu->_status = DcacheWaitResponse; 978 // memory system takes ownership of packet 979 cpu->dcache_pkt = NULL; 980 } 981 } 982 } else if (sendTimingReq(tmp)) { 983 cpu->_status = DcacheWaitResponse; 984 // memory system takes ownership of packet 985 cpu->dcache_pkt = NULL; 986 } 987} 988 989TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 990 Tick t) 991 : pkt(_pkt), cpu(_cpu) 992{ 993 cpu->schedule(this, t); 994} 995 996void 997TimingSimpleCPU::IprEvent::process() 998{ 999 cpu->completeDataAccess(pkt); 1000} 1001 1002const char * 1003TimingSimpleCPU::IprEvent::description() const 1004{ 1005 return "Timing Simple CPU Delay IPR event"; 1006} 1007 1008 1009void 1010TimingSimpleCPU::printAddr(Addr a) 1011{ 1012 dcachePort.printAddr(a); 1013} 1014 1015 1016//////////////////////////////////////////////////////////////////////// 1017// 1018// TimingSimpleCPU Simulation Object 1019// 1020TimingSimpleCPU * 1021TimingSimpleCPUParams::create() 1022{ 1023 return new TimingSimpleCPU(this); 1024} 1025