timing.cc revision 11526:5b81895e5d5e
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013,2015 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/locked_mem.hh" 45#include "arch/mmapped_ipr.hh" 46#include "arch/utility.hh" 47#include "base/bigint.hh" 48#include "config/the_isa.hh" 49#include "cpu/simple/timing.hh" 50#include "cpu/exetrace.hh" 51#include "debug/Config.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/SimpleCPU.hh" 55#include "mem/packet.hh" 56#include "mem/packet_access.hh" 57#include "params/TimingSimpleCPU.hh" 58#include "sim/faults.hh" 59#include "sim/full_system.hh" 60#include "sim/system.hh" 61 62#include "debug/Mwait.hh" 63 64using namespace std; 65using namespace TheISA; 66 67void 68TimingSimpleCPU::init() 69{ 70 BaseSimpleCPU::init(); 71} 72 73void 74TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 75{ 76 pkt = _pkt; 77 cpu->schedule(this, t); 78} 79 80TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 81 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 82 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 83 fetchEvent(this) 84{ 85 _status = Idle; 86} 87 88 89 90TimingSimpleCPU::~TimingSimpleCPU() 91{ 92} 93 94DrainState 95TimingSimpleCPU::drain() 96{ 97 if (switchedOut()) 98 return DrainState::Drained; 99 100 if (_status == Idle || 101 (_status == BaseSimpleCPU::Running && isDrained())) { 102 DPRINTF(Drain, "No need to drain.\n"); 103 activeThreads.clear(); 104 return DrainState::Drained; 105 } else { 106 DPRINTF(Drain, "Requesting drain.\n"); 107 108 // The fetch event can become descheduled if a drain didn't 109 // succeed on the first attempt. We need to reschedule it if 110 // the CPU is waiting for a microcode routine to complete. 111 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 112 schedule(fetchEvent, clockEdge()); 113 114 return DrainState::Draining; 115 } 116} 117 118void 119TimingSimpleCPU::drainResume() 120{ 121 assert(!fetchEvent.scheduled()); 122 if (switchedOut()) 123 return; 124 125 DPRINTF(SimpleCPU, "Resume\n"); 126 verifyMemoryMode(); 127 128 assert(!threadContexts.empty()); 129 130 _status = BaseSimpleCPU::Idle; 131 132 for (ThreadID tid = 0; tid < numThreads; tid++) { 133 if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 134 threadInfo[tid]->notIdleFraction = 1; 135 136 activeThreads.push_back(tid); 137 138 _status = BaseSimpleCPU::Running; 139 140 // Fetch if any threads active 141 if (!fetchEvent.scheduled()) { 142 schedule(fetchEvent, nextCycle()); 143 } 144 } else { 145 threadInfo[tid]->notIdleFraction = 0; 146 } 147 } 148 149 system->totalNumInsts = 0; 150} 151 152bool 153TimingSimpleCPU::tryCompleteDrain() 154{ 155 if (drainState() != DrainState::Draining) 156 return false; 157 158 DPRINTF(Drain, "tryCompleteDrain.\n"); 159 if (!isDrained()) 160 return false; 161 162 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 163 signalDrainDone(); 164 165 return true; 166} 167 168void 169TimingSimpleCPU::switchOut() 170{ 171 SimpleExecContext& t_info = *threadInfo[curThread]; 172 M5_VAR_USED SimpleThread* thread = t_info.thread; 173 174 BaseSimpleCPU::switchOut(); 175 176 assert(!fetchEvent.scheduled()); 177 assert(_status == BaseSimpleCPU::Running || _status == Idle); 178 assert(!t_info.stayAtPC); 179 assert(thread->microPC() == 0); 180 181 updateCycleCounts(); 182} 183 184 185void 186TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 187{ 188 BaseSimpleCPU::takeOverFrom(oldCPU); 189 190 previousCycle = curCycle(); 191} 192 193void 194TimingSimpleCPU::verifyMemoryMode() const 195{ 196 if (!system->isTimingMode()) { 197 fatal("The timing CPU requires the memory system to be in " 198 "'timing' mode.\n"); 199 } 200} 201 202void 203TimingSimpleCPU::activateContext(ThreadID thread_num) 204{ 205 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 206 207 assert(thread_num < numThreads); 208 209 threadInfo[thread_num]->notIdleFraction = 1; 210 if (_status == BaseSimpleCPU::Idle) 211 _status = BaseSimpleCPU::Running; 212 213 // kick things off by initiating the fetch of the next instruction 214 if (!fetchEvent.scheduled()) 215 schedule(fetchEvent, clockEdge(Cycles(0))); 216 217 if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 218 == activeThreads.end()) { 219 activeThreads.push_back(thread_num); 220 } 221 222 BaseCPU::activateContext(thread_num); 223} 224 225 226void 227TimingSimpleCPU::suspendContext(ThreadID thread_num) 228{ 229 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 230 231 assert(thread_num < numThreads); 232 activeThreads.remove(thread_num); 233 234 if (_status == Idle) 235 return; 236 237 assert(_status == BaseSimpleCPU::Running); 238 239 threadInfo[thread_num]->notIdleFraction = 0; 240 241 if (activeThreads.empty()) { 242 _status = Idle; 243 244 if (fetchEvent.scheduled()) { 245 deschedule(fetchEvent); 246 } 247 } 248 249 BaseCPU::suspendContext(thread_num); 250} 251 252bool 253TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 254{ 255 SimpleExecContext &t_info = *threadInfo[curThread]; 256 SimpleThread* thread = t_info.thread; 257 258 RequestPtr req = pkt->req; 259 260 // We're about the issues a locked load, so tell the monitor 261 // to start caring about this address 262 if (pkt->isRead() && pkt->req->isLLSC()) { 263 TheISA::handleLockedRead(thread, pkt->req); 264 } 265 if (req->isMmappedIpr()) { 266 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 267 new IprEvent(pkt, this, clockEdge(delay)); 268 _status = DcacheWaitResponse; 269 dcache_pkt = NULL; 270 } else if (!dcachePort.sendTimingReq(pkt)) { 271 _status = DcacheRetry; 272 dcache_pkt = pkt; 273 } else { 274 _status = DcacheWaitResponse; 275 // memory system takes ownership of packet 276 dcache_pkt = NULL; 277 } 278 return dcache_pkt == NULL; 279} 280 281void 282TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 283 bool read) 284{ 285 SimpleExecContext &t_info = *threadInfo[curThread]; 286 SimpleThread* thread = t_info.thread; 287 288 PacketPtr pkt = buildPacket(req, read); 289 pkt->dataDynamic<uint8_t>(data); 290 if (req->getFlags().isSet(Request::NO_ACCESS)) { 291 assert(!dcache_pkt); 292 pkt->makeResponse(); 293 completeDataAccess(pkt); 294 } else if (read) { 295 handleReadPacket(pkt); 296 } else { 297 bool do_access = true; // flag to suppress cache access 298 299 if (req->isLLSC()) { 300 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 301 } else if (req->isCondSwap()) { 302 assert(res); 303 req->setExtraData(*res); 304 } 305 306 if (do_access) { 307 dcache_pkt = pkt; 308 handleWritePacket(); 309 threadSnoop(pkt, curThread); 310 } else { 311 _status = DcacheWaitResponse; 312 completeDataAccess(pkt); 313 } 314 } 315} 316 317void 318TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 319 RequestPtr req, uint8_t *data, bool read) 320{ 321 PacketPtr pkt1, pkt2; 322 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 323 if (req->getFlags().isSet(Request::NO_ACCESS)) { 324 assert(!dcache_pkt); 325 pkt1->makeResponse(); 326 completeDataAccess(pkt1); 327 } else if (read) { 328 SplitFragmentSenderState * send_state = 329 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 330 if (handleReadPacket(pkt1)) { 331 send_state->clearFromParent(); 332 send_state = dynamic_cast<SplitFragmentSenderState *>( 333 pkt2->senderState); 334 if (handleReadPacket(pkt2)) { 335 send_state->clearFromParent(); 336 } 337 } 338 } else { 339 dcache_pkt = pkt1; 340 SplitFragmentSenderState * send_state = 341 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 342 if (handleWritePacket()) { 343 send_state->clearFromParent(); 344 dcache_pkt = pkt2; 345 send_state = dynamic_cast<SplitFragmentSenderState *>( 346 pkt2->senderState); 347 if (handleWritePacket()) { 348 send_state->clearFromParent(); 349 } 350 } 351 } 352} 353 354void 355TimingSimpleCPU::translationFault(const Fault &fault) 356{ 357 // fault may be NoFault in cases where a fault is suppressed, 358 // for instance prefetches. 359 updateCycleCounts(); 360 361 if (traceData) { 362 // Since there was a fault, we shouldn't trace this instruction. 363 delete traceData; 364 traceData = NULL; 365 } 366 367 postExecute(); 368 369 advanceInst(fault); 370} 371 372PacketPtr 373TimingSimpleCPU::buildPacket(RequestPtr req, bool read) 374{ 375 return read ? Packet::createRead(req) : Packet::createWrite(req); 376} 377 378void 379TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 380 RequestPtr req1, RequestPtr req2, RequestPtr req, 381 uint8_t *data, bool read) 382{ 383 pkt1 = pkt2 = NULL; 384 385 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 386 387 if (req->getFlags().isSet(Request::NO_ACCESS)) { 388 pkt1 = buildPacket(req, read); 389 return; 390 } 391 392 pkt1 = buildPacket(req1, read); 393 pkt2 = buildPacket(req2, read); 394 395 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 396 397 pkt->dataDynamic<uint8_t>(data); 398 pkt1->dataStatic<uint8_t>(data); 399 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 400 401 SplitMainSenderState * main_send_state = new SplitMainSenderState; 402 pkt->senderState = main_send_state; 403 main_send_state->fragments[0] = pkt1; 404 main_send_state->fragments[1] = pkt2; 405 main_send_state->outstanding = 2; 406 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 407 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 408} 409 410Fault 411TimingSimpleCPU::readMem(Addr addr, uint8_t *data, 412 unsigned size, unsigned flags) 413{ 414 panic("readMem() is for atomic accesses, and should " 415 "never be called on TimingSimpleCPU.\n"); 416} 417 418Fault 419TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags) 420{ 421 SimpleExecContext &t_info = *threadInfo[curThread]; 422 SimpleThread* thread = t_info.thread; 423 424 Fault fault; 425 const int asid = 0; 426 const Addr pc = thread->instAddr(); 427 unsigned block_size = cacheLineSize(); 428 BaseTLB::Mode mode = BaseTLB::Read; 429 430 if (traceData) 431 traceData->setMem(addr, size, flags); 432 433 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 434 thread->contextId()); 435 436 req->taskId(taskId()); 437 438 Addr split_addr = roundDown(addr + size - 1, block_size); 439 assert(split_addr <= addr || split_addr - addr < block_size); 440 441 _status = DTBWaitResponse; 442 if (split_addr > addr) { 443 RequestPtr req1, req2; 444 assert(!req->isLLSC() && !req->isSwap()); 445 req->splitOnVaddr(split_addr, req1, req2); 446 447 WholeTranslationState *state = 448 new WholeTranslationState(req, req1, req2, new uint8_t[size], 449 NULL, mode); 450 DataTranslation<TimingSimpleCPU *> *trans1 = 451 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 452 DataTranslation<TimingSimpleCPU *> *trans2 = 453 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 454 455 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 456 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 457 } else { 458 WholeTranslationState *state = 459 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 460 DataTranslation<TimingSimpleCPU *> *translation 461 = new DataTranslation<TimingSimpleCPU *>(this, state); 462 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 463 } 464 465 return NoFault; 466} 467 468bool 469TimingSimpleCPU::handleWritePacket() 470{ 471 SimpleExecContext &t_info = *threadInfo[curThread]; 472 SimpleThread* thread = t_info.thread; 473 474 RequestPtr req = dcache_pkt->req; 475 if (req->isMmappedIpr()) { 476 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 477 new IprEvent(dcache_pkt, this, clockEdge(delay)); 478 _status = DcacheWaitResponse; 479 dcache_pkt = NULL; 480 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 481 _status = DcacheRetry; 482 } else { 483 _status = DcacheWaitResponse; 484 // memory system takes ownership of packet 485 dcache_pkt = NULL; 486 } 487 return dcache_pkt == NULL; 488} 489 490Fault 491TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 492 Addr addr, unsigned flags, uint64_t *res) 493{ 494 SimpleExecContext &t_info = *threadInfo[curThread]; 495 SimpleThread* thread = t_info.thread; 496 497 uint8_t *newData = new uint8_t[size]; 498 const int asid = 0; 499 const Addr pc = thread->instAddr(); 500 unsigned block_size = cacheLineSize(); 501 BaseTLB::Mode mode = BaseTLB::Write; 502 503 if (data == NULL) { 504 assert(flags & Request::CACHE_BLOCK_ZERO); 505 // This must be a cache block cleaning request 506 memset(newData, 0, size); 507 } else { 508 memcpy(newData, data, size); 509 } 510 511 if (traceData) 512 traceData->setMem(addr, size, flags); 513 514 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 515 thread->contextId()); 516 517 req->taskId(taskId()); 518 519 Addr split_addr = roundDown(addr + size - 1, block_size); 520 assert(split_addr <= addr || split_addr - addr < block_size); 521 522 _status = DTBWaitResponse; 523 if (split_addr > addr) { 524 RequestPtr req1, req2; 525 assert(!req->isLLSC() && !req->isSwap()); 526 req->splitOnVaddr(split_addr, req1, req2); 527 528 WholeTranslationState *state = 529 new WholeTranslationState(req, req1, req2, newData, res, mode); 530 DataTranslation<TimingSimpleCPU *> *trans1 = 531 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 532 DataTranslation<TimingSimpleCPU *> *trans2 = 533 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 534 535 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 536 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 537 } else { 538 WholeTranslationState *state = 539 new WholeTranslationState(req, newData, res, mode); 540 DataTranslation<TimingSimpleCPU *> *translation = 541 new DataTranslation<TimingSimpleCPU *>(this, state); 542 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 543 } 544 545 // Translation faults will be returned via finishTranslation() 546 return NoFault; 547} 548 549void 550TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 551{ 552 for (ThreadID tid = 0; tid < numThreads; tid++) { 553 if (tid != sender) { 554 if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 555 wakeup(tid); 556 } 557 TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 558 dcachePort.cacheBlockMask); 559 } 560 } 561} 562 563void 564TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 565{ 566 _status = BaseSimpleCPU::Running; 567 568 if (state->getFault() != NoFault) { 569 if (state->isPrefetch()) { 570 state->setNoFault(); 571 } 572 delete [] state->data; 573 state->deleteReqs(); 574 translationFault(state->getFault()); 575 } else { 576 if (!state->isSplit) { 577 sendData(state->mainReq, state->data, state->res, 578 state->mode == BaseTLB::Read); 579 } else { 580 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 581 state->data, state->mode == BaseTLB::Read); 582 } 583 } 584 585 delete state; 586} 587 588 589void 590TimingSimpleCPU::fetch() 591{ 592 // Change thread if multi-threaded 593 swapActiveThread(); 594 595 SimpleExecContext &t_info = *threadInfo[curThread]; 596 SimpleThread* thread = t_info.thread; 597 598 DPRINTF(SimpleCPU, "Fetch\n"); 599 600 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 601 checkForInterrupts(); 602 checkPcEventQueue(); 603 } 604 605 // We must have just got suspended by a PC event 606 if (_status == Idle) 607 return; 608 609 TheISA::PCState pcState = thread->pcState(); 610 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 611 !curMacroStaticInst; 612 613 if (needToFetch) { 614 _status = BaseSimpleCPU::Running; 615 Request *ifetch_req = new Request(); 616 ifetch_req->taskId(taskId()); 617 ifetch_req->setContext(thread->contextId()); 618 setupFetchRequest(ifetch_req); 619 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 620 thread->itb->translateTiming(ifetch_req, thread->getTC(), 621 &fetchTranslation, BaseTLB::Execute); 622 } else { 623 _status = IcacheWaitResponse; 624 completeIfetch(NULL); 625 626 updateCycleCounts(); 627 } 628} 629 630 631void 632TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 633 ThreadContext *tc) 634{ 635 if (fault == NoFault) { 636 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 637 req->getVaddr(), req->getPaddr()); 638 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 639 ifetch_pkt->dataStatic(&inst); 640 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 641 642 if (!icachePort.sendTimingReq(ifetch_pkt)) { 643 // Need to wait for retry 644 _status = IcacheRetry; 645 } else { 646 // Need to wait for cache to respond 647 _status = IcacheWaitResponse; 648 // ownership of packet transferred to memory system 649 ifetch_pkt = NULL; 650 } 651 } else { 652 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 653 delete req; 654 // fetch fault: advance directly to next instruction (fault handler) 655 _status = BaseSimpleCPU::Running; 656 advanceInst(fault); 657 } 658 659 updateCycleCounts(); 660} 661 662 663void 664TimingSimpleCPU::advanceInst(const Fault &fault) 665{ 666 SimpleExecContext &t_info = *threadInfo[curThread]; 667 668 if (_status == Faulting) 669 return; 670 671 if (fault != NoFault) { 672 advancePC(fault); 673 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 674 reschedule(fetchEvent, clockEdge(), true); 675 _status = Faulting; 676 return; 677 } 678 679 680 if (!t_info.stayAtPC) 681 advancePC(fault); 682 683 if (tryCompleteDrain()) 684 return; 685 686 if (_status == BaseSimpleCPU::Running) { 687 // kick off fetch of next instruction... callback from icache 688 // response will cause that instruction to be executed, 689 // keeping the CPU running. 690 fetch(); 691 } 692} 693 694 695void 696TimingSimpleCPU::completeIfetch(PacketPtr pkt) 697{ 698 SimpleExecContext& t_info = *threadInfo[curThread]; 699 700 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 701 pkt->getAddr() : 0); 702 703 // received a response from the icache: execute the received 704 // instruction 705 assert(!pkt || !pkt->isError()); 706 assert(_status == IcacheWaitResponse); 707 708 _status = BaseSimpleCPU::Running; 709 710 updateCycleCounts(); 711 712 if (pkt) 713 pkt->req->setAccessLatency(); 714 715 716 preExecute(); 717 if (curStaticInst && curStaticInst->isMemRef()) { 718 // load or store: just send to dcache 719 Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 720 721 // If we're not running now the instruction will complete in a dcache 722 // response callback or the instruction faulted and has started an 723 // ifetch 724 if (_status == BaseSimpleCPU::Running) { 725 if (fault != NoFault && traceData) { 726 // If there was a fault, we shouldn't trace this instruction. 727 delete traceData; 728 traceData = NULL; 729 } 730 731 postExecute(); 732 // @todo remove me after debugging with legion done 733 if (curStaticInst && (!curStaticInst->isMicroop() || 734 curStaticInst->isFirstMicroop())) 735 instCnt++; 736 advanceInst(fault); 737 } 738 } else if (curStaticInst) { 739 // non-memory instruction: execute completely now 740 Fault fault = curStaticInst->execute(&t_info, traceData); 741 742 // keep an instruction count 743 if (fault == NoFault) 744 countInst(); 745 else if (traceData && !DTRACE(ExecFaulting)) { 746 delete traceData; 747 traceData = NULL; 748 } 749 750 postExecute(); 751 // @todo remove me after debugging with legion done 752 if (curStaticInst && (!curStaticInst->isMicroop() || 753 curStaticInst->isFirstMicroop())) 754 instCnt++; 755 advanceInst(fault); 756 } else { 757 advanceInst(NoFault); 758 } 759 760 if (pkt) { 761 delete pkt->req; 762 delete pkt; 763 } 764} 765 766void 767TimingSimpleCPU::IcachePort::ITickEvent::process() 768{ 769 cpu->completeIfetch(pkt); 770} 771 772bool 773TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 774{ 775 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 776 // we should only ever see one response per cycle since we only 777 // issue a new request once this response is sunk 778 assert(!tickEvent.scheduled()); 779 // delay processing of returned data until next CPU clock edge 780 tickEvent.schedule(pkt, cpu->clockEdge()); 781 782 return true; 783} 784 785void 786TimingSimpleCPU::IcachePort::recvReqRetry() 787{ 788 // we shouldn't get a retry unless we have a packet that we're 789 // waiting to transmit 790 assert(cpu->ifetch_pkt != NULL); 791 assert(cpu->_status == IcacheRetry); 792 PacketPtr tmp = cpu->ifetch_pkt; 793 if (sendTimingReq(tmp)) { 794 cpu->_status = IcacheWaitResponse; 795 cpu->ifetch_pkt = NULL; 796 } 797} 798 799void 800TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 801{ 802 // received a response from the dcache: complete the load or store 803 // instruction 804 assert(!pkt->isError()); 805 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 806 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 807 808 pkt->req->setAccessLatency(); 809 810 updateCycleCounts(); 811 812 if (pkt->senderState) { 813 SplitFragmentSenderState * send_state = 814 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 815 assert(send_state); 816 delete pkt->req; 817 delete pkt; 818 PacketPtr big_pkt = send_state->bigPkt; 819 delete send_state; 820 821 SplitMainSenderState * main_send_state = 822 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 823 assert(main_send_state); 824 // Record the fact that this packet is no longer outstanding. 825 assert(main_send_state->outstanding != 0); 826 main_send_state->outstanding--; 827 828 if (main_send_state->outstanding) { 829 return; 830 } else { 831 delete main_send_state; 832 big_pkt->senderState = NULL; 833 pkt = big_pkt; 834 } 835 } 836 837 _status = BaseSimpleCPU::Running; 838 839 Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 840 traceData); 841 842 // keep an instruction count 843 if (fault == NoFault) 844 countInst(); 845 else if (traceData) { 846 // If there was a fault, we shouldn't trace this instruction. 847 delete traceData; 848 traceData = NULL; 849 } 850 851 delete pkt->req; 852 delete pkt; 853 854 postExecute(); 855 856 advanceInst(fault); 857} 858 859void 860TimingSimpleCPU::updateCycleCounts() 861{ 862 const Cycles delta(curCycle() - previousCycle); 863 864 numCycles += delta; 865 ppCycles->notify(delta); 866 867 previousCycle = curCycle(); 868} 869 870void 871TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 872{ 873 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 874 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 875 cpu->wakeup(tid); 876 } 877 } 878 879 // Making it uniform across all CPUs: 880 // The CPUs need to be woken up only on an invalidation packet (when using caches) 881 // or on an incoming write packet (when not using caches) 882 // It is not necessary to wake up the processor on all incoming packets 883 if (pkt->isInvalidate() || pkt->isWrite()) { 884 for (auto &t_info : cpu->threadInfo) { 885 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 886 } 887 } 888} 889 890void 891TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 892{ 893 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 894 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 895 cpu->wakeup(tid); 896 } 897 } 898} 899 900bool 901TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 902{ 903 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 904 905 // The timing CPU is not really ticked, instead it relies on the 906 // memory system (fetch and load/store) to set the pace. 907 if (!tickEvent.scheduled()) { 908 // Delay processing of returned data until next CPU clock edge 909 tickEvent.schedule(pkt, cpu->clockEdge()); 910 return true; 911 } else { 912 // In the case of a split transaction and a cache that is 913 // faster than a CPU we could get two responses in the 914 // same tick, delay the second one 915 if (!retryRespEvent.scheduled()) 916 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 917 return false; 918 } 919} 920 921void 922TimingSimpleCPU::DcachePort::DTickEvent::process() 923{ 924 cpu->completeDataAccess(pkt); 925} 926 927void 928TimingSimpleCPU::DcachePort::recvReqRetry() 929{ 930 // we shouldn't get a retry unless we have a packet that we're 931 // waiting to transmit 932 assert(cpu->dcache_pkt != NULL); 933 assert(cpu->_status == DcacheRetry); 934 PacketPtr tmp = cpu->dcache_pkt; 935 if (tmp->senderState) { 936 // This is a packet from a split access. 937 SplitFragmentSenderState * send_state = 938 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 939 assert(send_state); 940 PacketPtr big_pkt = send_state->bigPkt; 941 942 SplitMainSenderState * main_send_state = 943 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 944 assert(main_send_state); 945 946 if (sendTimingReq(tmp)) { 947 // If we were able to send without retrying, record that fact 948 // and try sending the other fragment. 949 send_state->clearFromParent(); 950 int other_index = main_send_state->getPendingFragment(); 951 if (other_index > 0) { 952 tmp = main_send_state->fragments[other_index]; 953 cpu->dcache_pkt = tmp; 954 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 955 (big_pkt->isWrite() && cpu->handleWritePacket())) { 956 main_send_state->fragments[other_index] = NULL; 957 } 958 } else { 959 cpu->_status = DcacheWaitResponse; 960 // memory system takes ownership of packet 961 cpu->dcache_pkt = NULL; 962 } 963 } 964 } else if (sendTimingReq(tmp)) { 965 cpu->_status = DcacheWaitResponse; 966 // memory system takes ownership of packet 967 cpu->dcache_pkt = NULL; 968 } 969} 970 971TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 972 Tick t) 973 : pkt(_pkt), cpu(_cpu) 974{ 975 cpu->schedule(this, t); 976} 977 978void 979TimingSimpleCPU::IprEvent::process() 980{ 981 cpu->completeDataAccess(pkt); 982} 983 984const char * 985TimingSimpleCPU::IprEvent::description() const 986{ 987 return "Timing Simple CPU Delay IPR event"; 988} 989 990 991void 992TimingSimpleCPU::printAddr(Addr a) 993{ 994 dcachePort.printAddr(a); 995} 996 997 998//////////////////////////////////////////////////////////////////////// 999// 1000// TimingSimpleCPU Simulation Object 1001// 1002TimingSimpleCPU * 1003TimingSimpleCPUParams::create() 1004{ 1005 return new TimingSimpleCPU(this); 1006} 1007