timing.cc revision 11435
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013,2015 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/locked_mem.hh" 45#include "arch/mmapped_ipr.hh" 46#include "arch/utility.hh" 47#include "base/bigint.hh" 48#include "config/the_isa.hh" 49#include "cpu/simple/timing.hh" 50#include "cpu/exetrace.hh" 51#include "debug/Config.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/SimpleCPU.hh" 55#include "mem/packet.hh" 56#include "mem/packet_access.hh" 57#include "params/TimingSimpleCPU.hh" 58#include "sim/faults.hh" 59#include "sim/full_system.hh" 60#include "sim/system.hh" 61 62#include "debug/Mwait.hh" 63 64using namespace std; 65using namespace TheISA; 66 67void 68TimingSimpleCPU::init() 69{ 70 BaseSimpleCPU::init(); 71} 72 73void 74TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 75{ 76 pkt = _pkt; 77 cpu->schedule(this, t); 78} 79 80TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 81 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 82 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 83 fetchEvent(this) 84{ 85 _status = Idle; 86} 87 88 89 90TimingSimpleCPU::~TimingSimpleCPU() 91{ 92} 93 94DrainState 95TimingSimpleCPU::drain() 96{ 97 if (switchedOut()) 98 return DrainState::Drained; 99 100 if (_status == Idle || 101 (_status == BaseSimpleCPU::Running && isDrained())) { 102 DPRINTF(Drain, "No need to drain.\n"); 103 activeThreads.clear(); 104 return DrainState::Drained; 105 } else { 106 DPRINTF(Drain, "Requesting drain.\n"); 107 108 // The fetch event can become descheduled if a drain didn't 109 // succeed on the first attempt. We need to reschedule it if 110 // the CPU is waiting for a microcode routine to complete. 111 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 112 schedule(fetchEvent, clockEdge()); 113 114 return DrainState::Draining; 115 } 116} 117 118void 119TimingSimpleCPU::drainResume() 120{ 121 assert(!fetchEvent.scheduled()); 122 if (switchedOut()) 123 return; 124 125 DPRINTF(SimpleCPU, "Resume\n"); 126 verifyMemoryMode(); 127 128 assert(!threadContexts.empty()); 129 130 _status = BaseSimpleCPU::Idle; 131 132 for (ThreadID tid = 0; tid < numThreads; tid++) { 133 if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 134 threadInfo[tid]->notIdleFraction = 1; 135 136 activeThreads.push_back(tid); 137 138 _status = BaseSimpleCPU::Running; 139 140 // Fetch if any threads active 141 if (!fetchEvent.scheduled()) { 142 schedule(fetchEvent, nextCycle()); 143 } 144 } else { 145 threadInfo[tid]->notIdleFraction = 0; 146 } 147 } 148 149 system->totalNumInsts = 0; 150} 151 152bool 153TimingSimpleCPU::tryCompleteDrain() 154{ 155 if (drainState() != DrainState::Draining) 156 return false; 157 158 DPRINTF(Drain, "tryCompleteDrain.\n"); 159 if (!isDrained()) 160 return false; 161 162 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 163 signalDrainDone(); 164 165 return true; 166} 167 168void 169TimingSimpleCPU::switchOut() 170{ 171 SimpleExecContext& t_info = *threadInfo[curThread]; 172 M5_VAR_USED SimpleThread* thread = t_info.thread; 173 174 BaseSimpleCPU::switchOut(); 175 176 assert(!fetchEvent.scheduled()); 177 assert(_status == BaseSimpleCPU::Running || _status == Idle); 178 assert(!t_info.stayAtPC); 179 assert(thread->microPC() == 0); 180 181 updateCycleCounts(); 182} 183 184 185void 186TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 187{ 188 BaseSimpleCPU::takeOverFrom(oldCPU); 189 190 previousCycle = curCycle(); 191} 192 193void 194TimingSimpleCPU::verifyMemoryMode() const 195{ 196 if (!system->isTimingMode()) { 197 fatal("The timing CPU requires the memory system to be in " 198 "'timing' mode.\n"); 199 } 200} 201 202void 203TimingSimpleCPU::activateContext(ThreadID thread_num) 204{ 205 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 206 207 assert(thread_num < numThreads); 208 209 threadInfo[thread_num]->notIdleFraction = 1; 210 if (_status == BaseSimpleCPU::Idle) 211 _status = BaseSimpleCPU::Running; 212 213 // kick things off by initiating the fetch of the next instruction 214 if (!fetchEvent.scheduled()) 215 schedule(fetchEvent, clockEdge(Cycles(0))); 216 217 if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 218 == activeThreads.end()) { 219 activeThreads.push_back(thread_num); 220 } 221} 222 223 224void 225TimingSimpleCPU::suspendContext(ThreadID thread_num) 226{ 227 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 228 229 assert(thread_num < numThreads); 230 activeThreads.remove(thread_num); 231 232 if (_status == Idle) 233 return; 234 235 assert(_status == BaseSimpleCPU::Running); 236 237 threadInfo[thread_num]->notIdleFraction = 0; 238 239 if (activeThreads.empty()) { 240 _status = Idle; 241 242 if (fetchEvent.scheduled()) { 243 deschedule(fetchEvent); 244 } 245 } 246} 247 248bool 249TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 250{ 251 SimpleExecContext &t_info = *threadInfo[curThread]; 252 SimpleThread* thread = t_info.thread; 253 254 RequestPtr req = pkt->req; 255 256 // We're about the issues a locked load, so tell the monitor 257 // to start caring about this address 258 if (pkt->isRead() && pkt->req->isLLSC()) { 259 TheISA::handleLockedRead(thread, pkt->req); 260 } 261 if (req->isMmappedIpr()) { 262 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 263 new IprEvent(pkt, this, clockEdge(delay)); 264 _status = DcacheWaitResponse; 265 dcache_pkt = NULL; 266 } else if (!dcachePort.sendTimingReq(pkt)) { 267 _status = DcacheRetry; 268 dcache_pkt = pkt; 269 } else { 270 _status = DcacheWaitResponse; 271 // memory system takes ownership of packet 272 dcache_pkt = NULL; 273 } 274 return dcache_pkt == NULL; 275} 276 277void 278TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 279 bool read) 280{ 281 SimpleExecContext &t_info = *threadInfo[curThread]; 282 SimpleThread* thread = t_info.thread; 283 284 PacketPtr pkt = buildPacket(req, read); 285 pkt->dataDynamic<uint8_t>(data); 286 if (req->getFlags().isSet(Request::NO_ACCESS)) { 287 assert(!dcache_pkt); 288 pkt->makeResponse(); 289 completeDataAccess(pkt); 290 } else if (read) { 291 handleReadPacket(pkt); 292 } else { 293 bool do_access = true; // flag to suppress cache access 294 295 if (req->isLLSC()) { 296 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 297 } else if (req->isCondSwap()) { 298 assert(res); 299 req->setExtraData(*res); 300 } 301 302 if (do_access) { 303 dcache_pkt = pkt; 304 handleWritePacket(); 305 threadSnoop(pkt, curThread); 306 } else { 307 _status = DcacheWaitResponse; 308 completeDataAccess(pkt); 309 } 310 } 311} 312 313void 314TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 315 RequestPtr req, uint8_t *data, bool read) 316{ 317 PacketPtr pkt1, pkt2; 318 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 319 if (req->getFlags().isSet(Request::NO_ACCESS)) { 320 assert(!dcache_pkt); 321 pkt1->makeResponse(); 322 completeDataAccess(pkt1); 323 } else if (read) { 324 SplitFragmentSenderState * send_state = 325 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 326 if (handleReadPacket(pkt1)) { 327 send_state->clearFromParent(); 328 send_state = dynamic_cast<SplitFragmentSenderState *>( 329 pkt2->senderState); 330 if (handleReadPacket(pkt2)) { 331 send_state->clearFromParent(); 332 } 333 } 334 } else { 335 dcache_pkt = pkt1; 336 SplitFragmentSenderState * send_state = 337 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 338 if (handleWritePacket()) { 339 send_state->clearFromParent(); 340 dcache_pkt = pkt2; 341 send_state = dynamic_cast<SplitFragmentSenderState *>( 342 pkt2->senderState); 343 if (handleWritePacket()) { 344 send_state->clearFromParent(); 345 } 346 } 347 } 348} 349 350void 351TimingSimpleCPU::translationFault(const Fault &fault) 352{ 353 // fault may be NoFault in cases where a fault is suppressed, 354 // for instance prefetches. 355 updateCycleCounts(); 356 357 if (traceData) { 358 // Since there was a fault, we shouldn't trace this instruction. 359 delete traceData; 360 traceData = NULL; 361 } 362 363 postExecute(); 364 365 advanceInst(fault); 366} 367 368PacketPtr 369TimingSimpleCPU::buildPacket(RequestPtr req, bool read) 370{ 371 return read ? Packet::createRead(req) : Packet::createWrite(req); 372} 373 374void 375TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 376 RequestPtr req1, RequestPtr req2, RequestPtr req, 377 uint8_t *data, bool read) 378{ 379 pkt1 = pkt2 = NULL; 380 381 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 382 383 if (req->getFlags().isSet(Request::NO_ACCESS)) { 384 pkt1 = buildPacket(req, read); 385 return; 386 } 387 388 pkt1 = buildPacket(req1, read); 389 pkt2 = buildPacket(req2, read); 390 391 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 392 393 pkt->dataDynamic<uint8_t>(data); 394 pkt1->dataStatic<uint8_t>(data); 395 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 396 397 SplitMainSenderState * main_send_state = new SplitMainSenderState; 398 pkt->senderState = main_send_state; 399 main_send_state->fragments[0] = pkt1; 400 main_send_state->fragments[1] = pkt2; 401 main_send_state->outstanding = 2; 402 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 403 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 404} 405 406Fault 407TimingSimpleCPU::readMem(Addr addr, uint8_t *data, 408 unsigned size, unsigned flags) 409{ 410 panic("readMem() is for atomic accesses, and should " 411 "never be called on TimingSimpleCPU.\n"); 412} 413 414Fault 415TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags) 416{ 417 SimpleExecContext &t_info = *threadInfo[curThread]; 418 SimpleThread* thread = t_info.thread; 419 420 Fault fault; 421 const int asid = 0; 422 const Addr pc = thread->instAddr(); 423 unsigned block_size = cacheLineSize(); 424 BaseTLB::Mode mode = BaseTLB::Read; 425 426 if (traceData) 427 traceData->setMem(addr, size, flags); 428 429 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 430 thread->contextId()); 431 432 req->taskId(taskId()); 433 434 Addr split_addr = roundDown(addr + size - 1, block_size); 435 assert(split_addr <= addr || split_addr - addr < block_size); 436 437 _status = DTBWaitResponse; 438 if (split_addr > addr) { 439 RequestPtr req1, req2; 440 assert(!req->isLLSC() && !req->isSwap()); 441 req->splitOnVaddr(split_addr, req1, req2); 442 443 WholeTranslationState *state = 444 new WholeTranslationState(req, req1, req2, new uint8_t[size], 445 NULL, mode); 446 DataTranslation<TimingSimpleCPU *> *trans1 = 447 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 448 DataTranslation<TimingSimpleCPU *> *trans2 = 449 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 450 451 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 452 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 453 } else { 454 WholeTranslationState *state = 455 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 456 DataTranslation<TimingSimpleCPU *> *translation 457 = new DataTranslation<TimingSimpleCPU *>(this, state); 458 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 459 } 460 461 return NoFault; 462} 463 464bool 465TimingSimpleCPU::handleWritePacket() 466{ 467 SimpleExecContext &t_info = *threadInfo[curThread]; 468 SimpleThread* thread = t_info.thread; 469 470 RequestPtr req = dcache_pkt->req; 471 if (req->isMmappedIpr()) { 472 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 473 new IprEvent(dcache_pkt, this, clockEdge(delay)); 474 _status = DcacheWaitResponse; 475 dcache_pkt = NULL; 476 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 477 _status = DcacheRetry; 478 } else { 479 _status = DcacheWaitResponse; 480 // memory system takes ownership of packet 481 dcache_pkt = NULL; 482 } 483 return dcache_pkt == NULL; 484} 485 486Fault 487TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 488 Addr addr, unsigned flags, uint64_t *res) 489{ 490 SimpleExecContext &t_info = *threadInfo[curThread]; 491 SimpleThread* thread = t_info.thread; 492 493 uint8_t *newData = new uint8_t[size]; 494 const int asid = 0; 495 const Addr pc = thread->instAddr(); 496 unsigned block_size = cacheLineSize(); 497 BaseTLB::Mode mode = BaseTLB::Write; 498 499 if (data == NULL) { 500 assert(flags & Request::CACHE_BLOCK_ZERO); 501 // This must be a cache block cleaning request 502 memset(newData, 0, size); 503 } else { 504 memcpy(newData, data, size); 505 } 506 507 if (traceData) 508 traceData->setMem(addr, size, flags); 509 510 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 511 thread->contextId()); 512 513 req->taskId(taskId()); 514 515 Addr split_addr = roundDown(addr + size - 1, block_size); 516 assert(split_addr <= addr || split_addr - addr < block_size); 517 518 _status = DTBWaitResponse; 519 if (split_addr > addr) { 520 RequestPtr req1, req2; 521 assert(!req->isLLSC() && !req->isSwap()); 522 req->splitOnVaddr(split_addr, req1, req2); 523 524 WholeTranslationState *state = 525 new WholeTranslationState(req, req1, req2, newData, res, mode); 526 DataTranslation<TimingSimpleCPU *> *trans1 = 527 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 528 DataTranslation<TimingSimpleCPU *> *trans2 = 529 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 530 531 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 532 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 533 } else { 534 WholeTranslationState *state = 535 new WholeTranslationState(req, newData, res, mode); 536 DataTranslation<TimingSimpleCPU *> *translation = 537 new DataTranslation<TimingSimpleCPU *>(this, state); 538 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 539 } 540 541 // Translation faults will be returned via finishTranslation() 542 return NoFault; 543} 544 545void 546TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 547{ 548 for (ThreadID tid = 0; tid < numThreads; tid++) { 549 if (tid != sender) { 550 if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 551 wakeup(tid); 552 } 553 TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 554 dcachePort.cacheBlockMask); 555 } 556 } 557} 558 559void 560TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 561{ 562 _status = BaseSimpleCPU::Running; 563 564 if (state->getFault() != NoFault) { 565 if (state->isPrefetch()) { 566 state->setNoFault(); 567 } 568 delete [] state->data; 569 state->deleteReqs(); 570 translationFault(state->getFault()); 571 } else { 572 if (!state->isSplit) { 573 sendData(state->mainReq, state->data, state->res, 574 state->mode == BaseTLB::Read); 575 } else { 576 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 577 state->data, state->mode == BaseTLB::Read); 578 } 579 } 580 581 delete state; 582} 583 584 585void 586TimingSimpleCPU::fetch() 587{ 588 // Change thread if multi-threaded 589 swapActiveThread(); 590 591 SimpleExecContext &t_info = *threadInfo[curThread]; 592 SimpleThread* thread = t_info.thread; 593 594 DPRINTF(SimpleCPU, "Fetch\n"); 595 596 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 597 checkForInterrupts(); 598 checkPcEventQueue(); 599 } 600 601 // We must have just got suspended by a PC event 602 if (_status == Idle) 603 return; 604 605 TheISA::PCState pcState = thread->pcState(); 606 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 607 !curMacroStaticInst; 608 609 if (needToFetch) { 610 _status = BaseSimpleCPU::Running; 611 Request *ifetch_req = new Request(); 612 ifetch_req->taskId(taskId()); 613 ifetch_req->setContext(thread->contextId()); 614 setupFetchRequest(ifetch_req); 615 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 616 thread->itb->translateTiming(ifetch_req, thread->getTC(), 617 &fetchTranslation, BaseTLB::Execute); 618 } else { 619 _status = IcacheWaitResponse; 620 completeIfetch(NULL); 621 622 updateCycleCounts(); 623 } 624} 625 626 627void 628TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 629 ThreadContext *tc) 630{ 631 if (fault == NoFault) { 632 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 633 req->getVaddr(), req->getPaddr()); 634 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 635 ifetch_pkt->dataStatic(&inst); 636 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 637 638 if (!icachePort.sendTimingReq(ifetch_pkt)) { 639 // Need to wait for retry 640 _status = IcacheRetry; 641 } else { 642 // Need to wait for cache to respond 643 _status = IcacheWaitResponse; 644 // ownership of packet transferred to memory system 645 ifetch_pkt = NULL; 646 } 647 } else { 648 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 649 delete req; 650 // fetch fault: advance directly to next instruction (fault handler) 651 _status = BaseSimpleCPU::Running; 652 advanceInst(fault); 653 } 654 655 updateCycleCounts(); 656} 657 658 659void 660TimingSimpleCPU::advanceInst(const Fault &fault) 661{ 662 SimpleExecContext &t_info = *threadInfo[curThread]; 663 664 if (_status == Faulting) 665 return; 666 667 if (fault != NoFault) { 668 advancePC(fault); 669 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 670 reschedule(fetchEvent, clockEdge(), true); 671 _status = Faulting; 672 return; 673 } 674 675 676 if (!t_info.stayAtPC) 677 advancePC(fault); 678 679 if (tryCompleteDrain()) 680 return; 681 682 if (_status == BaseSimpleCPU::Running) { 683 // kick off fetch of next instruction... callback from icache 684 // response will cause that instruction to be executed, 685 // keeping the CPU running. 686 fetch(); 687 } 688} 689 690 691void 692TimingSimpleCPU::completeIfetch(PacketPtr pkt) 693{ 694 SimpleExecContext& t_info = *threadInfo[curThread]; 695 696 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 697 pkt->getAddr() : 0); 698 699 // received a response from the icache: execute the received 700 // instruction 701 assert(!pkt || !pkt->isError()); 702 assert(_status == IcacheWaitResponse); 703 704 _status = BaseSimpleCPU::Running; 705 706 updateCycleCounts(); 707 708 if (pkt) 709 pkt->req->setAccessLatency(); 710 711 712 preExecute(); 713 if (curStaticInst && curStaticInst->isMemRef()) { 714 // load or store: just send to dcache 715 Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 716 717 // If we're not running now the instruction will complete in a dcache 718 // response callback or the instruction faulted and has started an 719 // ifetch 720 if (_status == BaseSimpleCPU::Running) { 721 if (fault != NoFault && traceData) { 722 // If there was a fault, we shouldn't trace this instruction. 723 delete traceData; 724 traceData = NULL; 725 } 726 727 postExecute(); 728 // @todo remove me after debugging with legion done 729 if (curStaticInst && (!curStaticInst->isMicroop() || 730 curStaticInst->isFirstMicroop())) 731 instCnt++; 732 advanceInst(fault); 733 } 734 } else if (curStaticInst) { 735 // non-memory instruction: execute completely now 736 Fault fault = curStaticInst->execute(&t_info, traceData); 737 738 // keep an instruction count 739 if (fault == NoFault) 740 countInst(); 741 else if (traceData && !DTRACE(ExecFaulting)) { 742 delete traceData; 743 traceData = NULL; 744 } 745 746 postExecute(); 747 // @todo remove me after debugging with legion done 748 if (curStaticInst && (!curStaticInst->isMicroop() || 749 curStaticInst->isFirstMicroop())) 750 instCnt++; 751 advanceInst(fault); 752 } else { 753 advanceInst(NoFault); 754 } 755 756 if (pkt) { 757 delete pkt->req; 758 delete pkt; 759 } 760} 761 762void 763TimingSimpleCPU::IcachePort::ITickEvent::process() 764{ 765 cpu->completeIfetch(pkt); 766} 767 768bool 769TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 770{ 771 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 772 // we should only ever see one response per cycle since we only 773 // issue a new request once this response is sunk 774 assert(!tickEvent.scheduled()); 775 // delay processing of returned data until next CPU clock edge 776 tickEvent.schedule(pkt, cpu->clockEdge()); 777 778 return true; 779} 780 781void 782TimingSimpleCPU::IcachePort::recvReqRetry() 783{ 784 // we shouldn't get a retry unless we have a packet that we're 785 // waiting to transmit 786 assert(cpu->ifetch_pkt != NULL); 787 assert(cpu->_status == IcacheRetry); 788 PacketPtr tmp = cpu->ifetch_pkt; 789 if (sendTimingReq(tmp)) { 790 cpu->_status = IcacheWaitResponse; 791 cpu->ifetch_pkt = NULL; 792 } 793} 794 795void 796TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 797{ 798 // received a response from the dcache: complete the load or store 799 // instruction 800 assert(!pkt->isError()); 801 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 802 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 803 804 pkt->req->setAccessLatency(); 805 806 updateCycleCounts(); 807 808 if (pkt->senderState) { 809 SplitFragmentSenderState * send_state = 810 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 811 assert(send_state); 812 delete pkt->req; 813 delete pkt; 814 PacketPtr big_pkt = send_state->bigPkt; 815 delete send_state; 816 817 SplitMainSenderState * main_send_state = 818 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 819 assert(main_send_state); 820 // Record the fact that this packet is no longer outstanding. 821 assert(main_send_state->outstanding != 0); 822 main_send_state->outstanding--; 823 824 if (main_send_state->outstanding) { 825 return; 826 } else { 827 delete main_send_state; 828 big_pkt->senderState = NULL; 829 pkt = big_pkt; 830 } 831 } 832 833 _status = BaseSimpleCPU::Running; 834 835 Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 836 traceData); 837 838 // keep an instruction count 839 if (fault == NoFault) 840 countInst(); 841 else if (traceData) { 842 // If there was a fault, we shouldn't trace this instruction. 843 delete traceData; 844 traceData = NULL; 845 } 846 847 delete pkt->req; 848 delete pkt; 849 850 postExecute(); 851 852 advanceInst(fault); 853} 854 855void 856TimingSimpleCPU::updateCycleCounts() 857{ 858 const Cycles delta(curCycle() - previousCycle); 859 860 numCycles += delta; 861 ppCycles->notify(delta); 862 863 previousCycle = curCycle(); 864} 865 866void 867TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 868{ 869 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 870 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 871 cpu->wakeup(tid); 872 } 873 } 874 875 // Making it uniform across all CPUs: 876 // The CPUs need to be woken up only on an invalidation packet (when using caches) 877 // or on an incoming write packet (when not using caches) 878 // It is not necessary to wake up the processor on all incoming packets 879 if (pkt->isInvalidate() || pkt->isWrite()) { 880 for (auto &t_info : cpu->threadInfo) { 881 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 882 } 883 } 884} 885 886void 887TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 888{ 889 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 890 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 891 cpu->wakeup(tid); 892 } 893 } 894} 895 896bool 897TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 898{ 899 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 900 901 // The timing CPU is not really ticked, instead it relies on the 902 // memory system (fetch and load/store) to set the pace. 903 if (!tickEvent.scheduled()) { 904 // Delay processing of returned data until next CPU clock edge 905 tickEvent.schedule(pkt, cpu->clockEdge()); 906 return true; 907 } else { 908 // In the case of a split transaction and a cache that is 909 // faster than a CPU we could get two responses in the 910 // same tick, delay the second one 911 if (!retryRespEvent.scheduled()) 912 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 913 return false; 914 } 915} 916 917void 918TimingSimpleCPU::DcachePort::DTickEvent::process() 919{ 920 cpu->completeDataAccess(pkt); 921} 922 923void 924TimingSimpleCPU::DcachePort::recvReqRetry() 925{ 926 // we shouldn't get a retry unless we have a packet that we're 927 // waiting to transmit 928 assert(cpu->dcache_pkt != NULL); 929 assert(cpu->_status == DcacheRetry); 930 PacketPtr tmp = cpu->dcache_pkt; 931 if (tmp->senderState) { 932 // This is a packet from a split access. 933 SplitFragmentSenderState * send_state = 934 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 935 assert(send_state); 936 PacketPtr big_pkt = send_state->bigPkt; 937 938 SplitMainSenderState * main_send_state = 939 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 940 assert(main_send_state); 941 942 if (sendTimingReq(tmp)) { 943 // If we were able to send without retrying, record that fact 944 // and try sending the other fragment. 945 send_state->clearFromParent(); 946 int other_index = main_send_state->getPendingFragment(); 947 if (other_index > 0) { 948 tmp = main_send_state->fragments[other_index]; 949 cpu->dcache_pkt = tmp; 950 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 951 (big_pkt->isWrite() && cpu->handleWritePacket())) { 952 main_send_state->fragments[other_index] = NULL; 953 } 954 } else { 955 cpu->_status = DcacheWaitResponse; 956 // memory system takes ownership of packet 957 cpu->dcache_pkt = NULL; 958 } 959 } 960 } else if (sendTimingReq(tmp)) { 961 cpu->_status = DcacheWaitResponse; 962 // memory system takes ownership of packet 963 cpu->dcache_pkt = NULL; 964 } 965} 966 967TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 968 Tick t) 969 : pkt(_pkt), cpu(_cpu) 970{ 971 cpu->schedule(this, t); 972} 973 974void 975TimingSimpleCPU::IprEvent::process() 976{ 977 cpu->completeDataAccess(pkt); 978} 979 980const char * 981TimingSimpleCPU::IprEvent::description() const 982{ 983 return "Timing Simple CPU Delay IPR event"; 984} 985 986 987void 988TimingSimpleCPU::printAddr(Addr a) 989{ 990 dcachePort.printAddr(a); 991} 992 993 994//////////////////////////////////////////////////////////////////////// 995// 996// TimingSimpleCPU Simulation Object 997// 998TimingSimpleCPU * 999TimingSimpleCPUParams::create() 1000{ 1001 return new TimingSimpleCPU(this); 1002} 1003