timing.cc revision 11423:831c7f2f9e39
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013,2015 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/locked_mem.hh" 45#include "arch/mmapped_ipr.hh" 46#include "arch/utility.hh" 47#include "base/bigint.hh" 48#include "config/the_isa.hh" 49#include "cpu/simple/timing.hh" 50#include "cpu/exetrace.hh" 51#include "debug/Config.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/SimpleCPU.hh" 55#include "mem/packet.hh" 56#include "mem/packet_access.hh" 57#include "params/TimingSimpleCPU.hh" 58#include "sim/faults.hh" 59#include "sim/full_system.hh" 60#include "sim/system.hh" 61 62#include "debug/Mwait.hh" 63 64using namespace std; 65using namespace TheISA; 66 67void 68TimingSimpleCPU::init() 69{ 70 BaseSimpleCPU::init(); 71} 72 73void 74TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 75{ 76 pkt = _pkt; 77 cpu->schedule(this, t); 78} 79 80TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 81 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 82 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 83 fetchEvent(this) 84{ 85 _status = Idle; 86} 87 88 89 90TimingSimpleCPU::~TimingSimpleCPU() 91{ 92} 93 94DrainState 95TimingSimpleCPU::drain() 96{ 97 if (switchedOut()) 98 return DrainState::Drained; 99 100 if (_status == Idle || 101 (_status == BaseSimpleCPU::Running && isDrained())) { 102 DPRINTF(Drain, "No need to drain.\n"); 103 activeThreads.clear(); 104 return DrainState::Drained; 105 } else { 106 DPRINTF(Drain, "Requesting drain.\n"); 107 108 // The fetch event can become descheduled if a drain didn't 109 // succeed on the first attempt. We need to reschedule it if 110 // the CPU is waiting for a microcode routine to complete. 111 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 112 schedule(fetchEvent, clockEdge()); 113 114 return DrainState::Draining; 115 } 116} 117 118void 119TimingSimpleCPU::drainResume() 120{ 121 assert(!fetchEvent.scheduled()); 122 if (switchedOut()) 123 return; 124 125 DPRINTF(SimpleCPU, "Resume\n"); 126 verifyMemoryMode(); 127 128 assert(!threadContexts.empty()); 129 130 _status = BaseSimpleCPU::Idle; 131 132 for (ThreadID tid = 0; tid < numThreads; tid++) { 133 if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 134 threadInfo[tid]->notIdleFraction = 1; 135 136 activeThreads.push_back(tid); 137 138 _status = BaseSimpleCPU::Running; 139 140 // Fetch if any threads active 141 if (!fetchEvent.scheduled()) { 142 schedule(fetchEvent, nextCycle()); 143 } 144 } else { 145 threadInfo[tid]->notIdleFraction = 0; 146 } 147 } 148 149 system->totalNumInsts = 0; 150} 151 152bool 153TimingSimpleCPU::tryCompleteDrain() 154{ 155 if (drainState() != DrainState::Draining) 156 return false; 157 158 DPRINTF(Drain, "tryCompleteDrain.\n"); 159 if (!isDrained()) 160 return false; 161 162 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 163 signalDrainDone(); 164 165 return true; 166} 167 168void 169TimingSimpleCPU::switchOut() 170{ 171 SimpleExecContext& t_info = *threadInfo[curThread]; 172 M5_VAR_USED SimpleThread* thread = t_info.thread; 173 174 BaseSimpleCPU::switchOut(); 175 176 assert(!fetchEvent.scheduled()); 177 assert(_status == BaseSimpleCPU::Running || _status == Idle); 178 assert(!t_info.stayAtPC); 179 assert(thread->microPC() == 0); 180 181 updateCycleCounts(); 182} 183 184 185void 186TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 187{ 188 BaseSimpleCPU::takeOverFrom(oldCPU); 189 190 previousCycle = curCycle(); 191} 192 193void 194TimingSimpleCPU::verifyMemoryMode() const 195{ 196 if (!system->isTimingMode()) { 197 fatal("The timing CPU requires the memory system to be in " 198 "'timing' mode.\n"); 199 } 200} 201 202void 203TimingSimpleCPU::activateContext(ThreadID thread_num) 204{ 205 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 206 207 assert(thread_num < numThreads); 208 209 threadInfo[thread_num]->notIdleFraction = 1; 210 if (_status == BaseSimpleCPU::Idle) 211 _status = BaseSimpleCPU::Running; 212 213 // kick things off by initiating the fetch of the next instruction 214 if (!fetchEvent.scheduled()) 215 schedule(fetchEvent, clockEdge(Cycles(0))); 216 217 if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 218 == activeThreads.end()) { 219 activeThreads.push_back(thread_num); 220 } 221 222 BaseCPU::activateContext(thread_num); 223} 224 225 226void 227TimingSimpleCPU::suspendContext(ThreadID thread_num) 228{ 229 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 230 231 assert(thread_num < numThreads); 232 activeThreads.remove(thread_num); 233 234 if (_status == Idle) 235 return; 236 237 assert(_status == BaseSimpleCPU::Running); 238 239 threadInfo[thread_num]->notIdleFraction = 0; 240 241 if (activeThreads.empty()) { 242 _status = Idle; 243 244 if (fetchEvent.scheduled()) { 245 deschedule(fetchEvent); 246 } 247 } 248 249 BaseCPU::suspendContext(thread_num); 250} 251 252bool 253TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 254{ 255 SimpleExecContext &t_info = *threadInfo[curThread]; 256 SimpleThread* thread = t_info.thread; 257 258 RequestPtr req = pkt->req; 259 260 // We're about the issues a locked load, so tell the monitor 261 // to start caring about this address 262 if (pkt->isRead() && pkt->req->isLLSC()) { 263 TheISA::handleLockedRead(thread, pkt->req); 264 } 265 if (req->isMmappedIpr()) { 266 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 267 new IprEvent(pkt, this, clockEdge(delay)); 268 _status = DcacheWaitResponse; 269 dcache_pkt = NULL; 270 } else if (!dcachePort.sendTimingReq(pkt)) { 271 _status = DcacheRetry; 272 dcache_pkt = pkt; 273 } else { 274 _status = DcacheWaitResponse; 275 // memory system takes ownership of packet 276 dcache_pkt = NULL; 277 } 278 return dcache_pkt == NULL; 279} 280 281void 282TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 283 bool read) 284{ 285 SimpleExecContext &t_info = *threadInfo[curThread]; 286 SimpleThread* thread = t_info.thread; 287 288 PacketPtr pkt = buildPacket(req, read); 289 pkt->dataDynamic<uint8_t>(data); 290 if (req->getFlags().isSet(Request::NO_ACCESS)) { 291 assert(!dcache_pkt); 292 pkt->makeResponse(); 293 completeDataAccess(pkt); 294 } else if (read) { 295 handleReadPacket(pkt); 296 } else { 297 bool do_access = true; // flag to suppress cache access 298 299 if (req->isLLSC()) { 300 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 301 } else if (req->isCondSwap()) { 302 assert(res); 303 req->setExtraData(*res); 304 } 305 306 if (do_access) { 307 dcache_pkt = pkt; 308 handleWritePacket(); 309 threadSnoop(pkt, curThread); 310 } else { 311 _status = DcacheWaitResponse; 312 completeDataAccess(pkt); 313 } 314 } 315} 316 317void 318TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 319 RequestPtr req, uint8_t *data, bool read) 320{ 321 PacketPtr pkt1, pkt2; 322 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 323 if (req->getFlags().isSet(Request::NO_ACCESS)) { 324 assert(!dcache_pkt); 325 pkt1->makeResponse(); 326 completeDataAccess(pkt1); 327 } else if (read) { 328 SplitFragmentSenderState * send_state = 329 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 330 if (handleReadPacket(pkt1)) { 331 send_state->clearFromParent(); 332 send_state = dynamic_cast<SplitFragmentSenderState *>( 333 pkt2->senderState); 334 if (handleReadPacket(pkt2)) { 335 send_state->clearFromParent(); 336 } 337 } 338 } else { 339 dcache_pkt = pkt1; 340 SplitFragmentSenderState * send_state = 341 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 342 if (handleWritePacket()) { 343 send_state->clearFromParent(); 344 dcache_pkt = pkt2; 345 send_state = dynamic_cast<SplitFragmentSenderState *>( 346 pkt2->senderState); 347 if (handleWritePacket()) { 348 send_state->clearFromParent(); 349 } 350 } 351 } 352} 353 354void 355TimingSimpleCPU::translationFault(const Fault &fault) 356{ 357 // fault may be NoFault in cases where a fault is suppressed, 358 // for instance prefetches. 359 updateCycleCounts(); 360 361 if (traceData) { 362 // Since there was a fault, we shouldn't trace this instruction. 363 delete traceData; 364 traceData = NULL; 365 } 366 367 postExecute(); 368 369 advanceInst(fault); 370} 371 372PacketPtr 373TimingSimpleCPU::buildPacket(RequestPtr req, bool read) 374{ 375 return read ? Packet::createRead(req) : Packet::createWrite(req); 376} 377 378void 379TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 380 RequestPtr req1, RequestPtr req2, RequestPtr req, 381 uint8_t *data, bool read) 382{ 383 pkt1 = pkt2 = NULL; 384 385 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 386 387 if (req->getFlags().isSet(Request::NO_ACCESS)) { 388 pkt1 = buildPacket(req, read); 389 return; 390 } 391 392 pkt1 = buildPacket(req1, read); 393 pkt2 = buildPacket(req2, read); 394 395 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 396 397 pkt->dataDynamic<uint8_t>(data); 398 pkt1->dataStatic<uint8_t>(data); 399 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 400 401 SplitMainSenderState * main_send_state = new SplitMainSenderState; 402 pkt->senderState = main_send_state; 403 main_send_state->fragments[0] = pkt1; 404 main_send_state->fragments[1] = pkt2; 405 main_send_state->outstanding = 2; 406 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 407 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 408} 409 410Fault 411TimingSimpleCPU::readMem(Addr addr, uint8_t *data, 412 unsigned size, unsigned flags) 413{ 414 panic("readMem() is for atomic accesses, and should " 415 "never be called on TimingSimpleCPU.\n"); 416} 417 418Fault 419TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags) 420{ 421 SimpleExecContext &t_info = *threadInfo[curThread]; 422 SimpleThread* thread = t_info.thread; 423 424 Fault fault; 425 const int asid = 0; 426 const ThreadID tid = curThread; 427 const Addr pc = thread->instAddr(); 428 unsigned block_size = cacheLineSize(); 429 BaseTLB::Mode mode = BaseTLB::Read; 430 431 if (traceData) 432 traceData->setMem(addr, size, flags); 433 434 RequestPtr req = new Request(asid, addr, size, 435 flags, dataMasterId(), pc, 436 thread->contextId(), tid); 437 438 req->taskId(taskId()); 439 440 Addr split_addr = roundDown(addr + size - 1, block_size); 441 assert(split_addr <= addr || split_addr - addr < block_size); 442 443 _status = DTBWaitResponse; 444 if (split_addr > addr) { 445 RequestPtr req1, req2; 446 assert(!req->isLLSC() && !req->isSwap()); 447 req->splitOnVaddr(split_addr, req1, req2); 448 449 WholeTranslationState *state = 450 new WholeTranslationState(req, req1, req2, new uint8_t[size], 451 NULL, mode); 452 DataTranslation<TimingSimpleCPU *> *trans1 = 453 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 454 DataTranslation<TimingSimpleCPU *> *trans2 = 455 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 456 457 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 458 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 459 } else { 460 WholeTranslationState *state = 461 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 462 DataTranslation<TimingSimpleCPU *> *translation 463 = new DataTranslation<TimingSimpleCPU *>(this, state); 464 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 465 } 466 467 return NoFault; 468} 469 470bool 471TimingSimpleCPU::handleWritePacket() 472{ 473 SimpleExecContext &t_info = *threadInfo[curThread]; 474 SimpleThread* thread = t_info.thread; 475 476 RequestPtr req = dcache_pkt->req; 477 if (req->isMmappedIpr()) { 478 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 479 new IprEvent(dcache_pkt, this, clockEdge(delay)); 480 _status = DcacheWaitResponse; 481 dcache_pkt = NULL; 482 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 483 _status = DcacheRetry; 484 } else { 485 _status = DcacheWaitResponse; 486 // memory system takes ownership of packet 487 dcache_pkt = NULL; 488 } 489 return dcache_pkt == NULL; 490} 491 492Fault 493TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 494 Addr addr, unsigned flags, uint64_t *res) 495{ 496 SimpleExecContext &t_info = *threadInfo[curThread]; 497 SimpleThread* thread = t_info.thread; 498 499 uint8_t *newData = new uint8_t[size]; 500 const int asid = 0; 501 const ThreadID tid = curThread; 502 const Addr pc = thread->instAddr(); 503 unsigned block_size = cacheLineSize(); 504 BaseTLB::Mode mode = BaseTLB::Write; 505 506 if (data == NULL) { 507 assert(flags & Request::CACHE_BLOCK_ZERO); 508 // This must be a cache block cleaning request 509 memset(newData, 0, size); 510 } else { 511 memcpy(newData, data, size); 512 } 513 514 if (traceData) 515 traceData->setMem(addr, size, flags); 516 517 RequestPtr req = new Request(asid, addr, size, 518 flags, dataMasterId(), pc, 519 thread->contextId(), tid); 520 521 req->taskId(taskId()); 522 523 Addr split_addr = roundDown(addr + size - 1, block_size); 524 assert(split_addr <= addr || split_addr - addr < block_size); 525 526 _status = DTBWaitResponse; 527 if (split_addr > addr) { 528 RequestPtr req1, req2; 529 assert(!req->isLLSC() && !req->isSwap()); 530 req->splitOnVaddr(split_addr, req1, req2); 531 532 WholeTranslationState *state = 533 new WholeTranslationState(req, req1, req2, newData, res, mode); 534 DataTranslation<TimingSimpleCPU *> *trans1 = 535 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 536 DataTranslation<TimingSimpleCPU *> *trans2 = 537 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 538 539 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 540 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 541 } else { 542 WholeTranslationState *state = 543 new WholeTranslationState(req, newData, res, mode); 544 DataTranslation<TimingSimpleCPU *> *translation = 545 new DataTranslation<TimingSimpleCPU *>(this, state); 546 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 547 } 548 549 // Translation faults will be returned via finishTranslation() 550 return NoFault; 551} 552 553void 554TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 555{ 556 for (ThreadID tid = 0; tid < numThreads; tid++) { 557 if (tid != sender) { 558 if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 559 wakeup(tid); 560 } 561 TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 562 dcachePort.cacheBlockMask); 563 } 564 } 565} 566 567void 568TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 569{ 570 _status = BaseSimpleCPU::Running; 571 572 if (state->getFault() != NoFault) { 573 if (state->isPrefetch()) { 574 state->setNoFault(); 575 } 576 delete [] state->data; 577 state->deleteReqs(); 578 translationFault(state->getFault()); 579 } else { 580 if (!state->isSplit) { 581 sendData(state->mainReq, state->data, state->res, 582 state->mode == BaseTLB::Read); 583 } else { 584 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 585 state->data, state->mode == BaseTLB::Read); 586 } 587 } 588 589 delete state; 590} 591 592 593void 594TimingSimpleCPU::fetch() 595{ 596 // Change thread if multi-threaded 597 swapActiveThread(); 598 599 SimpleExecContext &t_info = *threadInfo[curThread]; 600 SimpleThread* thread = t_info.thread; 601 602 DPRINTF(SimpleCPU, "Fetch\n"); 603 604 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 605 checkForInterrupts(); 606 checkPcEventQueue(); 607 } 608 609 // We must have just got suspended by a PC event 610 if (_status == Idle) 611 return; 612 613 TheISA::PCState pcState = thread->pcState(); 614 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 615 !curMacroStaticInst; 616 617 if (needToFetch) { 618 _status = BaseSimpleCPU::Running; 619 Request *ifetch_req = new Request(); 620 ifetch_req->taskId(taskId()); 621 ifetch_req->setThreadContext(thread->contextId(), curThread); 622 setupFetchRequest(ifetch_req); 623 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 624 thread->itb->translateTiming(ifetch_req, thread->getTC(), 625 &fetchTranslation, BaseTLB::Execute); 626 } else { 627 _status = IcacheWaitResponse; 628 completeIfetch(NULL); 629 630 updateCycleCounts(); 631 } 632} 633 634 635void 636TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 637 ThreadContext *tc) 638{ 639 if (fault == NoFault) { 640 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 641 req->getVaddr(), req->getPaddr()); 642 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 643 ifetch_pkt->dataStatic(&inst); 644 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 645 646 if (!icachePort.sendTimingReq(ifetch_pkt)) { 647 // Need to wait for retry 648 _status = IcacheRetry; 649 } else { 650 // Need to wait for cache to respond 651 _status = IcacheWaitResponse; 652 // ownership of packet transferred to memory system 653 ifetch_pkt = NULL; 654 } 655 } else { 656 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 657 delete req; 658 // fetch fault: advance directly to next instruction (fault handler) 659 _status = BaseSimpleCPU::Running; 660 advanceInst(fault); 661 } 662 663 updateCycleCounts(); 664} 665 666 667void 668TimingSimpleCPU::advanceInst(const Fault &fault) 669{ 670 SimpleExecContext &t_info = *threadInfo[curThread]; 671 672 if (_status == Faulting) 673 return; 674 675 if (fault != NoFault) { 676 advancePC(fault); 677 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 678 reschedule(fetchEvent, clockEdge(), true); 679 _status = Faulting; 680 return; 681 } 682 683 684 if (!t_info.stayAtPC) 685 advancePC(fault); 686 687 if (tryCompleteDrain()) 688 return; 689 690 if (_status == BaseSimpleCPU::Running) { 691 // kick off fetch of next instruction... callback from icache 692 // response will cause that instruction to be executed, 693 // keeping the CPU running. 694 fetch(); 695 } 696} 697 698 699void 700TimingSimpleCPU::completeIfetch(PacketPtr pkt) 701{ 702 SimpleExecContext& t_info = *threadInfo[curThread]; 703 704 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 705 pkt->getAddr() : 0); 706 707 // received a response from the icache: execute the received 708 // instruction 709 assert(!pkt || !pkt->isError()); 710 assert(_status == IcacheWaitResponse); 711 712 _status = BaseSimpleCPU::Running; 713 714 updateCycleCounts(); 715 716 if (pkt) 717 pkt->req->setAccessLatency(); 718 719 720 preExecute(); 721 if (curStaticInst && curStaticInst->isMemRef()) { 722 // load or store: just send to dcache 723 Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 724 725 // If we're not running now the instruction will complete in a dcache 726 // response callback or the instruction faulted and has started an 727 // ifetch 728 if (_status == BaseSimpleCPU::Running) { 729 if (fault != NoFault && traceData) { 730 // If there was a fault, we shouldn't trace this instruction. 731 delete traceData; 732 traceData = NULL; 733 } 734 735 postExecute(); 736 // @todo remove me after debugging with legion done 737 if (curStaticInst && (!curStaticInst->isMicroop() || 738 curStaticInst->isFirstMicroop())) 739 instCnt++; 740 advanceInst(fault); 741 } 742 } else if (curStaticInst) { 743 // non-memory instruction: execute completely now 744 Fault fault = curStaticInst->execute(&t_info, traceData); 745 746 // keep an instruction count 747 if (fault == NoFault) 748 countInst(); 749 else if (traceData && !DTRACE(ExecFaulting)) { 750 delete traceData; 751 traceData = NULL; 752 } 753 754 postExecute(); 755 // @todo remove me after debugging with legion done 756 if (curStaticInst && (!curStaticInst->isMicroop() || 757 curStaticInst->isFirstMicroop())) 758 instCnt++; 759 advanceInst(fault); 760 } else { 761 advanceInst(NoFault); 762 } 763 764 if (pkt) { 765 delete pkt->req; 766 delete pkt; 767 } 768} 769 770void 771TimingSimpleCPU::IcachePort::ITickEvent::process() 772{ 773 cpu->completeIfetch(pkt); 774} 775 776bool 777TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 778{ 779 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 780 // we should only ever see one response per cycle since we only 781 // issue a new request once this response is sunk 782 assert(!tickEvent.scheduled()); 783 // delay processing of returned data until next CPU clock edge 784 tickEvent.schedule(pkt, cpu->clockEdge()); 785 786 return true; 787} 788 789void 790TimingSimpleCPU::IcachePort::recvReqRetry() 791{ 792 // we shouldn't get a retry unless we have a packet that we're 793 // waiting to transmit 794 assert(cpu->ifetch_pkt != NULL); 795 assert(cpu->_status == IcacheRetry); 796 PacketPtr tmp = cpu->ifetch_pkt; 797 if (sendTimingReq(tmp)) { 798 cpu->_status = IcacheWaitResponse; 799 cpu->ifetch_pkt = NULL; 800 } 801} 802 803void 804TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 805{ 806 // received a response from the dcache: complete the load or store 807 // instruction 808 assert(!pkt->isError()); 809 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 810 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 811 812 pkt->req->setAccessLatency(); 813 814 updateCycleCounts(); 815 816 if (pkt->senderState) { 817 SplitFragmentSenderState * send_state = 818 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 819 assert(send_state); 820 delete pkt->req; 821 delete pkt; 822 PacketPtr big_pkt = send_state->bigPkt; 823 delete send_state; 824 825 SplitMainSenderState * main_send_state = 826 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 827 assert(main_send_state); 828 // Record the fact that this packet is no longer outstanding. 829 assert(main_send_state->outstanding != 0); 830 main_send_state->outstanding--; 831 832 if (main_send_state->outstanding) { 833 return; 834 } else { 835 delete main_send_state; 836 big_pkt->senderState = NULL; 837 pkt = big_pkt; 838 } 839 } 840 841 _status = BaseSimpleCPU::Running; 842 843 Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 844 traceData); 845 846 // keep an instruction count 847 if (fault == NoFault) 848 countInst(); 849 else if (traceData) { 850 // If there was a fault, we shouldn't trace this instruction. 851 delete traceData; 852 traceData = NULL; 853 } 854 855 delete pkt->req; 856 delete pkt; 857 858 postExecute(); 859 860 advanceInst(fault); 861} 862 863void 864TimingSimpleCPU::updateCycleCounts() 865{ 866 const Cycles delta(curCycle() - previousCycle); 867 868 numCycles += delta; 869 ppCycles->notify(delta); 870 871 previousCycle = curCycle(); 872} 873 874void 875TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 876{ 877 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 878 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 879 cpu->wakeup(tid); 880 } 881 } 882 883 // Making it uniform across all CPUs: 884 // The CPUs need to be woken up only on an invalidation packet (when using caches) 885 // or on an incoming write packet (when not using caches) 886 // It is not necessary to wake up the processor on all incoming packets 887 if (pkt->isInvalidate() || pkt->isWrite()) { 888 for (auto &t_info : cpu->threadInfo) { 889 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 890 } 891 } 892} 893 894void 895TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 896{ 897 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 898 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 899 cpu->wakeup(tid); 900 } 901 } 902} 903 904bool 905TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 906{ 907 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 908 909 // The timing CPU is not really ticked, instead it relies on the 910 // memory system (fetch and load/store) to set the pace. 911 if (!tickEvent.scheduled()) { 912 // Delay processing of returned data until next CPU clock edge 913 tickEvent.schedule(pkt, cpu->clockEdge()); 914 return true; 915 } else { 916 // In the case of a split transaction and a cache that is 917 // faster than a CPU we could get two responses in the 918 // same tick, delay the second one 919 if (!retryRespEvent.scheduled()) 920 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 921 return false; 922 } 923} 924 925void 926TimingSimpleCPU::DcachePort::DTickEvent::process() 927{ 928 cpu->completeDataAccess(pkt); 929} 930 931void 932TimingSimpleCPU::DcachePort::recvReqRetry() 933{ 934 // we shouldn't get a retry unless we have a packet that we're 935 // waiting to transmit 936 assert(cpu->dcache_pkt != NULL); 937 assert(cpu->_status == DcacheRetry); 938 PacketPtr tmp = cpu->dcache_pkt; 939 if (tmp->senderState) { 940 // This is a packet from a split access. 941 SplitFragmentSenderState * send_state = 942 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 943 assert(send_state); 944 PacketPtr big_pkt = send_state->bigPkt; 945 946 SplitMainSenderState * main_send_state = 947 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 948 assert(main_send_state); 949 950 if (sendTimingReq(tmp)) { 951 // If we were able to send without retrying, record that fact 952 // and try sending the other fragment. 953 send_state->clearFromParent(); 954 int other_index = main_send_state->getPendingFragment(); 955 if (other_index > 0) { 956 tmp = main_send_state->fragments[other_index]; 957 cpu->dcache_pkt = tmp; 958 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 959 (big_pkt->isWrite() && cpu->handleWritePacket())) { 960 main_send_state->fragments[other_index] = NULL; 961 } 962 } else { 963 cpu->_status = DcacheWaitResponse; 964 // memory system takes ownership of packet 965 cpu->dcache_pkt = NULL; 966 } 967 } 968 } else if (sendTimingReq(tmp)) { 969 cpu->_status = DcacheWaitResponse; 970 // memory system takes ownership of packet 971 cpu->dcache_pkt = NULL; 972 } 973} 974 975TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 976 Tick t) 977 : pkt(_pkt), cpu(_cpu) 978{ 979 cpu->schedule(this, t); 980} 981 982void 983TimingSimpleCPU::IprEvent::process() 984{ 985 cpu->completeDataAccess(pkt); 986} 987 988const char * 989TimingSimpleCPU::IprEvent::description() const 990{ 991 return "Timing Simple CPU Delay IPR event"; 992} 993 994 995void 996TimingSimpleCPU::printAddr(Addr a) 997{ 998 dcachePort.printAddr(a); 999} 1000 1001 1002//////////////////////////////////////////////////////////////////////// 1003// 1004// TimingSimpleCPU Simulation Object 1005// 1006TimingSimpleCPU * 1007TimingSimpleCPUParams::create() 1008{ 1009 return new TimingSimpleCPU(this); 1010} 1011