timing.cc revision 11148:1bc3d93c7eaa
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013,2015 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/locked_mem.hh" 45#include "arch/mmapped_ipr.hh" 46#include "arch/utility.hh" 47#include "base/bigint.hh" 48#include "config/the_isa.hh" 49#include "cpu/simple/timing.hh" 50#include "cpu/exetrace.hh" 51#include "debug/Config.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/SimpleCPU.hh" 55#include "mem/packet.hh" 56#include "mem/packet_access.hh" 57#include "params/TimingSimpleCPU.hh" 58#include "sim/faults.hh" 59#include "sim/full_system.hh" 60#include "sim/system.hh" 61 62#include "debug/Mwait.hh" 63 64using namespace std; 65using namespace TheISA; 66 67void 68TimingSimpleCPU::init() 69{ 70 BaseSimpleCPU::init(); 71} 72 73void 74TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 75{ 76 pkt = _pkt; 77 cpu->schedule(this, t); 78} 79 80TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 81 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 82 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 83 fetchEvent(this) 84{ 85 _status = Idle; 86} 87 88 89 90TimingSimpleCPU::~TimingSimpleCPU() 91{ 92} 93 94DrainState 95TimingSimpleCPU::drain() 96{ 97 if (switchedOut()) 98 return DrainState::Drained; 99 100 if (_status == Idle || 101 (_status == BaseSimpleCPU::Running && isDrained())) { 102 DPRINTF(Drain, "No need to drain.\n"); 103 activeThreads.clear(); 104 return DrainState::Drained; 105 } else { 106 DPRINTF(Drain, "Requesting drain.\n"); 107 108 // The fetch event can become descheduled if a drain didn't 109 // succeed on the first attempt. We need to reschedule it if 110 // the CPU is waiting for a microcode routine to complete. 111 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 112 schedule(fetchEvent, clockEdge()); 113 114 return DrainState::Draining; 115 } 116} 117 118void 119TimingSimpleCPU::drainResume() 120{ 121 assert(!fetchEvent.scheduled()); 122 if (switchedOut()) 123 return; 124 125 DPRINTF(SimpleCPU, "Resume\n"); 126 verifyMemoryMode(); 127 128 assert(!threadContexts.empty()); 129 130 _status = BaseSimpleCPU::Idle; 131 132 for (ThreadID tid = 0; tid < numThreads; tid++) { 133 if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 134 threadInfo[tid]->notIdleFraction = 1; 135 136 activeThreads.push_back(tid); 137 138 _status = BaseSimpleCPU::Running; 139 140 // Fetch if any threads active 141 if (!fetchEvent.scheduled()) { 142 schedule(fetchEvent, nextCycle()); 143 } 144 } else { 145 threadInfo[tid]->notIdleFraction = 0; 146 } 147 } 148 149 system->totalNumInsts = 0; 150} 151 152bool 153TimingSimpleCPU::tryCompleteDrain() 154{ 155 if (drainState() != DrainState::Draining) 156 return false; 157 158 DPRINTF(Drain, "tryCompleteDrain.\n"); 159 if (!isDrained()) 160 return false; 161 162 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 163 signalDrainDone(); 164 165 return true; 166} 167 168void 169TimingSimpleCPU::switchOut() 170{ 171 SimpleExecContext& t_info = *threadInfo[curThread]; 172 M5_VAR_USED SimpleThread* thread = t_info.thread; 173 174 BaseSimpleCPU::switchOut(); 175 176 assert(!fetchEvent.scheduled()); 177 assert(_status == BaseSimpleCPU::Running || _status == Idle); 178 assert(!t_info.stayAtPC); 179 assert(thread->microPC() == 0); 180 181 updateCycleCounts(); 182} 183 184 185void 186TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 187{ 188 BaseSimpleCPU::takeOverFrom(oldCPU); 189 190 previousCycle = curCycle(); 191} 192 193void 194TimingSimpleCPU::verifyMemoryMode() const 195{ 196 if (!system->isTimingMode()) { 197 fatal("The timing CPU requires the memory system to be in " 198 "'timing' mode.\n"); 199 } 200} 201 202void 203TimingSimpleCPU::activateContext(ThreadID thread_num) 204{ 205 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 206 207 assert(thread_num < numThreads); 208 209 threadInfo[thread_num]->notIdleFraction = 1; 210 if (_status == BaseSimpleCPU::Idle) 211 _status = BaseSimpleCPU::Running; 212 213 // kick things off by initiating the fetch of the next instruction 214 if (!fetchEvent.scheduled()) 215 schedule(fetchEvent, clockEdge(Cycles(0))); 216 217 if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 218 == activeThreads.end()) { 219 activeThreads.push_back(thread_num); 220 } 221} 222 223 224void 225TimingSimpleCPU::suspendContext(ThreadID thread_num) 226{ 227 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 228 229 assert(thread_num < numThreads); 230 activeThreads.remove(thread_num); 231 232 if (_status == Idle) 233 return; 234 235 assert(_status == BaseSimpleCPU::Running); 236 237 threadInfo[thread_num]->notIdleFraction = 0; 238 239 if (activeThreads.empty()) { 240 _status = Idle; 241 242 if (fetchEvent.scheduled()) { 243 deschedule(fetchEvent); 244 } 245 } 246} 247 248bool 249TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 250{ 251 SimpleExecContext &t_info = *threadInfo[curThread]; 252 SimpleThread* thread = t_info.thread; 253 254 RequestPtr req = pkt->req; 255 256 // We're about the issues a locked load, so tell the monitor 257 // to start caring about this address 258 if (pkt->isRead() && pkt->req->isLLSC()) { 259 TheISA::handleLockedRead(thread, pkt->req); 260 } 261 if (req->isMmappedIpr()) { 262 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 263 new IprEvent(pkt, this, clockEdge(delay)); 264 _status = DcacheWaitResponse; 265 dcache_pkt = NULL; 266 } else if (!dcachePort.sendTimingReq(pkt)) { 267 _status = DcacheRetry; 268 dcache_pkt = pkt; 269 } else { 270 _status = DcacheWaitResponse; 271 // memory system takes ownership of packet 272 dcache_pkt = NULL; 273 } 274 return dcache_pkt == NULL; 275} 276 277void 278TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 279 bool read) 280{ 281 SimpleExecContext &t_info = *threadInfo[curThread]; 282 SimpleThread* thread = t_info.thread; 283 284 PacketPtr pkt = buildPacket(req, read); 285 pkt->dataDynamic<uint8_t>(data); 286 if (req->getFlags().isSet(Request::NO_ACCESS)) { 287 assert(!dcache_pkt); 288 pkt->makeResponse(); 289 completeDataAccess(pkt); 290 } else if (read) { 291 handleReadPacket(pkt); 292 } else { 293 bool do_access = true; // flag to suppress cache access 294 295 if (req->isLLSC()) { 296 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 297 } else if (req->isCondSwap()) { 298 assert(res); 299 req->setExtraData(*res); 300 } 301 302 if (do_access) { 303 dcache_pkt = pkt; 304 handleWritePacket(); 305 threadSnoop(pkt, curThread); 306 } else { 307 _status = DcacheWaitResponse; 308 completeDataAccess(pkt); 309 } 310 } 311} 312 313void 314TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 315 RequestPtr req, uint8_t *data, bool read) 316{ 317 PacketPtr pkt1, pkt2; 318 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 319 if (req->getFlags().isSet(Request::NO_ACCESS)) { 320 assert(!dcache_pkt); 321 pkt1->makeResponse(); 322 completeDataAccess(pkt1); 323 } else if (read) { 324 SplitFragmentSenderState * send_state = 325 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 326 if (handleReadPacket(pkt1)) { 327 send_state->clearFromParent(); 328 send_state = dynamic_cast<SplitFragmentSenderState *>( 329 pkt2->senderState); 330 if (handleReadPacket(pkt2)) { 331 send_state->clearFromParent(); 332 } 333 } 334 } else { 335 dcache_pkt = pkt1; 336 SplitFragmentSenderState * send_state = 337 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 338 if (handleWritePacket()) { 339 send_state->clearFromParent(); 340 dcache_pkt = pkt2; 341 send_state = dynamic_cast<SplitFragmentSenderState *>( 342 pkt2->senderState); 343 if (handleWritePacket()) { 344 send_state->clearFromParent(); 345 } 346 } 347 } 348} 349 350void 351TimingSimpleCPU::translationFault(const Fault &fault) 352{ 353 // fault may be NoFault in cases where a fault is suppressed, 354 // for instance prefetches. 355 updateCycleCounts(); 356 357 if (traceData) { 358 // Since there was a fault, we shouldn't trace this instruction. 359 delete traceData; 360 traceData = NULL; 361 } 362 363 postExecute(); 364 365 advanceInst(fault); 366} 367 368PacketPtr 369TimingSimpleCPU::buildPacket(RequestPtr req, bool read) 370{ 371 return read ? Packet::createRead(req) : Packet::createWrite(req); 372} 373 374void 375TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 376 RequestPtr req1, RequestPtr req2, RequestPtr req, 377 uint8_t *data, bool read) 378{ 379 pkt1 = pkt2 = NULL; 380 381 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 382 383 if (req->getFlags().isSet(Request::NO_ACCESS)) { 384 pkt1 = buildPacket(req, read); 385 return; 386 } 387 388 pkt1 = buildPacket(req1, read); 389 pkt2 = buildPacket(req2, read); 390 391 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 392 393 pkt->dataDynamic<uint8_t>(data); 394 pkt1->dataStatic<uint8_t>(data); 395 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 396 397 SplitMainSenderState * main_send_state = new SplitMainSenderState; 398 pkt->senderState = main_send_state; 399 main_send_state->fragments[0] = pkt1; 400 main_send_state->fragments[1] = pkt2; 401 main_send_state->outstanding = 2; 402 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 403 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 404} 405 406Fault 407TimingSimpleCPU::readMem(Addr addr, uint8_t *data, 408 unsigned size, unsigned flags) 409{ 410 SimpleExecContext &t_info = *threadInfo[curThread]; 411 SimpleThread* thread = t_info.thread; 412 413 Fault fault; 414 const int asid = 0; 415 const ThreadID tid = curThread; 416 const Addr pc = thread->instAddr(); 417 unsigned block_size = cacheLineSize(); 418 BaseTLB::Mode mode = BaseTLB::Read; 419 420 if (traceData) 421 traceData->setMem(addr, size, flags); 422 423 RequestPtr req = new Request(asid, addr, size, 424 flags, dataMasterId(), pc, 425 thread->contextId(), tid); 426 427 req->taskId(taskId()); 428 429 Addr split_addr = roundDown(addr + size - 1, block_size); 430 assert(split_addr <= addr || split_addr - addr < block_size); 431 432 _status = DTBWaitResponse; 433 if (split_addr > addr) { 434 RequestPtr req1, req2; 435 assert(!req->isLLSC() && !req->isSwap()); 436 req->splitOnVaddr(split_addr, req1, req2); 437 438 WholeTranslationState *state = 439 new WholeTranslationState(req, req1, req2, new uint8_t[size], 440 NULL, mode); 441 DataTranslation<TimingSimpleCPU *> *trans1 = 442 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 443 DataTranslation<TimingSimpleCPU *> *trans2 = 444 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 445 446 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 447 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 448 } else { 449 WholeTranslationState *state = 450 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 451 DataTranslation<TimingSimpleCPU *> *translation 452 = new DataTranslation<TimingSimpleCPU *>(this, state); 453 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 454 } 455 456 return NoFault; 457} 458 459bool 460TimingSimpleCPU::handleWritePacket() 461{ 462 SimpleExecContext &t_info = *threadInfo[curThread]; 463 SimpleThread* thread = t_info.thread; 464 465 RequestPtr req = dcache_pkt->req; 466 if (req->isMmappedIpr()) { 467 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 468 new IprEvent(dcache_pkt, this, clockEdge(delay)); 469 _status = DcacheWaitResponse; 470 dcache_pkt = NULL; 471 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 472 _status = DcacheRetry; 473 } else { 474 _status = DcacheWaitResponse; 475 // memory system takes ownership of packet 476 dcache_pkt = NULL; 477 } 478 return dcache_pkt == NULL; 479} 480 481Fault 482TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 483 Addr addr, unsigned flags, uint64_t *res) 484{ 485 SimpleExecContext &t_info = *threadInfo[curThread]; 486 SimpleThread* thread = t_info.thread; 487 488 uint8_t *newData = new uint8_t[size]; 489 const int asid = 0; 490 const ThreadID tid = curThread; 491 const Addr pc = thread->instAddr(); 492 unsigned block_size = cacheLineSize(); 493 BaseTLB::Mode mode = BaseTLB::Write; 494 495 if (data == NULL) { 496 assert(flags & Request::CACHE_BLOCK_ZERO); 497 // This must be a cache block cleaning request 498 memset(newData, 0, size); 499 } else { 500 memcpy(newData, data, size); 501 } 502 503 if (traceData) 504 traceData->setMem(addr, size, flags); 505 506 RequestPtr req = new Request(asid, addr, size, 507 flags, dataMasterId(), pc, 508 thread->contextId(), tid); 509 510 req->taskId(taskId()); 511 512 Addr split_addr = roundDown(addr + size - 1, block_size); 513 assert(split_addr <= addr || split_addr - addr < block_size); 514 515 _status = DTBWaitResponse; 516 if (split_addr > addr) { 517 RequestPtr req1, req2; 518 assert(!req->isLLSC() && !req->isSwap()); 519 req->splitOnVaddr(split_addr, req1, req2); 520 521 WholeTranslationState *state = 522 new WholeTranslationState(req, req1, req2, newData, res, mode); 523 DataTranslation<TimingSimpleCPU *> *trans1 = 524 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 525 DataTranslation<TimingSimpleCPU *> *trans2 = 526 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 527 528 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 529 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 530 } else { 531 WholeTranslationState *state = 532 new WholeTranslationState(req, newData, res, mode); 533 DataTranslation<TimingSimpleCPU *> *translation = 534 new DataTranslation<TimingSimpleCPU *>(this, state); 535 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 536 } 537 538 // Translation faults will be returned via finishTranslation() 539 return NoFault; 540} 541 542void 543TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 544{ 545 for (ThreadID tid = 0; tid < numThreads; tid++) { 546 if (tid != sender) { 547 if(getCpuAddrMonitor(tid)->doMonitor(pkt)) { 548 wakeup(); 549 } 550 TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 551 dcachePort.cacheBlockMask); 552 } 553 } 554} 555 556void 557TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 558{ 559 _status = BaseSimpleCPU::Running; 560 561 if (state->getFault() != NoFault) { 562 if (state->isPrefetch()) { 563 state->setNoFault(); 564 } 565 delete [] state->data; 566 state->deleteReqs(); 567 translationFault(state->getFault()); 568 } else { 569 if (!state->isSplit) { 570 sendData(state->mainReq, state->data, state->res, 571 state->mode == BaseTLB::Read); 572 } else { 573 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 574 state->data, state->mode == BaseTLB::Read); 575 } 576 } 577 578 delete state; 579} 580 581 582void 583TimingSimpleCPU::fetch() 584{ 585 // Change thread if multi-threaded 586 swapActiveThread(); 587 588 SimpleExecContext &t_info = *threadInfo[curThread]; 589 SimpleThread* thread = t_info.thread; 590 591 DPRINTF(SimpleCPU, "Fetch\n"); 592 593 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 594 checkForInterrupts(); 595 checkPcEventQueue(); 596 } 597 598 // We must have just got suspended by a PC event 599 if (_status == Idle) 600 return; 601 602 TheISA::PCState pcState = thread->pcState(); 603 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 604 !curMacroStaticInst; 605 606 if (needToFetch) { 607 _status = BaseSimpleCPU::Running; 608 Request *ifetch_req = new Request(); 609 ifetch_req->taskId(taskId()); 610 ifetch_req->setThreadContext(thread->contextId(), curThread); 611 setupFetchRequest(ifetch_req); 612 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 613 thread->itb->translateTiming(ifetch_req, thread->getTC(), 614 &fetchTranslation, BaseTLB::Execute); 615 } else { 616 _status = IcacheWaitResponse; 617 completeIfetch(NULL); 618 619 updateCycleCounts(); 620 } 621} 622 623 624void 625TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 626 ThreadContext *tc) 627{ 628 if (fault == NoFault) { 629 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 630 req->getVaddr(), req->getPaddr()); 631 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 632 ifetch_pkt->dataStatic(&inst); 633 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 634 635 if (!icachePort.sendTimingReq(ifetch_pkt)) { 636 // Need to wait for retry 637 _status = IcacheRetry; 638 } else { 639 // Need to wait for cache to respond 640 _status = IcacheWaitResponse; 641 // ownership of packet transferred to memory system 642 ifetch_pkt = NULL; 643 } 644 } else { 645 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 646 delete req; 647 // fetch fault: advance directly to next instruction (fault handler) 648 _status = BaseSimpleCPU::Running; 649 advanceInst(fault); 650 } 651 652 updateCycleCounts(); 653} 654 655 656void 657TimingSimpleCPU::advanceInst(const Fault &fault) 658{ 659 SimpleExecContext &t_info = *threadInfo[curThread]; 660 661 if (_status == Faulting) 662 return; 663 664 if (fault != NoFault) { 665 advancePC(fault); 666 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 667 reschedule(fetchEvent, clockEdge(), true); 668 _status = Faulting; 669 return; 670 } 671 672 673 if (!t_info.stayAtPC) 674 advancePC(fault); 675 676 if (tryCompleteDrain()) 677 return; 678 679 if (_status == BaseSimpleCPU::Running) { 680 // kick off fetch of next instruction... callback from icache 681 // response will cause that instruction to be executed, 682 // keeping the CPU running. 683 fetch(); 684 } 685} 686 687 688void 689TimingSimpleCPU::completeIfetch(PacketPtr pkt) 690{ 691 SimpleExecContext& t_info = *threadInfo[curThread]; 692 693 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 694 pkt->getAddr() : 0); 695 696 // received a response from the icache: execute the received 697 // instruction 698 assert(!pkt || !pkt->isError()); 699 assert(_status == IcacheWaitResponse); 700 701 _status = BaseSimpleCPU::Running; 702 703 updateCycleCounts(); 704 705 if (pkt) 706 pkt->req->setAccessLatency(); 707 708 709 preExecute(); 710 if (curStaticInst && curStaticInst->isMemRef()) { 711 // load or store: just send to dcache 712 Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 713 714 // If we're not running now the instruction will complete in a dcache 715 // response callback or the instruction faulted and has started an 716 // ifetch 717 if (_status == BaseSimpleCPU::Running) { 718 if (fault != NoFault && traceData) { 719 // If there was a fault, we shouldn't trace this instruction. 720 delete traceData; 721 traceData = NULL; 722 } 723 724 postExecute(); 725 // @todo remove me after debugging with legion done 726 if (curStaticInst && (!curStaticInst->isMicroop() || 727 curStaticInst->isFirstMicroop())) 728 instCnt++; 729 advanceInst(fault); 730 } 731 } else if (curStaticInst) { 732 // non-memory instruction: execute completely now 733 Fault fault = curStaticInst->execute(&t_info, traceData); 734 735 // keep an instruction count 736 if (fault == NoFault) 737 countInst(); 738 else if (traceData && !DTRACE(ExecFaulting)) { 739 delete traceData; 740 traceData = NULL; 741 } 742 743 postExecute(); 744 // @todo remove me after debugging with legion done 745 if (curStaticInst && (!curStaticInst->isMicroop() || 746 curStaticInst->isFirstMicroop())) 747 instCnt++; 748 advanceInst(fault); 749 } else { 750 advanceInst(NoFault); 751 } 752 753 if (pkt) { 754 delete pkt->req; 755 delete pkt; 756 } 757} 758 759void 760TimingSimpleCPU::IcachePort::ITickEvent::process() 761{ 762 cpu->completeIfetch(pkt); 763} 764 765bool 766TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 767{ 768 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 769 // we should only ever see one response per cycle since we only 770 // issue a new request once this response is sunk 771 assert(!tickEvent.scheduled()); 772 // delay processing of returned data until next CPU clock edge 773 tickEvent.schedule(pkt, cpu->clockEdge()); 774 775 return true; 776} 777 778void 779TimingSimpleCPU::IcachePort::recvReqRetry() 780{ 781 // we shouldn't get a retry unless we have a packet that we're 782 // waiting to transmit 783 assert(cpu->ifetch_pkt != NULL); 784 assert(cpu->_status == IcacheRetry); 785 PacketPtr tmp = cpu->ifetch_pkt; 786 if (sendTimingReq(tmp)) { 787 cpu->_status = IcacheWaitResponse; 788 cpu->ifetch_pkt = NULL; 789 } 790} 791 792void 793TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 794{ 795 // received a response from the dcache: complete the load or store 796 // instruction 797 assert(!pkt->isError()); 798 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 799 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 800 801 pkt->req->setAccessLatency(); 802 803 updateCycleCounts(); 804 805 if (pkt->senderState) { 806 SplitFragmentSenderState * send_state = 807 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 808 assert(send_state); 809 delete pkt->req; 810 delete pkt; 811 PacketPtr big_pkt = send_state->bigPkt; 812 delete send_state; 813 814 SplitMainSenderState * main_send_state = 815 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 816 assert(main_send_state); 817 // Record the fact that this packet is no longer outstanding. 818 assert(main_send_state->outstanding != 0); 819 main_send_state->outstanding--; 820 821 if (main_send_state->outstanding) { 822 return; 823 } else { 824 delete main_send_state; 825 big_pkt->senderState = NULL; 826 pkt = big_pkt; 827 } 828 } 829 830 _status = BaseSimpleCPU::Running; 831 832 Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 833 traceData); 834 835 // keep an instruction count 836 if (fault == NoFault) 837 countInst(); 838 else if (traceData) { 839 // If there was a fault, we shouldn't trace this instruction. 840 delete traceData; 841 traceData = NULL; 842 } 843 844 delete pkt->req; 845 delete pkt; 846 847 postExecute(); 848 849 advanceInst(fault); 850} 851 852void 853TimingSimpleCPU::updateCycleCounts() 854{ 855 const Cycles delta(curCycle() - previousCycle); 856 857 numCycles += delta; 858 ppCycles->notify(delta); 859 860 previousCycle = curCycle(); 861} 862 863void 864TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 865{ 866 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 867 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 868 cpu->wakeup(); 869 } 870 } 871 872 for (auto &t_info : cpu->threadInfo) { 873 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 874 } 875} 876 877void 878TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 879{ 880 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 881 if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 882 cpu->wakeup(); 883 } 884 } 885} 886 887bool 888TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 889{ 890 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 891 892 // The timing CPU is not really ticked, instead it relies on the 893 // memory system (fetch and load/store) to set the pace. 894 if (!tickEvent.scheduled()) { 895 // Delay processing of returned data until next CPU clock edge 896 tickEvent.schedule(pkt, cpu->clockEdge()); 897 return true; 898 } else { 899 // In the case of a split transaction and a cache that is 900 // faster than a CPU we could get two responses in the 901 // same tick, delay the second one 902 if (!retryRespEvent.scheduled()) 903 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 904 return false; 905 } 906} 907 908void 909TimingSimpleCPU::DcachePort::DTickEvent::process() 910{ 911 cpu->completeDataAccess(pkt); 912} 913 914void 915TimingSimpleCPU::DcachePort::recvReqRetry() 916{ 917 // we shouldn't get a retry unless we have a packet that we're 918 // waiting to transmit 919 assert(cpu->dcache_pkt != NULL); 920 assert(cpu->_status == DcacheRetry); 921 PacketPtr tmp = cpu->dcache_pkt; 922 if (tmp->senderState) { 923 // This is a packet from a split access. 924 SplitFragmentSenderState * send_state = 925 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 926 assert(send_state); 927 PacketPtr big_pkt = send_state->bigPkt; 928 929 SplitMainSenderState * main_send_state = 930 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 931 assert(main_send_state); 932 933 if (sendTimingReq(tmp)) { 934 // If we were able to send without retrying, record that fact 935 // and try sending the other fragment. 936 send_state->clearFromParent(); 937 int other_index = main_send_state->getPendingFragment(); 938 if (other_index > 0) { 939 tmp = main_send_state->fragments[other_index]; 940 cpu->dcache_pkt = tmp; 941 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 942 (big_pkt->isWrite() && cpu->handleWritePacket())) { 943 main_send_state->fragments[other_index] = NULL; 944 } 945 } else { 946 cpu->_status = DcacheWaitResponse; 947 // memory system takes ownership of packet 948 cpu->dcache_pkt = NULL; 949 } 950 } 951 } else if (sendTimingReq(tmp)) { 952 cpu->_status = DcacheWaitResponse; 953 // memory system takes ownership of packet 954 cpu->dcache_pkt = NULL; 955 } 956} 957 958TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 959 Tick t) 960 : pkt(_pkt), cpu(_cpu) 961{ 962 cpu->schedule(this, t); 963} 964 965void 966TimingSimpleCPU::IprEvent::process() 967{ 968 cpu->completeDataAccess(pkt); 969} 970 971const char * 972TimingSimpleCPU::IprEvent::description() const 973{ 974 return "Timing Simple CPU Delay IPR event"; 975} 976 977 978void 979TimingSimpleCPU::printAddr(Addr a) 980{ 981 dcachePort.printAddr(a); 982} 983 984 985//////////////////////////////////////////////////////////////////////// 986// 987// TimingSimpleCPU Simulation Object 988// 989TimingSimpleCPU * 990TimingSimpleCPUParams::create() 991{ 992 return new TimingSimpleCPU(this); 993} 994