timing.cc revision 9523
12623SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528232Snate@binkert.org#include "debug/ExecFaulting.hh" 538232Snate@binkert.org#include "debug/SimpleCPU.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 553348Sbinkertn@umich.edu#include "mem/packet_access.hh" 564762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 577678Sgblack@eecs.umich.edu#include "sim/faults.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592901Ssaidi@eecs.umich.edu#include "sim/system.hh" 602623SN/A 612623SN/Ausing namespace std; 622623SN/Ausing namespace TheISA; 632623SN/A 642623SN/Avoid 652623SN/ATimingSimpleCPU::init() 662623SN/A{ 672623SN/A BaseCPU::init(); 688921Sandreas.hansson@arm.com 698921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 708921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 718921Sandreas.hansson@arm.com 729433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 738779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 748779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 758779Sgblack@eecs.umich.edu // initialize CPU, including PC 768779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 778779Sgblack@eecs.umich.edu } 782623SN/A } 792623SN/A} 802623SN/A 812623SN/Avoid 828707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 832948Ssaidi@eecs.umich.edu{ 842948Ssaidi@eecs.umich.edu pkt = _pkt; 855606Snate@binkert.org cpu->schedule(this, t); 862948Ssaidi@eecs.umich.edu} 872948Ssaidi@eecs.umich.edu 885529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 898707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 909179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 919442SAndreas.Sandberg@ARM.com fetchEvent(this), drainManager(NULL) 922623SN/A{ 932623SN/A _status = Idle; 943647Srdreslin@umich.edu 957897Shestness@cs.utexas.edu system->totalNumInsts = 0; 962623SN/A} 972623SN/A 982623SN/A 992623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1002623SN/A{ 1012623SN/A} 1022623SN/A 1032901Ssaidi@eecs.umich.eduunsigned int 1049342SAndreas.Sandberg@arm.comTimingSimpleCPU::drain(DrainManager *drain_manager) 1052798Sktlim@umich.edu{ 1069448SAndreas.Sandberg@ARM.com assert(!drainManager); 1079448SAndreas.Sandberg@ARM.com if (switchedOut()) 1089448SAndreas.Sandberg@ARM.com return 0; 1099448SAndreas.Sandberg@ARM.com 1109342SAndreas.Sandberg@arm.com if (_status == Idle || 1119448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1129442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1139442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 1142901Ssaidi@eecs.umich.edu return 0; 1152798Sktlim@umich.edu } else { 1169342SAndreas.Sandberg@arm.com drainManager = drain_manager; 1179442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1189442SAndreas.Sandberg@ARM.com 1199442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1209442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1219442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1229448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1239442SAndreas.Sandberg@ARM.com schedule(fetchEvent, nextCycle()); 1249442SAndreas.Sandberg@ARM.com 1252901Ssaidi@eecs.umich.edu return 1; 1262798Sktlim@umich.edu } 1272623SN/A} 1282623SN/A 1292623SN/Avoid 1309342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1312623SN/A{ 1329442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1339448SAndreas.Sandberg@ARM.com assert(!drainManager); 1349448SAndreas.Sandberg@ARM.com if (switchedOut()) 1359448SAndreas.Sandberg@ARM.com return; 1369442SAndreas.Sandberg@ARM.com 1375221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1389523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1393201Shsul@eecs.umich.edu 1409448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1419448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1429448SAndreas.Sandberg@ARM.com fatal("The timing CPU only supports one thread.\n"); 1439448SAndreas.Sandberg@ARM.com 1449448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1455710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1469448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1479448SAndreas.Sandberg@ARM.com } else { 1489448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1492623SN/A } 1509442SAndreas.Sandberg@ARM.com} 1512798Sktlim@umich.edu 1529442SAndreas.Sandberg@ARM.combool 1539442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1549442SAndreas.Sandberg@ARM.com{ 1559442SAndreas.Sandberg@ARM.com if (!drainManager) 1569442SAndreas.Sandberg@ARM.com return false; 1579442SAndreas.Sandberg@ARM.com 1589442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1599442SAndreas.Sandberg@ARM.com if (!isDrained()) 1609442SAndreas.Sandberg@ARM.com return false; 1619442SAndreas.Sandberg@ARM.com 1629442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1639442SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 1649442SAndreas.Sandberg@ARM.com drainManager = NULL; 1659442SAndreas.Sandberg@ARM.com 1669442SAndreas.Sandberg@ARM.com return true; 1672798Sktlim@umich.edu} 1682798Sktlim@umich.edu 1692798Sktlim@umich.eduvoid 1702798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1712798Sktlim@umich.edu{ 1729429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1739429SAndreas.Sandberg@ARM.com 1749442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1759342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1769442SAndreas.Sandberg@ARM.com assert(!stayAtPC); 1779442SAndreas.Sandberg@ARM.com assert(microPC() == 0); 1789442SAndreas.Sandberg@ARM.com 1799179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 1802623SN/A} 1812623SN/A 1822623SN/A 1832623SN/Avoid 1842623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1852623SN/A{ 1869429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1872623SN/A 1889179Sandreas.hansson@arm.com previousCycle = curCycle(); 1892623SN/A} 1902623SN/A 1919523SAndreas.Sandberg@ARM.comvoid 1929523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1939523SAndreas.Sandberg@ARM.com{ 1949523SAndreas.Sandberg@ARM.com if (system->getMemoryMode() != Enums::timing) { 1959523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 1969523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 1979523SAndreas.Sandberg@ARM.com } 1989523SAndreas.Sandberg@ARM.com} 1992623SN/A 2002623SN/Avoid 2019180Sandreas.hansson@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 2022623SN/A{ 2035221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2045221Ssaidi@eecs.umich.edu 2052623SN/A assert(thread_num == 0); 2062683Sktlim@umich.edu assert(thread); 2072623SN/A 2082623SN/A assert(_status == Idle); 2092623SN/A 2102623SN/A notIdleFraction++; 2119342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2123686Sktlim@umich.edu 2132623SN/A // kick things off by initiating the fetch of the next instruction 2149179Sandreas.hansson@arm.com schedule(fetchEvent, clockEdge(delay)); 2152623SN/A} 2162623SN/A 2172623SN/A 2182623SN/Avoid 2198737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2202623SN/A{ 2215221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2225221Ssaidi@eecs.umich.edu 2232623SN/A assert(thread_num == 0); 2242683Sktlim@umich.edu assert(thread); 2252623SN/A 2266043Sgblack@eecs.umich.edu if (_status == Idle) 2276043Sgblack@eecs.umich.edu return; 2286043Sgblack@eecs.umich.edu 2299342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2302623SN/A 2312644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2322644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2332623SN/A 2342623SN/A notIdleFraction--; 2352623SN/A _status = Idle; 2362623SN/A} 2372623SN/A 2385728Sgblack@eecs.umich.edubool 2395728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2405728Sgblack@eecs.umich.edu{ 2415728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2428105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2439180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2449179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2455728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2465728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2478975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2485728Sgblack@eecs.umich.edu _status = DcacheRetry; 2495728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2505728Sgblack@eecs.umich.edu } else { 2515728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2525728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2535728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2545728Sgblack@eecs.umich.edu } 2555728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2565728Sgblack@eecs.umich.edu} 2572623SN/A 2585894Sgblack@eecs.umich.eduvoid 2596973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2606973Stjones1@inf.ed.ac.uk bool read) 2615744Sgblack@eecs.umich.edu{ 2625894Sgblack@eecs.umich.edu PacketPtr pkt; 2635894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2647691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2655894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2665894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2675894Sgblack@eecs.umich.edu pkt->makeResponse(); 2685894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2695894Sgblack@eecs.umich.edu } else if (read) { 2705894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2715894Sgblack@eecs.umich.edu } else { 2725894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2735894Sgblack@eecs.umich.edu 2746102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2755894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2765894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2775894Sgblack@eecs.umich.edu assert(res); 2785894Sgblack@eecs.umich.edu req->setExtraData(*res); 2795894Sgblack@eecs.umich.edu } 2805894Sgblack@eecs.umich.edu 2815894Sgblack@eecs.umich.edu if (do_access) { 2825894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2835894Sgblack@eecs.umich.edu handleWritePacket(); 2845894Sgblack@eecs.umich.edu } else { 2855894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2865894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2875894Sgblack@eecs.umich.edu } 2885894Sgblack@eecs.umich.edu } 2895894Sgblack@eecs.umich.edu} 2905894Sgblack@eecs.umich.edu 2915894Sgblack@eecs.umich.eduvoid 2926973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 2936973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 2945894Sgblack@eecs.umich.edu{ 2955894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 2965894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 2975894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2985894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2995894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3005894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3015894Sgblack@eecs.umich.edu } else if (read) { 3027911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3037911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3045894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3055894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3067911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3077911Shestness@cs.utexas.edu pkt2->senderState); 3085894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3095894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3105894Sgblack@eecs.umich.edu } 3115894Sgblack@eecs.umich.edu } 3125894Sgblack@eecs.umich.edu } else { 3135894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3147911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3157911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3165894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3175894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3185894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3197911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3207911Shestness@cs.utexas.edu pkt2->senderState); 3215894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3225894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3235894Sgblack@eecs.umich.edu } 3245894Sgblack@eecs.umich.edu } 3255894Sgblack@eecs.umich.edu } 3265894Sgblack@eecs.umich.edu} 3275894Sgblack@eecs.umich.edu 3285894Sgblack@eecs.umich.eduvoid 3295894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3305894Sgblack@eecs.umich.edu{ 3316739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3326739Sgblack@eecs.umich.edu // for instance prefetches. 3339179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 3349179Sandreas.hansson@arm.com previousCycle = curCycle(); 3355894Sgblack@eecs.umich.edu 3365894Sgblack@eecs.umich.edu if (traceData) { 3375894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3385894Sgblack@eecs.umich.edu delete traceData; 3395894Sgblack@eecs.umich.edu traceData = NULL; 3405744Sgblack@eecs.umich.edu } 3415744Sgblack@eecs.umich.edu 3425894Sgblack@eecs.umich.edu postExecute(); 3435894Sgblack@eecs.umich.edu 3449442SAndreas.Sandberg@ARM.com advanceInst(fault); 3455894Sgblack@eecs.umich.edu} 3465894Sgblack@eecs.umich.edu 3475894Sgblack@eecs.umich.eduvoid 3485894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3495894Sgblack@eecs.umich.edu{ 3505894Sgblack@eecs.umich.edu MemCmd cmd; 3515894Sgblack@eecs.umich.edu if (read) { 3525894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3536102Sgblack@eecs.umich.edu if (req->isLLSC()) 3545894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3555894Sgblack@eecs.umich.edu } else { 3565894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3576102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3585894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3595894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3605894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3615894Sgblack@eecs.umich.edu } 3625894Sgblack@eecs.umich.edu } 3638949Sandreas.hansson@arm.com pkt = new Packet(req, cmd); 3645894Sgblack@eecs.umich.edu} 3655894Sgblack@eecs.umich.edu 3665894Sgblack@eecs.umich.eduvoid 3675894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3685894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3695894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3705894Sgblack@eecs.umich.edu{ 3715894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3725894Sgblack@eecs.umich.edu 3738105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3745744Sgblack@eecs.umich.edu 3755894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3765894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3775894Sgblack@eecs.umich.edu return; 3785894Sgblack@eecs.umich.edu } 3795894Sgblack@eecs.umich.edu 3805894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3815894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3825894Sgblack@eecs.umich.edu 3838832SAli.Saidi@ARM.com req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 3848949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3855744Sgblack@eecs.umich.edu 3867691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 3875744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3885744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3895744Sgblack@eecs.umich.edu 3905744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3915744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3925744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3935744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3945744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3955744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3965744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3975744Sgblack@eecs.umich.edu} 3985744Sgblack@eecs.umich.edu 3992623SN/AFault 4008444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4018444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4022623SN/A{ 4035728Sgblack@eecs.umich.edu Fault fault; 4045728Sgblack@eecs.umich.edu const int asid = 0; 4056221Snate@binkert.org const ThreadID tid = 0; 4067720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4076227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4086973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4092623SN/A 4107045Ssteve.reinhardt@amd.com if (traceData) { 4117045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4127045Ssteve.reinhardt@amd.com } 4137045Ssteve.reinhardt@amd.com 4147520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4158832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4165728Sgblack@eecs.umich.edu 4177520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4185744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4195728Sgblack@eecs.umich.edu 4205894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4215744Sgblack@eecs.umich.edu if (split_addr > addr) { 4225894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4236102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4245894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4255894Sgblack@eecs.umich.edu 4266973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4277520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4286973Stjones1@inf.ed.ac.uk NULL, mode); 4298486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4308486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4318486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4328486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4336973Stjones1@inf.ed.ac.uk 4346973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4356973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4365744Sgblack@eecs.umich.edu } else { 4376973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4387520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4398486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4408486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4416973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4422623SN/A } 4432623SN/A 4445728Sgblack@eecs.umich.edu return NoFault; 4452623SN/A} 4462623SN/A 4475728Sgblack@eecs.umich.edubool 4485728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4495728Sgblack@eecs.umich.edu{ 4505728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4518105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4529180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4539179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4545728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4555728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4568975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4575728Sgblack@eecs.umich.edu _status = DcacheRetry; 4585728Sgblack@eecs.umich.edu } else { 4595728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4605728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4615728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4625728Sgblack@eecs.umich.edu } 4635728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4645728Sgblack@eecs.umich.edu} 4652623SN/A 4662623SN/AFault 4678444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4688444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4692623SN/A{ 4708443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4718443Sgblack@eecs.umich.edu memcpy(newData, data, size); 4728443Sgblack@eecs.umich.edu 4735728Sgblack@eecs.umich.edu const int asid = 0; 4746221Snate@binkert.org const ThreadID tid = 0; 4757720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4766227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4776973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4783169Sstever@eecs.umich.edu 4797045Ssteve.reinhardt@amd.com if (traceData) { 4807045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4817045Ssteve.reinhardt@amd.com } 4827045Ssteve.reinhardt@amd.com 4837520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4848832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4855728Sgblack@eecs.umich.edu 4867520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4875744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4885728Sgblack@eecs.umich.edu 4895894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4905744Sgblack@eecs.umich.edu if (split_addr > addr) { 4915894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4926102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4935894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4945894Sgblack@eecs.umich.edu 4956973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4968443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 4978486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4988486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4998486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5008486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5016973Stjones1@inf.ed.ac.uk 5026973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5036973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5045744Sgblack@eecs.umich.edu } else { 5056973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5068443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5078486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5088486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5096973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5102623SN/A } 5112623SN/A 5127045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5135728Sgblack@eecs.umich.edu return NoFault; 5142623SN/A} 5152623SN/A 5162623SN/A 5172623SN/Avoid 5186973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5196973Stjones1@inf.ed.ac.uk{ 5209342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5216973Stjones1@inf.ed.ac.uk 5226973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5236973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5246973Stjones1@inf.ed.ac.uk state->setNoFault(); 5256973Stjones1@inf.ed.ac.uk } 5267691SAli.Saidi@ARM.com delete [] state->data; 5276973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5286973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5296973Stjones1@inf.ed.ac.uk } else { 5306973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5316973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5326973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5336973Stjones1@inf.ed.ac.uk } else { 5346973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5356973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5366973Stjones1@inf.ed.ac.uk } 5376973Stjones1@inf.ed.ac.uk } 5386973Stjones1@inf.ed.ac.uk 5396973Stjones1@inf.ed.ac.uk delete state; 5406973Stjones1@inf.ed.ac.uk} 5416973Stjones1@inf.ed.ac.uk 5426973Stjones1@inf.ed.ac.uk 5436973Stjones1@inf.ed.ac.ukvoid 5442623SN/ATimingSimpleCPU::fetch() 5452623SN/A{ 5465221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5475221Ssaidi@eecs.umich.edu 5483387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5493387Sgblack@eecs.umich.edu checkForInterrupts(); 5502631SN/A 5515348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5525348Ssaidi@eecs.umich.edu 5538143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5548143SAli.Saidi@ARM.com if (_status == Idle) 5558143SAli.Saidi@ARM.com return; 5568143SAli.Saidi@ARM.com 5577720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5587720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5592623SN/A 5607720Sgblack@eecs.umich.edu if (needToFetch) { 5619342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5625669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5635712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5645894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5658277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5666023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5676023Snate@binkert.org BaseTLB::Execute); 5682623SN/A } else { 5695669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5705669Sgblack@eecs.umich.edu completeIfetch(NULL); 5715894Sgblack@eecs.umich.edu 5729179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 5739179Sandreas.hansson@arm.com previousCycle = curCycle(); 5745894Sgblack@eecs.umich.edu } 5755894Sgblack@eecs.umich.edu} 5765894Sgblack@eecs.umich.edu 5775894Sgblack@eecs.umich.edu 5785894Sgblack@eecs.umich.eduvoid 5795894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 5805894Sgblack@eecs.umich.edu{ 5815894Sgblack@eecs.umich.edu if (fault == NoFault) { 5828277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5838277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5848949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5855894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5868277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5875894Sgblack@eecs.umich.edu 5888975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5895894Sgblack@eecs.umich.edu // Need to wait for retry 5905894Sgblack@eecs.umich.edu _status = IcacheRetry; 5915894Sgblack@eecs.umich.edu } else { 5925894Sgblack@eecs.umich.edu // Need to wait for cache to respond 5935894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5945894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5955894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 5965894Sgblack@eecs.umich.edu } 5975894Sgblack@eecs.umich.edu } else { 5988277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 5995894Sgblack@eecs.umich.edu delete req; 6005894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6019342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6025894Sgblack@eecs.umich.edu advanceInst(fault); 6032623SN/A } 6043222Sktlim@umich.edu 6059179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6069179Sandreas.hansson@arm.com previousCycle = curCycle(); 6072623SN/A} 6082623SN/A 6092623SN/A 6102623SN/Avoid 6112644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6122623SN/A{ 6138276SAli.Saidi@ARM.com if (_status == Faulting) 6148276SAli.Saidi@ARM.com return; 6158276SAli.Saidi@ARM.com 6168276SAli.Saidi@ARM.com if (fault != NoFault) { 6178276SAli.Saidi@ARM.com advancePC(fault); 6188276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6198276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 6208276SAli.Saidi@ARM.com _status = Faulting; 6218276SAli.Saidi@ARM.com return; 6228276SAli.Saidi@ARM.com } 6238276SAli.Saidi@ARM.com 6248276SAli.Saidi@ARM.com 6258276SAli.Saidi@ARM.com if (!stayAtPC) 6265726Sgblack@eecs.umich.edu advancePC(fault); 6272623SN/A 6289442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6299442SAndreas.Sandberg@ARM.com return; 6309442SAndreas.Sandberg@ARM.com 6319342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6322631SN/A // kick off fetch of next instruction... callback from icache 6332631SN/A // response will cause that instruction to be executed, 6342631SN/A // keeping the CPU running. 6352631SN/A fetch(); 6362631SN/A } 6372623SN/A} 6382623SN/A 6392623SN/A 6402623SN/Avoid 6413349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6422623SN/A{ 6438277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6448277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6458277SAli.Saidi@ARM.com 6462623SN/A // received a response from the icache: execute the received 6472623SN/A // instruction 6485669Sgblack@eecs.umich.edu 6495669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6502623SN/A assert(_status == IcacheWaitResponse); 6512798Sktlim@umich.edu 6529342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6532644Sstever@eecs.umich.edu 6549179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6559179Sandreas.hansson@arm.com previousCycle = curCycle(); 6563222Sktlim@umich.edu 6572623SN/A preExecute(); 6587725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6592623SN/A // load or store: just send to dcache 6602623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6617945SAli.Saidi@ARM.com 6627945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6637945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6647945SAli.Saidi@ARM.com // ifetch 6659342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6665894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6675001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6685001Sgblack@eecs.umich.edu delete traceData; 6695001Sgblack@eecs.umich.edu traceData = NULL; 6703170Sstever@eecs.umich.edu } 6714998Sgblack@eecs.umich.edu 6722644Sstever@eecs.umich.edu postExecute(); 6735103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6745103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6755103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6765103Ssaidi@eecs.umich.edu instCnt++; 6772644Sstever@eecs.umich.edu advanceInst(fault); 6782644Sstever@eecs.umich.edu } 6795726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6802623SN/A // non-memory instruction: execute completely now 6812623SN/A Fault fault = curStaticInst->execute(this, traceData); 6824998Sgblack@eecs.umich.edu 6834998Sgblack@eecs.umich.edu // keep an instruction count 6844998Sgblack@eecs.umich.edu if (fault == NoFault) 6854998Sgblack@eecs.umich.edu countInst(); 6867655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6875001Sgblack@eecs.umich.edu delete traceData; 6885001Sgblack@eecs.umich.edu traceData = NULL; 6895001Sgblack@eecs.umich.edu } 6904998Sgblack@eecs.umich.edu 6912644Sstever@eecs.umich.edu postExecute(); 6925103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6935103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6945103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6955103Ssaidi@eecs.umich.edu instCnt++; 6962644Sstever@eecs.umich.edu advanceInst(fault); 6975726Sgblack@eecs.umich.edu } else { 6985726Sgblack@eecs.umich.edu advanceInst(NoFault); 6992623SN/A } 7003658Sktlim@umich.edu 7015669Sgblack@eecs.umich.edu if (pkt) { 7025669Sgblack@eecs.umich.edu delete pkt->req; 7035669Sgblack@eecs.umich.edu delete pkt; 7045669Sgblack@eecs.umich.edu } 7052623SN/A} 7062623SN/A 7072948Ssaidi@eecs.umich.eduvoid 7082948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7092948Ssaidi@eecs.umich.edu{ 7102948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7112948Ssaidi@eecs.umich.edu} 7122623SN/A 7132623SN/Abool 7148975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7152623SN/A{ 7169165Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7179165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 7189165Sandreas.hansson@arm.com Tick next_tick = cpu->nextCycle(); 7192948Ssaidi@eecs.umich.edu 7209165Sandreas.hansson@arm.com if (next_tick == curTick()) 7219165Sandreas.hansson@arm.com cpu->completeIfetch(pkt); 7229165Sandreas.hansson@arm.com else 7239165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 7248948Sandreas.hansson@arm.com 7254433Ssaidi@eecs.umich.edu return true; 7262623SN/A} 7272623SN/A 7282657Ssaidi@eecs.umich.eduvoid 7292623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7302623SN/A{ 7312623SN/A // we shouldn't get a retry unless we have a packet that we're 7322623SN/A // waiting to transmit 7332623SN/A assert(cpu->ifetch_pkt != NULL); 7342623SN/A assert(cpu->_status == IcacheRetry); 7353349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7368975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7372657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7382657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7392657Ssaidi@eecs.umich.edu } 7402623SN/A} 7412623SN/A 7422623SN/Avoid 7433349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7442623SN/A{ 7452623SN/A // received a response from the dcache: complete the load or store 7462623SN/A // instruction 7474870Sstever@eecs.umich.edu assert(!pkt->isError()); 7487516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7497516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7502623SN/A 7519179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 7529179Sandreas.hansson@arm.com previousCycle = curCycle(); 7533184Srdreslin@umich.edu 7545728Sgblack@eecs.umich.edu if (pkt->senderState) { 7555728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7565728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7575728Sgblack@eecs.umich.edu assert(send_state); 7585728Sgblack@eecs.umich.edu delete pkt->req; 7595728Sgblack@eecs.umich.edu delete pkt; 7605728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7615728Sgblack@eecs.umich.edu delete send_state; 7625728Sgblack@eecs.umich.edu 7635728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7645728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7655728Sgblack@eecs.umich.edu assert(main_send_state); 7665728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7675728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7685728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7695728Sgblack@eecs.umich.edu 7705728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7715728Sgblack@eecs.umich.edu return; 7725728Sgblack@eecs.umich.edu } else { 7735728Sgblack@eecs.umich.edu delete main_send_state; 7745728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7755728Sgblack@eecs.umich.edu pkt = big_pkt; 7765728Sgblack@eecs.umich.edu } 7775728Sgblack@eecs.umich.edu } 7785728Sgblack@eecs.umich.edu 7799342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7805728Sgblack@eecs.umich.edu 7812623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7822623SN/A 7834998Sgblack@eecs.umich.edu // keep an instruction count 7844998Sgblack@eecs.umich.edu if (fault == NoFault) 7854998Sgblack@eecs.umich.edu countInst(); 7865001Sgblack@eecs.umich.edu else if (traceData) { 7875001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7885001Sgblack@eecs.umich.edu delete traceData; 7895001Sgblack@eecs.umich.edu traceData = NULL; 7905001Sgblack@eecs.umich.edu } 7914998Sgblack@eecs.umich.edu 7925507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 7935507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 7946102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 7953170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 7963170Sstever@eecs.umich.edu } 7973170Sstever@eecs.umich.edu 7982644Sstever@eecs.umich.edu delete pkt->req; 7992644Sstever@eecs.umich.edu delete pkt; 8002644Sstever@eecs.umich.edu 8013184Srdreslin@umich.edu postExecute(); 8023227Sktlim@umich.edu 8032644Sstever@eecs.umich.edu advanceInst(fault); 8042623SN/A} 8052623SN/A 8062623SN/Abool 8078975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8082623SN/A{ 8099165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 8109165Sandreas.hansson@arm.com Tick next_tick = cpu->nextCycle(); 8112948Ssaidi@eecs.umich.edu 8129165Sandreas.hansson@arm.com if (next_tick == curTick()) { 8139165Sandreas.hansson@arm.com cpu->completeDataAccess(pkt); 8149165Sandreas.hansson@arm.com } else { 8159165Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 8169165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 8175728Sgblack@eecs.umich.edu } else { 8189165Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 8199165Sandreas.hansson@arm.com // faster than a CPU we could get two responses before 8209165Sandreas.hansson@arm.com // next_tick expires 8219165Sandreas.hansson@arm.com if (!retryEvent.scheduled()) 8229165Sandreas.hansson@arm.com cpu->schedule(retryEvent, next_tick); 8239165Sandreas.hansson@arm.com return false; 8244433Ssaidi@eecs.umich.edu } 8253310Srdreslin@umich.edu } 8268948Sandreas.hansson@arm.com 8274433Ssaidi@eecs.umich.edu return true; 8282948Ssaidi@eecs.umich.edu} 8292948Ssaidi@eecs.umich.edu 8302948Ssaidi@eecs.umich.eduvoid 8312948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8322948Ssaidi@eecs.umich.edu{ 8332630SN/A cpu->completeDataAccess(pkt); 8342623SN/A} 8352623SN/A 8362657Ssaidi@eecs.umich.eduvoid 8372623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8382623SN/A{ 8392623SN/A // we shouldn't get a retry unless we have a packet that we're 8402623SN/A // waiting to transmit 8412623SN/A assert(cpu->dcache_pkt != NULL); 8422623SN/A assert(cpu->_status == DcacheRetry); 8433349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8445728Sgblack@eecs.umich.edu if (tmp->senderState) { 8455728Sgblack@eecs.umich.edu // This is a packet from a split access. 8465728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8475728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8485728Sgblack@eecs.umich.edu assert(send_state); 8495728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8505728Sgblack@eecs.umich.edu 8515728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8525728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8535728Sgblack@eecs.umich.edu assert(main_send_state); 8545728Sgblack@eecs.umich.edu 8558975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8565728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8575728Sgblack@eecs.umich.edu // and try sending the other fragment. 8585728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8595728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8605728Sgblack@eecs.umich.edu if (other_index > 0) { 8615728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8625728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8635728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8645728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8655728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 8665728Sgblack@eecs.umich.edu } 8675728Sgblack@eecs.umich.edu } else { 8685728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8695728Sgblack@eecs.umich.edu // memory system takes ownership of packet 8705728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 8715728Sgblack@eecs.umich.edu } 8725728Sgblack@eecs.umich.edu } 8738975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 8742657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8753170Sstever@eecs.umich.edu // memory system takes ownership of packet 8762657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8772657Ssaidi@eecs.umich.edu } 8782623SN/A} 8792623SN/A 8805606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 8815606Snate@binkert.org Tick t) 8825606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 8835103Ssaidi@eecs.umich.edu{ 8845606Snate@binkert.org cpu->schedule(this, t); 8855103Ssaidi@eecs.umich.edu} 8865103Ssaidi@eecs.umich.edu 8875103Ssaidi@eecs.umich.eduvoid 8885103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8895103Ssaidi@eecs.umich.edu{ 8905103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8915103Ssaidi@eecs.umich.edu} 8925103Ssaidi@eecs.umich.edu 8935103Ssaidi@eecs.umich.educonst char * 8945336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 8955103Ssaidi@eecs.umich.edu{ 8965103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 8975103Ssaidi@eecs.umich.edu} 8985103Ssaidi@eecs.umich.edu 8992623SN/A 9005315Sstever@gmail.comvoid 9015315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9025315Sstever@gmail.com{ 9035315Sstever@gmail.com dcachePort.printAddr(a); 9045315Sstever@gmail.com} 9055315Sstever@gmail.com 9065315Sstever@gmail.com 9072623SN/A//////////////////////////////////////////////////////////////////////// 9082623SN/A// 9092623SN/A// TimingSimpleCPU Simulation Object 9102623SN/A// 9114762Snate@binkert.orgTimingSimpleCPU * 9124762Snate@binkert.orgTimingSimpleCPUParams::create() 9132623SN/A{ 9145529Snate@binkert.org numThreads = 1; 9158779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9164762Snate@binkert.org panic("only one workload allowed"); 9175529Snate@binkert.org return new TimingSimpleCPU(this); 9182623SN/A} 919