timing.cc revision 9342
12623SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528232Snate@binkert.org#include "debug/ExecFaulting.hh" 538232Snate@binkert.org#include "debug/SimpleCPU.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 553348Sbinkertn@umich.edu#include "mem/packet_access.hh" 564762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 577678Sgblack@eecs.umich.edu#include "sim/faults.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592901Ssaidi@eecs.umich.edu#include "sim/system.hh" 602623SN/A 612623SN/Ausing namespace std; 622623SN/Ausing namespace TheISA; 632623SN/A 642623SN/Avoid 652623SN/ATimingSimpleCPU::init() 662623SN/A{ 672623SN/A BaseCPU::init(); 688921Sandreas.hansson@arm.com 698921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 708921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 718921Sandreas.hansson@arm.com 729058Satgutier@umich.edu if (FullSystem && !params()->defer_registration) { 738779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 748779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 758779Sgblack@eecs.umich.edu // initialize CPU, including PC 768779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 778779Sgblack@eecs.umich.edu } 782623SN/A } 792623SN/A} 802623SN/A 812623SN/Avoid 828707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 832948Ssaidi@eecs.umich.edu{ 842948Ssaidi@eecs.umich.edu pkt = _pkt; 855606Snate@binkert.org cpu->schedule(this, t); 862948Ssaidi@eecs.umich.edu} 872948Ssaidi@eecs.umich.edu 885529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 898707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 909179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 919179Sandreas.hansson@arm.com fetchEvent(this) 922623SN/A{ 932623SN/A _status = Idle; 943647Srdreslin@umich.edu 959342SAndreas.Sandberg@arm.com setDrainState(Drainable::Running); 967897Shestness@cs.utexas.edu system->totalNumInsts = 0; 972623SN/A} 982623SN/A 992623SN/A 1002623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1012623SN/A{ 1022623SN/A} 1032623SN/A 1042623SN/Avoid 1052623SN/ATimingSimpleCPU::serialize(ostream &os) 1062623SN/A{ 1079342SAndreas.Sandberg@arm.com Drainable::State so_state(getDrainState()); 1082915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1092623SN/A BaseSimpleCPU::serialize(os); 1102623SN/A} 1112623SN/A 1122623SN/Avoid 1132623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1142623SN/A{ 1159342SAndreas.Sandberg@arm.com Drainable::State so_state; 1162915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1172623SN/A BaseSimpleCPU::unserialize(cp, section); 1182798Sktlim@umich.edu} 1192798Sktlim@umich.edu 1202901Ssaidi@eecs.umich.eduunsigned int 1219342SAndreas.Sandberg@arm.comTimingSimpleCPU::drain(DrainManager *drain_manager) 1222798Sktlim@umich.edu{ 1232839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1242798Sktlim@umich.edu // an access to complete. 1259342SAndreas.Sandberg@arm.com if (_status == Idle || 1269342SAndreas.Sandberg@arm.com _status == BaseSimpleCPU::Running || 1279342SAndreas.Sandberg@arm.com _status == SwitchedOut) { 1289342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 1292901Ssaidi@eecs.umich.edu return 0; 1302798Sktlim@umich.edu } else { 1319342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 1329342SAndreas.Sandberg@arm.com drainManager = drain_manager; 1339152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 1342901Ssaidi@eecs.umich.edu return 1; 1352798Sktlim@umich.edu } 1362623SN/A} 1372623SN/A 1382623SN/Avoid 1399342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1402623SN/A{ 1415221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1422798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1434762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1443201Shsul@eecs.umich.edu 1455710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1465710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1472915Sktlim@umich.edu 1485710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1492623SN/A } 1502798Sktlim@umich.edu 1519342SAndreas.Sandberg@arm.com setDrainState(Drainable::Running); 1522798Sktlim@umich.edu} 1532798Sktlim@umich.edu 1542798Sktlim@umich.eduvoid 1552798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1562798Sktlim@umich.edu{ 1579342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1582798Sktlim@umich.edu _status = SwitchedOut; 1599179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 1602867Sktlim@umich.edu 1612867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1622867Sktlim@umich.edu // we'll need to cancel it. 1635710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1645606Snate@binkert.org deschedule(fetchEvent); 1652623SN/A} 1662623SN/A 1672623SN/A 1682623SN/Avoid 1692623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1702623SN/A{ 1718737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 1722623SN/A 1732680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1742623SN/A // running and schedule its tick event. 1752680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1762680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1779342SAndreas.Sandberg@arm.com if (tc->status() == ThreadContext::Active && 1789342SAndreas.Sandberg@arm.com _status != BaseSimpleCPU::Running) { 1799342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 1802623SN/A break; 1812623SN/A } 1822623SN/A } 1833201Shsul@eecs.umich.edu 1849342SAndreas.Sandberg@arm.com if (_status != BaseSimpleCPU::Running) { 1853201Shsul@eecs.umich.edu _status = Idle; 1863201Shsul@eecs.umich.edu } 1875169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 1889179Sandreas.hansson@arm.com previousCycle = curCycle(); 1892623SN/A} 1902623SN/A 1912623SN/A 1922623SN/Avoid 1939180Sandreas.hansson@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 1942623SN/A{ 1955221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 1965221Ssaidi@eecs.umich.edu 1972623SN/A assert(thread_num == 0); 1982683Sktlim@umich.edu assert(thread); 1992623SN/A 2002623SN/A assert(_status == Idle); 2012623SN/A 2022623SN/A notIdleFraction++; 2039342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2043686Sktlim@umich.edu 2052623SN/A // kick things off by initiating the fetch of the next instruction 2069179Sandreas.hansson@arm.com schedule(fetchEvent, clockEdge(delay)); 2072623SN/A} 2082623SN/A 2092623SN/A 2102623SN/Avoid 2118737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2122623SN/A{ 2135221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2145221Ssaidi@eecs.umich.edu 2152623SN/A assert(thread_num == 0); 2162683Sktlim@umich.edu assert(thread); 2172623SN/A 2186043Sgblack@eecs.umich.edu if (_status == Idle) 2196043Sgblack@eecs.umich.edu return; 2206043Sgblack@eecs.umich.edu 2219342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2222623SN/A 2232644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2242644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2252623SN/A 2262623SN/A notIdleFraction--; 2272623SN/A _status = Idle; 2282623SN/A} 2292623SN/A 2305728Sgblack@eecs.umich.edubool 2315728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2325728Sgblack@eecs.umich.edu{ 2335728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2348105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2359180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2369179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2375728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2385728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2398975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2405728Sgblack@eecs.umich.edu _status = DcacheRetry; 2415728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2425728Sgblack@eecs.umich.edu } else { 2435728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2445728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2455728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2465728Sgblack@eecs.umich.edu } 2475728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2485728Sgblack@eecs.umich.edu} 2492623SN/A 2505894Sgblack@eecs.umich.eduvoid 2516973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2526973Stjones1@inf.ed.ac.uk bool read) 2535744Sgblack@eecs.umich.edu{ 2545894Sgblack@eecs.umich.edu PacketPtr pkt; 2555894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2567691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2575894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2585894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2595894Sgblack@eecs.umich.edu pkt->makeResponse(); 2605894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2615894Sgblack@eecs.umich.edu } else if (read) { 2625894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2635894Sgblack@eecs.umich.edu } else { 2645894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2655894Sgblack@eecs.umich.edu 2666102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2675894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2685894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2695894Sgblack@eecs.umich.edu assert(res); 2705894Sgblack@eecs.umich.edu req->setExtraData(*res); 2715894Sgblack@eecs.umich.edu } 2725894Sgblack@eecs.umich.edu 2735894Sgblack@eecs.umich.edu if (do_access) { 2745894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2755894Sgblack@eecs.umich.edu handleWritePacket(); 2765894Sgblack@eecs.umich.edu } else { 2775894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2785894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2795894Sgblack@eecs.umich.edu } 2805894Sgblack@eecs.umich.edu } 2815894Sgblack@eecs.umich.edu} 2825894Sgblack@eecs.umich.edu 2835894Sgblack@eecs.umich.eduvoid 2846973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 2856973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 2865894Sgblack@eecs.umich.edu{ 2875894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 2885894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 2895894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2905894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2915894Sgblack@eecs.umich.edu pkt1->makeResponse(); 2925894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 2935894Sgblack@eecs.umich.edu } else if (read) { 2947911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 2957911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 2965894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 2975894Sgblack@eecs.umich.edu send_state->clearFromParent(); 2987911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 2997911Shestness@cs.utexas.edu pkt2->senderState); 3005894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3015894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3025894Sgblack@eecs.umich.edu } 3035894Sgblack@eecs.umich.edu } 3045894Sgblack@eecs.umich.edu } else { 3055894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3067911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3077911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3085894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3095894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3105894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3117911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3127911Shestness@cs.utexas.edu pkt2->senderState); 3135894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3145894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3155894Sgblack@eecs.umich.edu } 3165894Sgblack@eecs.umich.edu } 3175894Sgblack@eecs.umich.edu } 3185894Sgblack@eecs.umich.edu} 3195894Sgblack@eecs.umich.edu 3205894Sgblack@eecs.umich.eduvoid 3215894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3225894Sgblack@eecs.umich.edu{ 3236739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3246739Sgblack@eecs.umich.edu // for instance prefetches. 3259179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 3269179Sandreas.hansson@arm.com previousCycle = curCycle(); 3275894Sgblack@eecs.umich.edu 3285894Sgblack@eecs.umich.edu if (traceData) { 3295894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3305894Sgblack@eecs.umich.edu delete traceData; 3315894Sgblack@eecs.umich.edu traceData = NULL; 3325744Sgblack@eecs.umich.edu } 3335744Sgblack@eecs.umich.edu 3345894Sgblack@eecs.umich.edu postExecute(); 3355894Sgblack@eecs.umich.edu 3369342SAndreas.Sandberg@arm.com if (getDrainState() == Drainable::Draining) { 3375894Sgblack@eecs.umich.edu advancePC(fault); 3385894Sgblack@eecs.umich.edu completeDrain(); 3395894Sgblack@eecs.umich.edu } else { 3405894Sgblack@eecs.umich.edu advanceInst(fault); 3415894Sgblack@eecs.umich.edu } 3425894Sgblack@eecs.umich.edu} 3435894Sgblack@eecs.umich.edu 3445894Sgblack@eecs.umich.eduvoid 3455894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3465894Sgblack@eecs.umich.edu{ 3475894Sgblack@eecs.umich.edu MemCmd cmd; 3485894Sgblack@eecs.umich.edu if (read) { 3495894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3506102Sgblack@eecs.umich.edu if (req->isLLSC()) 3515894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3525894Sgblack@eecs.umich.edu } else { 3535894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3546102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3555894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3565894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3575894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3585894Sgblack@eecs.umich.edu } 3595894Sgblack@eecs.umich.edu } 3608949Sandreas.hansson@arm.com pkt = new Packet(req, cmd); 3615894Sgblack@eecs.umich.edu} 3625894Sgblack@eecs.umich.edu 3635894Sgblack@eecs.umich.eduvoid 3645894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3655894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3665894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3675894Sgblack@eecs.umich.edu{ 3685894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3695894Sgblack@eecs.umich.edu 3708105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3715744Sgblack@eecs.umich.edu 3725894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3735894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3745894Sgblack@eecs.umich.edu return; 3755894Sgblack@eecs.umich.edu } 3765894Sgblack@eecs.umich.edu 3775894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3785894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3795894Sgblack@eecs.umich.edu 3808832SAli.Saidi@ARM.com req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 3818949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3825744Sgblack@eecs.umich.edu 3837691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 3845744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3855744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3865744Sgblack@eecs.umich.edu 3875744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3885744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3895744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3905744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3915744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3925744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3935744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3945744Sgblack@eecs.umich.edu} 3955744Sgblack@eecs.umich.edu 3962623SN/AFault 3978444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 3988444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3992623SN/A{ 4005728Sgblack@eecs.umich.edu Fault fault; 4015728Sgblack@eecs.umich.edu const int asid = 0; 4026221Snate@binkert.org const ThreadID tid = 0; 4037720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4046227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4056973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4062623SN/A 4077045Ssteve.reinhardt@amd.com if (traceData) { 4087045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4097045Ssteve.reinhardt@amd.com } 4107045Ssteve.reinhardt@amd.com 4117520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4128832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4135728Sgblack@eecs.umich.edu 4147520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4155744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4165728Sgblack@eecs.umich.edu 4175894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4185744Sgblack@eecs.umich.edu if (split_addr > addr) { 4195894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4206102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4215894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4225894Sgblack@eecs.umich.edu 4236973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4247520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4256973Stjones1@inf.ed.ac.uk NULL, mode); 4268486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4278486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4288486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4298486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4306973Stjones1@inf.ed.ac.uk 4316973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4326973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4335744Sgblack@eecs.umich.edu } else { 4346973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4357520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4368486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4378486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4386973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4392623SN/A } 4402623SN/A 4415728Sgblack@eecs.umich.edu return NoFault; 4422623SN/A} 4432623SN/A 4445728Sgblack@eecs.umich.edubool 4455728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4465728Sgblack@eecs.umich.edu{ 4475728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4488105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4499180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4509179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4515728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4525728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4538975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4545728Sgblack@eecs.umich.edu _status = DcacheRetry; 4555728Sgblack@eecs.umich.edu } else { 4565728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4575728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4585728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4595728Sgblack@eecs.umich.edu } 4605728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4615728Sgblack@eecs.umich.edu} 4622623SN/A 4632623SN/AFault 4648444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4658444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4662623SN/A{ 4678443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4688443Sgblack@eecs.umich.edu memcpy(newData, data, size); 4698443Sgblack@eecs.umich.edu 4705728Sgblack@eecs.umich.edu const int asid = 0; 4716221Snate@binkert.org const ThreadID tid = 0; 4727720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4736227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4746973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4753169Sstever@eecs.umich.edu 4767045Ssteve.reinhardt@amd.com if (traceData) { 4777045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4787045Ssteve.reinhardt@amd.com } 4797045Ssteve.reinhardt@amd.com 4807520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4818832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4825728Sgblack@eecs.umich.edu 4837520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4845744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4855728Sgblack@eecs.umich.edu 4865894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4875744Sgblack@eecs.umich.edu if (split_addr > addr) { 4885894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4896102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4905894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4915894Sgblack@eecs.umich.edu 4926973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4938443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 4948486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4958486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4968486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4978486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4986973Stjones1@inf.ed.ac.uk 4996973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5006973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5015744Sgblack@eecs.umich.edu } else { 5026973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5038443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5048486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5058486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5066973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5072623SN/A } 5082623SN/A 5097045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5105728Sgblack@eecs.umich.edu return NoFault; 5112623SN/A} 5122623SN/A 5132623SN/A 5142623SN/Avoid 5156973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5166973Stjones1@inf.ed.ac.uk{ 5179342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5186973Stjones1@inf.ed.ac.uk 5196973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5206973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5216973Stjones1@inf.ed.ac.uk state->setNoFault(); 5226973Stjones1@inf.ed.ac.uk } 5237691SAli.Saidi@ARM.com delete [] state->data; 5246973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5256973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5266973Stjones1@inf.ed.ac.uk } else { 5276973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5286973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5296973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5306973Stjones1@inf.ed.ac.uk } else { 5316973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5326973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5336973Stjones1@inf.ed.ac.uk } 5346973Stjones1@inf.ed.ac.uk } 5356973Stjones1@inf.ed.ac.uk 5366973Stjones1@inf.ed.ac.uk delete state; 5376973Stjones1@inf.ed.ac.uk} 5386973Stjones1@inf.ed.ac.uk 5396973Stjones1@inf.ed.ac.uk 5406973Stjones1@inf.ed.ac.ukvoid 5412623SN/ATimingSimpleCPU::fetch() 5422623SN/A{ 5435221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5445221Ssaidi@eecs.umich.edu 5453387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5463387Sgblack@eecs.umich.edu checkForInterrupts(); 5472631SN/A 5485348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5495348Ssaidi@eecs.umich.edu 5508143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5518143SAli.Saidi@ARM.com if (_status == Idle) 5528143SAli.Saidi@ARM.com return; 5538143SAli.Saidi@ARM.com 5547720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5557720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5562623SN/A 5577720Sgblack@eecs.umich.edu if (needToFetch) { 5589342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5595669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5605712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5615894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5628277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5636023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5646023Snate@binkert.org BaseTLB::Execute); 5652623SN/A } else { 5665669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5675669Sgblack@eecs.umich.edu completeIfetch(NULL); 5685894Sgblack@eecs.umich.edu 5699179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 5709179Sandreas.hansson@arm.com previousCycle = curCycle(); 5715894Sgblack@eecs.umich.edu } 5725894Sgblack@eecs.umich.edu} 5735894Sgblack@eecs.umich.edu 5745894Sgblack@eecs.umich.edu 5755894Sgblack@eecs.umich.eduvoid 5765894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 5775894Sgblack@eecs.umich.edu{ 5785894Sgblack@eecs.umich.edu if (fault == NoFault) { 5798277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5808277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5818949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5825894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5838277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5845894Sgblack@eecs.umich.edu 5858975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5865894Sgblack@eecs.umich.edu // Need to wait for retry 5875894Sgblack@eecs.umich.edu _status = IcacheRetry; 5885894Sgblack@eecs.umich.edu } else { 5895894Sgblack@eecs.umich.edu // Need to wait for cache to respond 5905894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5915894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5925894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 5935894Sgblack@eecs.umich.edu } 5945894Sgblack@eecs.umich.edu } else { 5958277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 5965894Sgblack@eecs.umich.edu delete req; 5975894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5989342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5995894Sgblack@eecs.umich.edu advanceInst(fault); 6002623SN/A } 6013222Sktlim@umich.edu 6029179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6039179Sandreas.hansson@arm.com previousCycle = curCycle(); 6042623SN/A} 6052623SN/A 6062623SN/A 6072623SN/Avoid 6082644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6092623SN/A{ 6108276SAli.Saidi@ARM.com 6118276SAli.Saidi@ARM.com if (_status == Faulting) 6128276SAli.Saidi@ARM.com return; 6138276SAli.Saidi@ARM.com 6148276SAli.Saidi@ARM.com if (fault != NoFault) { 6158276SAli.Saidi@ARM.com advancePC(fault); 6168276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6178276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 6188276SAli.Saidi@ARM.com _status = Faulting; 6198276SAli.Saidi@ARM.com return; 6208276SAli.Saidi@ARM.com } 6218276SAli.Saidi@ARM.com 6228276SAli.Saidi@ARM.com 6238276SAli.Saidi@ARM.com if (!stayAtPC) 6245726Sgblack@eecs.umich.edu advancePC(fault); 6252623SN/A 6269342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6272631SN/A // kick off fetch of next instruction... callback from icache 6282631SN/A // response will cause that instruction to be executed, 6292631SN/A // keeping the CPU running. 6302631SN/A fetch(); 6312631SN/A } 6322623SN/A} 6332623SN/A 6342623SN/A 6352623SN/Avoid 6363349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6372623SN/A{ 6388277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6398277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6408277SAli.Saidi@ARM.com 6412623SN/A // received a response from the icache: execute the received 6422623SN/A // instruction 6435669Sgblack@eecs.umich.edu 6445669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6452623SN/A assert(_status == IcacheWaitResponse); 6462798Sktlim@umich.edu 6479342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6482644Sstever@eecs.umich.edu 6499179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6509179Sandreas.hansson@arm.com previousCycle = curCycle(); 6513222Sktlim@umich.edu 6529342SAndreas.Sandberg@arm.com if (getDrainState() == Drainable::Draining) { 6535669Sgblack@eecs.umich.edu if (pkt) { 6545669Sgblack@eecs.umich.edu delete pkt->req; 6555669Sgblack@eecs.umich.edu delete pkt; 6565669Sgblack@eecs.umich.edu } 6573658Sktlim@umich.edu 6582839Sktlim@umich.edu completeDrain(); 6592798Sktlim@umich.edu return; 6602798Sktlim@umich.edu } 6612798Sktlim@umich.edu 6622623SN/A preExecute(); 6637725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6642623SN/A // load or store: just send to dcache 6652623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6667945SAli.Saidi@ARM.com 6677945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6687945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6697945SAli.Saidi@ARM.com // ifetch 6709342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6715894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6725001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6735001Sgblack@eecs.umich.edu delete traceData; 6745001Sgblack@eecs.umich.edu traceData = NULL; 6753170Sstever@eecs.umich.edu } 6764998Sgblack@eecs.umich.edu 6772644Sstever@eecs.umich.edu postExecute(); 6785103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6795103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6805103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6815103Ssaidi@eecs.umich.edu instCnt++; 6822644Sstever@eecs.umich.edu advanceInst(fault); 6832644Sstever@eecs.umich.edu } 6845726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6852623SN/A // non-memory instruction: execute completely now 6862623SN/A Fault fault = curStaticInst->execute(this, traceData); 6874998Sgblack@eecs.umich.edu 6884998Sgblack@eecs.umich.edu // keep an instruction count 6894998Sgblack@eecs.umich.edu if (fault == NoFault) 6904998Sgblack@eecs.umich.edu countInst(); 6917655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6925001Sgblack@eecs.umich.edu delete traceData; 6935001Sgblack@eecs.umich.edu traceData = NULL; 6945001Sgblack@eecs.umich.edu } 6954998Sgblack@eecs.umich.edu 6962644Sstever@eecs.umich.edu postExecute(); 6975103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6985103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6995103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7005103Ssaidi@eecs.umich.edu instCnt++; 7012644Sstever@eecs.umich.edu advanceInst(fault); 7025726Sgblack@eecs.umich.edu } else { 7035726Sgblack@eecs.umich.edu advanceInst(NoFault); 7042623SN/A } 7053658Sktlim@umich.edu 7065669Sgblack@eecs.umich.edu if (pkt) { 7075669Sgblack@eecs.umich.edu delete pkt->req; 7085669Sgblack@eecs.umich.edu delete pkt; 7095669Sgblack@eecs.umich.edu } 7102623SN/A} 7112623SN/A 7122948Ssaidi@eecs.umich.eduvoid 7132948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7142948Ssaidi@eecs.umich.edu{ 7152948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7162948Ssaidi@eecs.umich.edu} 7172623SN/A 7182623SN/Abool 7198975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7202623SN/A{ 7219165Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7229165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 7239165Sandreas.hansson@arm.com Tick next_tick = cpu->nextCycle(); 7242948Ssaidi@eecs.umich.edu 7259165Sandreas.hansson@arm.com if (next_tick == curTick()) 7269165Sandreas.hansson@arm.com cpu->completeIfetch(pkt); 7279165Sandreas.hansson@arm.com else 7289165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 7298948Sandreas.hansson@arm.com 7304433Ssaidi@eecs.umich.edu return true; 7312623SN/A} 7322623SN/A 7332657Ssaidi@eecs.umich.eduvoid 7342623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7352623SN/A{ 7362623SN/A // we shouldn't get a retry unless we have a packet that we're 7372623SN/A // waiting to transmit 7382623SN/A assert(cpu->ifetch_pkt != NULL); 7392623SN/A assert(cpu->_status == IcacheRetry); 7403349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7418975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7422657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7432657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7442657Ssaidi@eecs.umich.edu } 7452623SN/A} 7462623SN/A 7472623SN/Avoid 7483349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7492623SN/A{ 7502623SN/A // received a response from the dcache: complete the load or store 7512623SN/A // instruction 7524870Sstever@eecs.umich.edu assert(!pkt->isError()); 7537516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7547516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7552623SN/A 7569179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 7579179Sandreas.hansson@arm.com previousCycle = curCycle(); 7583184Srdreslin@umich.edu 7595728Sgblack@eecs.umich.edu if (pkt->senderState) { 7605728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7615728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7625728Sgblack@eecs.umich.edu assert(send_state); 7635728Sgblack@eecs.umich.edu delete pkt->req; 7645728Sgblack@eecs.umich.edu delete pkt; 7655728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7665728Sgblack@eecs.umich.edu delete send_state; 7675728Sgblack@eecs.umich.edu 7685728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7695728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7705728Sgblack@eecs.umich.edu assert(main_send_state); 7715728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7725728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7735728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7745728Sgblack@eecs.umich.edu 7755728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7765728Sgblack@eecs.umich.edu return; 7775728Sgblack@eecs.umich.edu } else { 7785728Sgblack@eecs.umich.edu delete main_send_state; 7795728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7805728Sgblack@eecs.umich.edu pkt = big_pkt; 7815728Sgblack@eecs.umich.edu } 7825728Sgblack@eecs.umich.edu } 7835728Sgblack@eecs.umich.edu 7849342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7855728Sgblack@eecs.umich.edu 7862623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7872623SN/A 7884998Sgblack@eecs.umich.edu // keep an instruction count 7894998Sgblack@eecs.umich.edu if (fault == NoFault) 7904998Sgblack@eecs.umich.edu countInst(); 7915001Sgblack@eecs.umich.edu else if (traceData) { 7925001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7935001Sgblack@eecs.umich.edu delete traceData; 7945001Sgblack@eecs.umich.edu traceData = NULL; 7955001Sgblack@eecs.umich.edu } 7964998Sgblack@eecs.umich.edu 7975507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 7985507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 7996102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8003170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8013170Sstever@eecs.umich.edu } 8023170Sstever@eecs.umich.edu 8032644Sstever@eecs.umich.edu delete pkt->req; 8042644Sstever@eecs.umich.edu delete pkt; 8052644Sstever@eecs.umich.edu 8063184Srdreslin@umich.edu postExecute(); 8073227Sktlim@umich.edu 8089342SAndreas.Sandberg@arm.com if (getDrainState() == Drainable::Draining) { 8093201Shsul@eecs.umich.edu advancePC(fault); 8103201Shsul@eecs.umich.edu completeDrain(); 8113201Shsul@eecs.umich.edu 8123201Shsul@eecs.umich.edu return; 8133201Shsul@eecs.umich.edu } 8143201Shsul@eecs.umich.edu 8152644Sstever@eecs.umich.edu advanceInst(fault); 8162623SN/A} 8172623SN/A 8182623SN/A 8192798Sktlim@umich.eduvoid 8202839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 8212798Sktlim@umich.edu{ 8229152Satgutier@umich.edu DPRINTF(Drain, "CPU done draining, processing drain event\n"); 8239342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 8249342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 8252798Sktlim@umich.edu} 8262623SN/A 8272623SN/Abool 8288975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8292623SN/A{ 8309165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 8319165Sandreas.hansson@arm.com Tick next_tick = cpu->nextCycle(); 8322948Ssaidi@eecs.umich.edu 8339165Sandreas.hansson@arm.com if (next_tick == curTick()) { 8349165Sandreas.hansson@arm.com cpu->completeDataAccess(pkt); 8359165Sandreas.hansson@arm.com } else { 8369165Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 8379165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 8385728Sgblack@eecs.umich.edu } else { 8399165Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 8409165Sandreas.hansson@arm.com // faster than a CPU we could get two responses before 8419165Sandreas.hansson@arm.com // next_tick expires 8429165Sandreas.hansson@arm.com if (!retryEvent.scheduled()) 8439165Sandreas.hansson@arm.com cpu->schedule(retryEvent, next_tick); 8449165Sandreas.hansson@arm.com return false; 8454433Ssaidi@eecs.umich.edu } 8463310Srdreslin@umich.edu } 8478948Sandreas.hansson@arm.com 8484433Ssaidi@eecs.umich.edu return true; 8492948Ssaidi@eecs.umich.edu} 8502948Ssaidi@eecs.umich.edu 8512948Ssaidi@eecs.umich.eduvoid 8522948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8532948Ssaidi@eecs.umich.edu{ 8542630SN/A cpu->completeDataAccess(pkt); 8552623SN/A} 8562623SN/A 8572657Ssaidi@eecs.umich.eduvoid 8582623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8592623SN/A{ 8602623SN/A // we shouldn't get a retry unless we have a packet that we're 8612623SN/A // waiting to transmit 8622623SN/A assert(cpu->dcache_pkt != NULL); 8632623SN/A assert(cpu->_status == DcacheRetry); 8643349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8655728Sgblack@eecs.umich.edu if (tmp->senderState) { 8665728Sgblack@eecs.umich.edu // This is a packet from a split access. 8675728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8685728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8695728Sgblack@eecs.umich.edu assert(send_state); 8705728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8715728Sgblack@eecs.umich.edu 8725728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8735728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8745728Sgblack@eecs.umich.edu assert(main_send_state); 8755728Sgblack@eecs.umich.edu 8768975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8775728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8785728Sgblack@eecs.umich.edu // and try sending the other fragment. 8795728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8805728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8815728Sgblack@eecs.umich.edu if (other_index > 0) { 8825728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8835728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8845728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8855728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8865728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 8875728Sgblack@eecs.umich.edu } 8885728Sgblack@eecs.umich.edu } else { 8895728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8905728Sgblack@eecs.umich.edu // memory system takes ownership of packet 8915728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 8925728Sgblack@eecs.umich.edu } 8935728Sgblack@eecs.umich.edu } 8948975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 8952657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8963170Sstever@eecs.umich.edu // memory system takes ownership of packet 8972657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8982657Ssaidi@eecs.umich.edu } 8992623SN/A} 9002623SN/A 9015606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9025606Snate@binkert.org Tick t) 9035606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9045103Ssaidi@eecs.umich.edu{ 9055606Snate@binkert.org cpu->schedule(this, t); 9065103Ssaidi@eecs.umich.edu} 9075103Ssaidi@eecs.umich.edu 9085103Ssaidi@eecs.umich.eduvoid 9095103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9105103Ssaidi@eecs.umich.edu{ 9115103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9125103Ssaidi@eecs.umich.edu} 9135103Ssaidi@eecs.umich.edu 9145103Ssaidi@eecs.umich.educonst char * 9155336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9165103Ssaidi@eecs.umich.edu{ 9175103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9185103Ssaidi@eecs.umich.edu} 9195103Ssaidi@eecs.umich.edu 9202623SN/A 9215315Sstever@gmail.comvoid 9225315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9235315Sstever@gmail.com{ 9245315Sstever@gmail.com dcachePort.printAddr(a); 9255315Sstever@gmail.com} 9265315Sstever@gmail.com 9275315Sstever@gmail.com 9282623SN/A//////////////////////////////////////////////////////////////////////// 9292623SN/A// 9302623SN/A// TimingSimpleCPU Simulation Object 9312623SN/A// 9324762Snate@binkert.orgTimingSimpleCPU * 9334762Snate@binkert.orgTimingSimpleCPUParams::create() 9342623SN/A{ 9355529Snate@binkert.org numThreads = 1; 9368779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9374762Snate@binkert.org panic("only one workload allowed"); 9385529Snate@binkert.org return new TimingSimpleCPU(this); 9392623SN/A} 940