timing.cc revision 8975
12623SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 518232Snate@binkert.org#include "debug/ExecFaulting.hh" 528232Snate@binkert.org#include "debug/SimpleCPU.hh" 533348Sbinkertn@umich.edu#include "mem/packet.hh" 543348Sbinkertn@umich.edu#include "mem/packet_access.hh" 554762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 567678Sgblack@eecs.umich.edu#include "sim/faults.hh" 578779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 582901Ssaidi@eecs.umich.edu#include "sim/system.hh" 592623SN/A 602623SN/Ausing namespace std; 612623SN/Ausing namespace TheISA; 622623SN/A 632623SN/Avoid 642623SN/ATimingSimpleCPU::init() 652623SN/A{ 662623SN/A BaseCPU::init(); 678921Sandreas.hansson@arm.com 688921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 698921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 708921Sandreas.hansson@arm.com 718779Sgblack@eecs.umich.edu if (FullSystem) { 728779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 738779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 748779Sgblack@eecs.umich.edu // initialize CPU, including PC 758779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 768779Sgblack@eecs.umich.edu } 772623SN/A } 782623SN/A} 792623SN/A 802623SN/Avoid 818707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 822948Ssaidi@eecs.umich.edu{ 832948Ssaidi@eecs.umich.edu pkt = _pkt; 845606Snate@binkert.org cpu->schedule(this, t); 852948Ssaidi@eecs.umich.edu} 862948Ssaidi@eecs.umich.edu 875529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 888707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 898707Sandreas.hansson@arm.com dcachePort(this), fetchEvent(this) 902623SN/A{ 912623SN/A _status = Idle; 923647Srdreslin@umich.edu 932623SN/A ifetch_pkt = dcache_pkt = NULL; 942839Sktlim@umich.edu drainEvent = NULL; 953222Sktlim@umich.edu previousTick = 0; 962901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 977897Shestness@cs.utexas.edu system->totalNumInsts = 0; 982623SN/A} 992623SN/A 1002623SN/A 1012623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1022623SN/A{ 1032623SN/A} 1042623SN/A 1052623SN/Avoid 1062623SN/ATimingSimpleCPU::serialize(ostream &os) 1072623SN/A{ 1082915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1092915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1102623SN/A BaseSimpleCPU::serialize(os); 1112623SN/A} 1122623SN/A 1132623SN/Avoid 1142623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1152623SN/A{ 1162915Sktlim@umich.edu SimObject::State so_state; 1172915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1182623SN/A BaseSimpleCPU::unserialize(cp, section); 1192798Sktlim@umich.edu} 1202798Sktlim@umich.edu 1212901Ssaidi@eecs.umich.eduunsigned int 1222839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1232798Sktlim@umich.edu{ 1242839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1252798Sktlim@umich.edu // an access to complete. 1265496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1272901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1282901Ssaidi@eecs.umich.edu return 0; 1292798Sktlim@umich.edu } else { 1302839Sktlim@umich.edu changeState(SimObject::Draining); 1312839Sktlim@umich.edu drainEvent = drain_event; 1322901Ssaidi@eecs.umich.edu return 1; 1332798Sktlim@umich.edu } 1342623SN/A} 1352623SN/A 1362623SN/Avoid 1372798Sktlim@umich.eduTimingSimpleCPU::resume() 1382623SN/A{ 1395221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1402798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1414762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1423201Shsul@eecs.umich.edu 1435710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1445710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1452915Sktlim@umich.edu 1465710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1472623SN/A } 1482798Sktlim@umich.edu 1492901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1502798Sktlim@umich.edu} 1512798Sktlim@umich.edu 1522798Sktlim@umich.eduvoid 1532798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1542798Sktlim@umich.edu{ 1555496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1562798Sktlim@umich.edu _status = SwitchedOut; 1577823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 1582867Sktlim@umich.edu 1592867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1602867Sktlim@umich.edu // we'll need to cancel it. 1615710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1625606Snate@binkert.org deschedule(fetchEvent); 1632623SN/A} 1642623SN/A 1652623SN/A 1662623SN/Avoid 1672623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1682623SN/A{ 1698737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 1702623SN/A 1712680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1722623SN/A // running and schedule its tick event. 1732680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1742680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1752680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1762623SN/A _status = Running; 1772623SN/A break; 1782623SN/A } 1792623SN/A } 1803201Shsul@eecs.umich.edu 1813201Shsul@eecs.umich.edu if (_status != Running) { 1823201Shsul@eecs.umich.edu _status = Idle; 1833201Shsul@eecs.umich.edu } 1845169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 1857823Ssteve.reinhardt@amd.com previousTick = curTick(); 1862623SN/A} 1872623SN/A 1882623SN/A 1892623SN/Avoid 1908737Skoansin.tan@gmail.comTimingSimpleCPU::activateContext(ThreadID thread_num, int delay) 1912623SN/A{ 1925221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 1935221Ssaidi@eecs.umich.edu 1942623SN/A assert(thread_num == 0); 1952683Sktlim@umich.edu assert(thread); 1962623SN/A 1972623SN/A assert(_status == Idle); 1982623SN/A 1992623SN/A notIdleFraction++; 2002623SN/A _status = Running; 2013686Sktlim@umich.edu 2022623SN/A // kick things off by initiating the fetch of the next instruction 2037823Ssteve.reinhardt@amd.com schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 2042623SN/A} 2052623SN/A 2062623SN/A 2072623SN/Avoid 2088737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2092623SN/A{ 2105221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2115221Ssaidi@eecs.umich.edu 2122623SN/A assert(thread_num == 0); 2132683Sktlim@umich.edu assert(thread); 2142623SN/A 2156043Sgblack@eecs.umich.edu if (_status == Idle) 2166043Sgblack@eecs.umich.edu return; 2176043Sgblack@eecs.umich.edu 2182644Sstever@eecs.umich.edu assert(_status == Running); 2192623SN/A 2202644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2212644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2222623SN/A 2232623SN/A notIdleFraction--; 2242623SN/A _status = Idle; 2252623SN/A} 2262623SN/A 2275728Sgblack@eecs.umich.edubool 2285728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2295728Sgblack@eecs.umich.edu{ 2305728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2318105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2325728Sgblack@eecs.umich.edu Tick delay; 2335728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2347823Ssteve.reinhardt@amd.com new IprEvent(pkt, this, nextCycle(curTick() + delay)); 2355728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2365728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2378975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2385728Sgblack@eecs.umich.edu _status = DcacheRetry; 2395728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2405728Sgblack@eecs.umich.edu } else { 2415728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2425728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2435728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2445728Sgblack@eecs.umich.edu } 2455728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2465728Sgblack@eecs.umich.edu} 2472623SN/A 2485894Sgblack@eecs.umich.eduvoid 2496973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2506973Stjones1@inf.ed.ac.uk bool read) 2515744Sgblack@eecs.umich.edu{ 2525894Sgblack@eecs.umich.edu PacketPtr pkt; 2535894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2547691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2555894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2565894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2575894Sgblack@eecs.umich.edu pkt->makeResponse(); 2585894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2595894Sgblack@eecs.umich.edu } else if (read) { 2605894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2615894Sgblack@eecs.umich.edu } else { 2625894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2635894Sgblack@eecs.umich.edu 2646102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2655894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2665894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2675894Sgblack@eecs.umich.edu assert(res); 2685894Sgblack@eecs.umich.edu req->setExtraData(*res); 2695894Sgblack@eecs.umich.edu } 2705894Sgblack@eecs.umich.edu 2715894Sgblack@eecs.umich.edu if (do_access) { 2725894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2735894Sgblack@eecs.umich.edu handleWritePacket(); 2745894Sgblack@eecs.umich.edu } else { 2755894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2765894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2775894Sgblack@eecs.umich.edu } 2785894Sgblack@eecs.umich.edu } 2795894Sgblack@eecs.umich.edu} 2805894Sgblack@eecs.umich.edu 2815894Sgblack@eecs.umich.eduvoid 2826973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 2836973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 2845894Sgblack@eecs.umich.edu{ 2855894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 2865894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 2875894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2885894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2895894Sgblack@eecs.umich.edu pkt1->makeResponse(); 2905894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 2915894Sgblack@eecs.umich.edu } else if (read) { 2927911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 2937911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 2945894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 2955894Sgblack@eecs.umich.edu send_state->clearFromParent(); 2967911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 2977911Shestness@cs.utexas.edu pkt2->senderState); 2985894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 2995894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3005894Sgblack@eecs.umich.edu } 3015894Sgblack@eecs.umich.edu } 3025894Sgblack@eecs.umich.edu } else { 3035894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3047911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3057911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3065894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3075894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3085894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3097911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3107911Shestness@cs.utexas.edu pkt2->senderState); 3115894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3125894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3135894Sgblack@eecs.umich.edu } 3145894Sgblack@eecs.umich.edu } 3155894Sgblack@eecs.umich.edu } 3165894Sgblack@eecs.umich.edu} 3175894Sgblack@eecs.umich.edu 3185894Sgblack@eecs.umich.eduvoid 3195894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3205894Sgblack@eecs.umich.edu{ 3216739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3226739Sgblack@eecs.umich.edu // for instance prefetches. 3237823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 3247823Ssteve.reinhardt@amd.com previousTick = curTick(); 3255894Sgblack@eecs.umich.edu 3265894Sgblack@eecs.umich.edu if (traceData) { 3275894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3285894Sgblack@eecs.umich.edu delete traceData; 3295894Sgblack@eecs.umich.edu traceData = NULL; 3305744Sgblack@eecs.umich.edu } 3315744Sgblack@eecs.umich.edu 3325894Sgblack@eecs.umich.edu postExecute(); 3335894Sgblack@eecs.umich.edu 3345894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3355894Sgblack@eecs.umich.edu advancePC(fault); 3365894Sgblack@eecs.umich.edu completeDrain(); 3375894Sgblack@eecs.umich.edu } else { 3385894Sgblack@eecs.umich.edu advanceInst(fault); 3395894Sgblack@eecs.umich.edu } 3405894Sgblack@eecs.umich.edu} 3415894Sgblack@eecs.umich.edu 3425894Sgblack@eecs.umich.eduvoid 3435894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3445894Sgblack@eecs.umich.edu{ 3455894Sgblack@eecs.umich.edu MemCmd cmd; 3465894Sgblack@eecs.umich.edu if (read) { 3475894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3486102Sgblack@eecs.umich.edu if (req->isLLSC()) 3495894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3505894Sgblack@eecs.umich.edu } else { 3515894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3526102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3535894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3545894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3555894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3565894Sgblack@eecs.umich.edu } 3575894Sgblack@eecs.umich.edu } 3588949Sandreas.hansson@arm.com pkt = new Packet(req, cmd); 3595894Sgblack@eecs.umich.edu} 3605894Sgblack@eecs.umich.edu 3615894Sgblack@eecs.umich.eduvoid 3625894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3635894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3645894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3655894Sgblack@eecs.umich.edu{ 3665894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3675894Sgblack@eecs.umich.edu 3688105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3695744Sgblack@eecs.umich.edu 3705894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3715894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3725894Sgblack@eecs.umich.edu return; 3735894Sgblack@eecs.umich.edu } 3745894Sgblack@eecs.umich.edu 3755894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3765894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3775894Sgblack@eecs.umich.edu 3788832SAli.Saidi@ARM.com req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 3798949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3805744Sgblack@eecs.umich.edu 3817691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 3825744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3835744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3845744Sgblack@eecs.umich.edu 3855744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3865744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3875744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3885744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3895744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3905744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3915744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3925744Sgblack@eecs.umich.edu} 3935744Sgblack@eecs.umich.edu 3942623SN/AFault 3958444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 3968444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3972623SN/A{ 3985728Sgblack@eecs.umich.edu Fault fault; 3995728Sgblack@eecs.umich.edu const int asid = 0; 4006221Snate@binkert.org const ThreadID tid = 0; 4017720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4026227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4036973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4042623SN/A 4057045Ssteve.reinhardt@amd.com if (traceData) { 4067045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4077045Ssteve.reinhardt@amd.com } 4087045Ssteve.reinhardt@amd.com 4097520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4108832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4115728Sgblack@eecs.umich.edu 4127520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4135744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4145728Sgblack@eecs.umich.edu 4155894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4165744Sgblack@eecs.umich.edu if (split_addr > addr) { 4175894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4186102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4195894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4205894Sgblack@eecs.umich.edu 4216973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4227520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4236973Stjones1@inf.ed.ac.uk NULL, mode); 4248486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4258486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4268486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4278486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4286973Stjones1@inf.ed.ac.uk 4296973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4306973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4315744Sgblack@eecs.umich.edu } else { 4326973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4337520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4348486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4358486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4366973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4372623SN/A } 4382623SN/A 4395728Sgblack@eecs.umich.edu return NoFault; 4402623SN/A} 4412623SN/A 4425728Sgblack@eecs.umich.edubool 4435728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4445728Sgblack@eecs.umich.edu{ 4455728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4468105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4475728Sgblack@eecs.umich.edu Tick delay; 4485728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4497823Ssteve.reinhardt@amd.com new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 4505728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4515728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4528975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4535728Sgblack@eecs.umich.edu _status = DcacheRetry; 4545728Sgblack@eecs.umich.edu } else { 4555728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4565728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4575728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4585728Sgblack@eecs.umich.edu } 4595728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4605728Sgblack@eecs.umich.edu} 4612623SN/A 4622623SN/AFault 4638444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4648444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4652623SN/A{ 4668443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4678443Sgblack@eecs.umich.edu memcpy(newData, data, size); 4688443Sgblack@eecs.umich.edu 4695728Sgblack@eecs.umich.edu const int asid = 0; 4706221Snate@binkert.org const ThreadID tid = 0; 4717720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4726227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4736973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4743169Sstever@eecs.umich.edu 4757045Ssteve.reinhardt@amd.com if (traceData) { 4767045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4777045Ssteve.reinhardt@amd.com } 4787045Ssteve.reinhardt@amd.com 4797520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4808832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4815728Sgblack@eecs.umich.edu 4827520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4835744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4845728Sgblack@eecs.umich.edu 4855894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4865744Sgblack@eecs.umich.edu if (split_addr > addr) { 4875894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4886102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4895894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4905894Sgblack@eecs.umich.edu 4916973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4928443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 4938486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4948486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4958486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4968486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4976973Stjones1@inf.ed.ac.uk 4986973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4996973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5005744Sgblack@eecs.umich.edu } else { 5016973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5028443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5038486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5048486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5056973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5062623SN/A } 5072623SN/A 5087045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5095728Sgblack@eecs.umich.edu return NoFault; 5102623SN/A} 5112623SN/A 5122623SN/A 5132623SN/Avoid 5146973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5156973Stjones1@inf.ed.ac.uk{ 5166973Stjones1@inf.ed.ac.uk _status = Running; 5176973Stjones1@inf.ed.ac.uk 5186973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5196973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5206973Stjones1@inf.ed.ac.uk state->setNoFault(); 5216973Stjones1@inf.ed.ac.uk } 5227691SAli.Saidi@ARM.com delete [] state->data; 5236973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5246973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5256973Stjones1@inf.ed.ac.uk } else { 5266973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5276973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5286973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5296973Stjones1@inf.ed.ac.uk } else { 5306973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5316973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5326973Stjones1@inf.ed.ac.uk } 5336973Stjones1@inf.ed.ac.uk } 5346973Stjones1@inf.ed.ac.uk 5356973Stjones1@inf.ed.ac.uk delete state; 5366973Stjones1@inf.ed.ac.uk} 5376973Stjones1@inf.ed.ac.uk 5386973Stjones1@inf.ed.ac.uk 5396973Stjones1@inf.ed.ac.ukvoid 5402623SN/ATimingSimpleCPU::fetch() 5412623SN/A{ 5425221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5435221Ssaidi@eecs.umich.edu 5443387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5453387Sgblack@eecs.umich.edu checkForInterrupts(); 5462631SN/A 5475348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5485348Ssaidi@eecs.umich.edu 5498143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5508143SAli.Saidi@ARM.com if (_status == Idle) 5518143SAli.Saidi@ARM.com return; 5528143SAli.Saidi@ARM.com 5537720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5547720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5552623SN/A 5567720Sgblack@eecs.umich.edu if (needToFetch) { 5578276SAli.Saidi@ARM.com _status = Running; 5585669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5595712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5605894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5618277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5626023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5636023Snate@binkert.org BaseTLB::Execute); 5642623SN/A } else { 5655669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5665669Sgblack@eecs.umich.edu completeIfetch(NULL); 5675894Sgblack@eecs.umich.edu 5687823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 5697823Ssteve.reinhardt@amd.com previousTick = curTick(); 5705894Sgblack@eecs.umich.edu } 5715894Sgblack@eecs.umich.edu} 5725894Sgblack@eecs.umich.edu 5735894Sgblack@eecs.umich.edu 5745894Sgblack@eecs.umich.eduvoid 5755894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 5765894Sgblack@eecs.umich.edu{ 5775894Sgblack@eecs.umich.edu if (fault == NoFault) { 5788277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5798277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5808949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5815894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5828277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5835894Sgblack@eecs.umich.edu 5848975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5855894Sgblack@eecs.umich.edu // Need to wait for retry 5865894Sgblack@eecs.umich.edu _status = IcacheRetry; 5875894Sgblack@eecs.umich.edu } else { 5885894Sgblack@eecs.umich.edu // Need to wait for cache to respond 5895894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5905894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5915894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 5925894Sgblack@eecs.umich.edu } 5935894Sgblack@eecs.umich.edu } else { 5948277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 5955894Sgblack@eecs.umich.edu delete req; 5965894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5977945SAli.Saidi@ARM.com _status = Running; 5985894Sgblack@eecs.umich.edu advanceInst(fault); 5992623SN/A } 6003222Sktlim@umich.edu 6017823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6027823Ssteve.reinhardt@amd.com previousTick = curTick(); 6032623SN/A} 6042623SN/A 6052623SN/A 6062623SN/Avoid 6072644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6082623SN/A{ 6098276SAli.Saidi@ARM.com 6108276SAli.Saidi@ARM.com if (_status == Faulting) 6118276SAli.Saidi@ARM.com return; 6128276SAli.Saidi@ARM.com 6138276SAli.Saidi@ARM.com if (fault != NoFault) { 6148276SAli.Saidi@ARM.com advancePC(fault); 6158276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6168276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 6178276SAli.Saidi@ARM.com _status = Faulting; 6188276SAli.Saidi@ARM.com return; 6198276SAli.Saidi@ARM.com } 6208276SAli.Saidi@ARM.com 6218276SAli.Saidi@ARM.com 6228276SAli.Saidi@ARM.com if (!stayAtPC) 6235726Sgblack@eecs.umich.edu advancePC(fault); 6242623SN/A 6252631SN/A if (_status == Running) { 6262631SN/A // kick off fetch of next instruction... callback from icache 6272631SN/A // response will cause that instruction to be executed, 6282631SN/A // keeping the CPU running. 6292631SN/A fetch(); 6302631SN/A } 6312623SN/A} 6322623SN/A 6332623SN/A 6342623SN/Avoid 6353349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6362623SN/A{ 6378277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6388277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6398277SAli.Saidi@ARM.com 6402623SN/A // received a response from the icache: execute the received 6412623SN/A // instruction 6425669Sgblack@eecs.umich.edu 6435669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6442623SN/A assert(_status == IcacheWaitResponse); 6452798Sktlim@umich.edu 6462623SN/A _status = Running; 6472644Sstever@eecs.umich.edu 6487823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6497823Ssteve.reinhardt@amd.com previousTick = curTick(); 6503222Sktlim@umich.edu 6512839Sktlim@umich.edu if (getState() == SimObject::Draining) { 6525669Sgblack@eecs.umich.edu if (pkt) { 6535669Sgblack@eecs.umich.edu delete pkt->req; 6545669Sgblack@eecs.umich.edu delete pkt; 6555669Sgblack@eecs.umich.edu } 6563658Sktlim@umich.edu 6572839Sktlim@umich.edu completeDrain(); 6582798Sktlim@umich.edu return; 6592798Sktlim@umich.edu } 6602798Sktlim@umich.edu 6612623SN/A preExecute(); 6627725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6632623SN/A // load or store: just send to dcache 6642623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6657945SAli.Saidi@ARM.com 6667945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6677945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6687945SAli.Saidi@ARM.com // ifetch 6697945SAli.Saidi@ARM.com if (_status == Running) { 6705894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6715001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6725001Sgblack@eecs.umich.edu delete traceData; 6735001Sgblack@eecs.umich.edu traceData = NULL; 6743170Sstever@eecs.umich.edu } 6754998Sgblack@eecs.umich.edu 6762644Sstever@eecs.umich.edu postExecute(); 6775103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6785103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6795103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6805103Ssaidi@eecs.umich.edu instCnt++; 6812644Sstever@eecs.umich.edu advanceInst(fault); 6822644Sstever@eecs.umich.edu } 6835726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6842623SN/A // non-memory instruction: execute completely now 6852623SN/A Fault fault = curStaticInst->execute(this, traceData); 6864998Sgblack@eecs.umich.edu 6874998Sgblack@eecs.umich.edu // keep an instruction count 6884998Sgblack@eecs.umich.edu if (fault == NoFault) 6894998Sgblack@eecs.umich.edu countInst(); 6907655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6915001Sgblack@eecs.umich.edu delete traceData; 6925001Sgblack@eecs.umich.edu traceData = NULL; 6935001Sgblack@eecs.umich.edu } 6944998Sgblack@eecs.umich.edu 6952644Sstever@eecs.umich.edu postExecute(); 6965103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6975103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6985103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6995103Ssaidi@eecs.umich.edu instCnt++; 7002644Sstever@eecs.umich.edu advanceInst(fault); 7015726Sgblack@eecs.umich.edu } else { 7025726Sgblack@eecs.umich.edu advanceInst(NoFault); 7032623SN/A } 7043658Sktlim@umich.edu 7055669Sgblack@eecs.umich.edu if (pkt) { 7065669Sgblack@eecs.umich.edu delete pkt->req; 7075669Sgblack@eecs.umich.edu delete pkt; 7085669Sgblack@eecs.umich.edu } 7092623SN/A} 7102623SN/A 7112948Ssaidi@eecs.umich.eduvoid 7122948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7132948Ssaidi@eecs.umich.edu{ 7142948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7152948Ssaidi@eecs.umich.edu} 7162623SN/A 7172623SN/Abool 7188975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7192623SN/A{ 7208948Sandreas.hansson@arm.com if (!pkt->wasNacked()) { 7218277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7223310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7237823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 7242948Ssaidi@eecs.umich.edu 7257823Ssteve.reinhardt@amd.com if (next_tick == curTick()) 7263310Srdreslin@umich.edu cpu->completeIfetch(pkt); 7273310Srdreslin@umich.edu else 7283495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7292948Ssaidi@eecs.umich.edu 7303310Srdreslin@umich.edu return true; 7318948Sandreas.hansson@arm.com } else { 7324433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 7334433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7348975Sandreas.hansson@arm.com if (!sendTimingReq(pkt)) { 7354433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 7364433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 7374433Ssaidi@eecs.umich.edu } 7383310Srdreslin@umich.edu } 7398948Sandreas.hansson@arm.com 7404433Ssaidi@eecs.umich.edu return true; 7412623SN/A} 7422623SN/A 7432657Ssaidi@eecs.umich.eduvoid 7442623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7452623SN/A{ 7462623SN/A // we shouldn't get a retry unless we have a packet that we're 7472623SN/A // waiting to transmit 7482623SN/A assert(cpu->ifetch_pkt != NULL); 7492623SN/A assert(cpu->_status == IcacheRetry); 7503349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7518975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7522657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7532657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7542657Ssaidi@eecs.umich.edu } 7552623SN/A} 7562623SN/A 7572623SN/Avoid 7583349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7592623SN/A{ 7602623SN/A // received a response from the dcache: complete the load or store 7612623SN/A // instruction 7624870Sstever@eecs.umich.edu assert(!pkt->isError()); 7637516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7647516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7652623SN/A 7667823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 7677823Ssteve.reinhardt@amd.com previousTick = curTick(); 7683184Srdreslin@umich.edu 7695728Sgblack@eecs.umich.edu if (pkt->senderState) { 7705728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7715728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7725728Sgblack@eecs.umich.edu assert(send_state); 7735728Sgblack@eecs.umich.edu delete pkt->req; 7745728Sgblack@eecs.umich.edu delete pkt; 7755728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7765728Sgblack@eecs.umich.edu delete send_state; 7775728Sgblack@eecs.umich.edu 7785728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7795728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7805728Sgblack@eecs.umich.edu assert(main_send_state); 7815728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7825728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7835728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7845728Sgblack@eecs.umich.edu 7855728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7865728Sgblack@eecs.umich.edu return; 7875728Sgblack@eecs.umich.edu } else { 7885728Sgblack@eecs.umich.edu delete main_send_state; 7895728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7905728Sgblack@eecs.umich.edu pkt = big_pkt; 7915728Sgblack@eecs.umich.edu } 7925728Sgblack@eecs.umich.edu } 7935728Sgblack@eecs.umich.edu 7945728Sgblack@eecs.umich.edu _status = Running; 7955728Sgblack@eecs.umich.edu 7962623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7972623SN/A 7984998Sgblack@eecs.umich.edu // keep an instruction count 7994998Sgblack@eecs.umich.edu if (fault == NoFault) 8004998Sgblack@eecs.umich.edu countInst(); 8015001Sgblack@eecs.umich.edu else if (traceData) { 8025001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8035001Sgblack@eecs.umich.edu delete traceData; 8045001Sgblack@eecs.umich.edu traceData = NULL; 8055001Sgblack@eecs.umich.edu } 8064998Sgblack@eecs.umich.edu 8075507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 8085507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 8096102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8103170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8113170Sstever@eecs.umich.edu } 8123170Sstever@eecs.umich.edu 8132644Sstever@eecs.umich.edu delete pkt->req; 8142644Sstever@eecs.umich.edu delete pkt; 8152644Sstever@eecs.umich.edu 8163184Srdreslin@umich.edu postExecute(); 8173227Sktlim@umich.edu 8183201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 8193201Shsul@eecs.umich.edu advancePC(fault); 8203201Shsul@eecs.umich.edu completeDrain(); 8213201Shsul@eecs.umich.edu 8223201Shsul@eecs.umich.edu return; 8233201Shsul@eecs.umich.edu } 8243201Shsul@eecs.umich.edu 8252644Sstever@eecs.umich.edu advanceInst(fault); 8262623SN/A} 8272623SN/A 8282623SN/A 8292798Sktlim@umich.eduvoid 8302839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 8312798Sktlim@umich.edu{ 8322839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 8332901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 8342839Sktlim@umich.edu drainEvent->process(); 8352798Sktlim@umich.edu} 8362623SN/A 8372623SN/Abool 8388975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8392623SN/A{ 8408948Sandreas.hansson@arm.com if (!pkt->wasNacked()) { 8413310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8427823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 8432948Ssaidi@eecs.umich.edu 8447823Ssteve.reinhardt@amd.com if (next_tick == curTick()) { 8453310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 8465728Sgblack@eecs.umich.edu } else { 8477745SAli.Saidi@ARM.com if (!tickEvent.scheduled()) { 8487745SAli.Saidi@ARM.com tickEvent.schedule(pkt, next_tick); 8497745SAli.Saidi@ARM.com } else { 8507745SAli.Saidi@ARM.com // In the case of a split transaction and a cache that is 8517745SAli.Saidi@ARM.com // faster than a CPU we could get two responses before 8527745SAli.Saidi@ARM.com // next_tick expires 8537745SAli.Saidi@ARM.com if (!retryEvent.scheduled()) 8548708Sandreas.hansson@arm.com cpu->schedule(retryEvent, next_tick); 8557745SAli.Saidi@ARM.com return false; 8567745SAli.Saidi@ARM.com } 8575728Sgblack@eecs.umich.edu } 8582948Ssaidi@eecs.umich.edu 8593310Srdreslin@umich.edu return true; 8608948Sandreas.hansson@arm.com } else { 8614433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 8624433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8638975Sandreas.hansson@arm.com if (!sendTimingReq(pkt)) { 8644433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 8654433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 8664433Ssaidi@eecs.umich.edu } 8673310Srdreslin@umich.edu } 8688948Sandreas.hansson@arm.com 8694433Ssaidi@eecs.umich.edu return true; 8702948Ssaidi@eecs.umich.edu} 8712948Ssaidi@eecs.umich.edu 8722948Ssaidi@eecs.umich.eduvoid 8732948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8742948Ssaidi@eecs.umich.edu{ 8752630SN/A cpu->completeDataAccess(pkt); 8762623SN/A} 8772623SN/A 8782657Ssaidi@eecs.umich.eduvoid 8792623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8802623SN/A{ 8812623SN/A // we shouldn't get a retry unless we have a packet that we're 8822623SN/A // waiting to transmit 8832623SN/A assert(cpu->dcache_pkt != NULL); 8842623SN/A assert(cpu->_status == DcacheRetry); 8853349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8865728Sgblack@eecs.umich.edu if (tmp->senderState) { 8875728Sgblack@eecs.umich.edu // This is a packet from a split access. 8885728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8895728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8905728Sgblack@eecs.umich.edu assert(send_state); 8915728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8925728Sgblack@eecs.umich.edu 8935728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8945728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8955728Sgblack@eecs.umich.edu assert(main_send_state); 8965728Sgblack@eecs.umich.edu 8978975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8985728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8995728Sgblack@eecs.umich.edu // and try sending the other fragment. 9005728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9015728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9025728Sgblack@eecs.umich.edu if (other_index > 0) { 9035728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9045728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9055728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9065728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9075728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9085728Sgblack@eecs.umich.edu } 9095728Sgblack@eecs.umich.edu } else { 9105728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9115728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9125728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9135728Sgblack@eecs.umich.edu } 9145728Sgblack@eecs.umich.edu } 9158975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 9162657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9173170Sstever@eecs.umich.edu // memory system takes ownership of packet 9182657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9192657Ssaidi@eecs.umich.edu } 9202623SN/A} 9212623SN/A 9225606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9235606Snate@binkert.org Tick t) 9245606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9255103Ssaidi@eecs.umich.edu{ 9265606Snate@binkert.org cpu->schedule(this, t); 9275103Ssaidi@eecs.umich.edu} 9285103Ssaidi@eecs.umich.edu 9295103Ssaidi@eecs.umich.eduvoid 9305103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9315103Ssaidi@eecs.umich.edu{ 9325103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9335103Ssaidi@eecs.umich.edu} 9345103Ssaidi@eecs.umich.edu 9355103Ssaidi@eecs.umich.educonst char * 9365336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9375103Ssaidi@eecs.umich.edu{ 9385103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9395103Ssaidi@eecs.umich.edu} 9405103Ssaidi@eecs.umich.edu 9412623SN/A 9425315Sstever@gmail.comvoid 9435315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9445315Sstever@gmail.com{ 9455315Sstever@gmail.com dcachePort.printAddr(a); 9465315Sstever@gmail.com} 9475315Sstever@gmail.com 9485315Sstever@gmail.com 9492623SN/A//////////////////////////////////////////////////////////////////////// 9502623SN/A// 9512623SN/A// TimingSimpleCPU Simulation Object 9522623SN/A// 9534762Snate@binkert.orgTimingSimpleCPU * 9544762Snate@binkert.orgTimingSimpleCPUParams::create() 9552623SN/A{ 9565529Snate@binkert.org numThreads = 1; 9578779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9584762Snate@binkert.org panic("only one workload allowed"); 9595529Snate@binkert.org return new TimingSimpleCPU(this); 9602623SN/A} 961