timing.cc revision 8779
12623SN/A/* 27725SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 518232Snate@binkert.org#include "debug/ExecFaulting.hh" 528232Snate@binkert.org#include "debug/SimpleCPU.hh" 533348Sbinkertn@umich.edu#include "mem/packet.hh" 543348Sbinkertn@umich.edu#include "mem/packet_access.hh" 554762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 567678Sgblack@eecs.umich.edu#include "sim/faults.hh" 578779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 582901Ssaidi@eecs.umich.edu#include "sim/system.hh" 592623SN/A 602623SN/Ausing namespace std; 612623SN/Ausing namespace TheISA; 622623SN/A 632856Srdreslin@umich.eduPort * 642856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 652856Srdreslin@umich.edu{ 662856Srdreslin@umich.edu if (if_name == "dcache_port") 672856Srdreslin@umich.edu return &dcachePort; 682856Srdreslin@umich.edu else if (if_name == "icache_port") 692856Srdreslin@umich.edu return &icachePort; 702856Srdreslin@umich.edu else 712856Srdreslin@umich.edu panic("No Such Port\n"); 722856Srdreslin@umich.edu} 732623SN/A 742623SN/Avoid 752623SN/ATimingSimpleCPU::init() 762623SN/A{ 772623SN/A BaseCPU::init(); 788779Sgblack@eecs.umich.edu if (FullSystem) { 798779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 802623SN/A#if FULL_SYSTEM 818779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 828779Sgblack@eecs.umich.edu // initialize CPU, including PC 838779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 848779Sgblack@eecs.umich.edu#endif 858779Sgblack@eecs.umich.edu } 862623SN/A } 872623SN/A} 882623SN/A 892623SN/ATick 903349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 912623SN/A{ 922623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 937823Ssteve.reinhardt@amd.com return curTick(); 942623SN/A} 952623SN/A 962623SN/Avoid 973349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 982623SN/A{ 993184Srdreslin@umich.edu //No internal storage to update, jusst return 1003184Srdreslin@umich.edu return; 1012623SN/A} 1022623SN/A 1032623SN/Avoid 1042623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 1052623SN/A{ 1063647Srdreslin@umich.edu if (status == RangeChange) { 1073647Srdreslin@umich.edu if (!snoopRangeSent) { 1083647Srdreslin@umich.edu snoopRangeSent = true; 1093647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1103647Srdreslin@umich.edu } 1112631SN/A return; 1123647Srdreslin@umich.edu } 1132631SN/A 1142623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 1152623SN/A} 1162623SN/A 1172948Ssaidi@eecs.umich.edu 1182948Ssaidi@eecs.umich.eduvoid 1193349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1202948Ssaidi@eecs.umich.edu{ 1212948Ssaidi@eecs.umich.edu pkt = _pkt; 1225606Snate@binkert.org cpu->schedule(this, t); 1232948Ssaidi@eecs.umich.edu} 1242948Ssaidi@eecs.umich.edu 1255529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1265894Sgblack@eecs.umich.edu : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 1275894Sgblack@eecs.umich.edu dcachePort(this, p->clock), fetchEvent(this) 1282623SN/A{ 1292623SN/A _status = Idle; 1303647Srdreslin@umich.edu 1313647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1323647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1333647Srdreslin@umich.edu 1342623SN/A ifetch_pkt = dcache_pkt = NULL; 1352839Sktlim@umich.edu drainEvent = NULL; 1363222Sktlim@umich.edu previousTick = 0; 1372901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1387897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1392623SN/A} 1402623SN/A 1412623SN/A 1422623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1432623SN/A{ 1442623SN/A} 1452623SN/A 1462623SN/Avoid 1472623SN/ATimingSimpleCPU::serialize(ostream &os) 1482623SN/A{ 1492915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1502915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1512623SN/A BaseSimpleCPU::serialize(os); 1522623SN/A} 1532623SN/A 1542623SN/Avoid 1552623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1562623SN/A{ 1572915Sktlim@umich.edu SimObject::State so_state; 1582915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1592623SN/A BaseSimpleCPU::unserialize(cp, section); 1602798Sktlim@umich.edu} 1612798Sktlim@umich.edu 1622901Ssaidi@eecs.umich.eduunsigned int 1632839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1642798Sktlim@umich.edu{ 1652839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1662798Sktlim@umich.edu // an access to complete. 1675496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1682901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1692901Ssaidi@eecs.umich.edu return 0; 1702798Sktlim@umich.edu } else { 1712839Sktlim@umich.edu changeState(SimObject::Draining); 1722839Sktlim@umich.edu drainEvent = drain_event; 1732901Ssaidi@eecs.umich.edu return 1; 1742798Sktlim@umich.edu } 1752623SN/A} 1762623SN/A 1772623SN/Avoid 1782798Sktlim@umich.eduTimingSimpleCPU::resume() 1792623SN/A{ 1805221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1812798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1824762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1833201Shsul@eecs.umich.edu 1845710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1855710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1862915Sktlim@umich.edu 1875710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1882623SN/A } 1892798Sktlim@umich.edu 1902901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1912798Sktlim@umich.edu} 1922798Sktlim@umich.edu 1932798Sktlim@umich.eduvoid 1942798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1952798Sktlim@umich.edu{ 1965496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1972798Sktlim@umich.edu _status = SwitchedOut; 1987823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 1992867Sktlim@umich.edu 2002867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 2012867Sktlim@umich.edu // we'll need to cancel it. 2025710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 2035606Snate@binkert.org deschedule(fetchEvent); 2042623SN/A} 2052623SN/A 2062623SN/A 2072623SN/Avoid 2082623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2092623SN/A{ 2104192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2112623SN/A 2122680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2132623SN/A // running and schedule its tick event. 2142680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2152680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2162680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2172623SN/A _status = Running; 2182623SN/A break; 2192623SN/A } 2202623SN/A } 2213201Shsul@eecs.umich.edu 2223201Shsul@eecs.umich.edu if (_status != Running) { 2233201Shsul@eecs.umich.edu _status = Idle; 2243201Shsul@eecs.umich.edu } 2255169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2267823Ssteve.reinhardt@amd.com previousTick = curTick(); 2272623SN/A} 2282623SN/A 2292623SN/A 2302623SN/Avoid 2312623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2322623SN/A{ 2335221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2345221Ssaidi@eecs.umich.edu 2352623SN/A assert(thread_num == 0); 2362683Sktlim@umich.edu assert(thread); 2372623SN/A 2382623SN/A assert(_status == Idle); 2392623SN/A 2402623SN/A notIdleFraction++; 2412623SN/A _status = Running; 2423686Sktlim@umich.edu 2432623SN/A // kick things off by initiating the fetch of the next instruction 2447823Ssteve.reinhardt@amd.com schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 2452623SN/A} 2462623SN/A 2472623SN/A 2482623SN/Avoid 2492623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2502623SN/A{ 2515221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2525221Ssaidi@eecs.umich.edu 2532623SN/A assert(thread_num == 0); 2542683Sktlim@umich.edu assert(thread); 2552623SN/A 2566043Sgblack@eecs.umich.edu if (_status == Idle) 2576043Sgblack@eecs.umich.edu return; 2586043Sgblack@eecs.umich.edu 2592644Sstever@eecs.umich.edu assert(_status == Running); 2602623SN/A 2612644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2622644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2632623SN/A 2642623SN/A notIdleFraction--; 2652623SN/A _status = Idle; 2662623SN/A} 2672623SN/A 2685728Sgblack@eecs.umich.edubool 2695728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2705728Sgblack@eecs.umich.edu{ 2715728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2728105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2735728Sgblack@eecs.umich.edu Tick delay; 2745728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2757823Ssteve.reinhardt@amd.com new IprEvent(pkt, this, nextCycle(curTick() + delay)); 2765728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2775728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2785728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2795728Sgblack@eecs.umich.edu _status = DcacheRetry; 2805728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2815728Sgblack@eecs.umich.edu } else { 2825728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2835728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2845728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2855728Sgblack@eecs.umich.edu } 2865728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2875728Sgblack@eecs.umich.edu} 2882623SN/A 2895894Sgblack@eecs.umich.eduvoid 2906973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2916973Stjones1@inf.ed.ac.uk bool read) 2925744Sgblack@eecs.umich.edu{ 2935894Sgblack@eecs.umich.edu PacketPtr pkt; 2945894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2957691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2965894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2975894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2985894Sgblack@eecs.umich.edu pkt->makeResponse(); 2995894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3005894Sgblack@eecs.umich.edu } else if (read) { 3015894Sgblack@eecs.umich.edu handleReadPacket(pkt); 3025894Sgblack@eecs.umich.edu } else { 3035894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3045894Sgblack@eecs.umich.edu 3056102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3065894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3075894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3085894Sgblack@eecs.umich.edu assert(res); 3095894Sgblack@eecs.umich.edu req->setExtraData(*res); 3105894Sgblack@eecs.umich.edu } 3115894Sgblack@eecs.umich.edu 3125894Sgblack@eecs.umich.edu if (do_access) { 3135894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3145894Sgblack@eecs.umich.edu handleWritePacket(); 3155894Sgblack@eecs.umich.edu } else { 3165894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3175894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3185894Sgblack@eecs.umich.edu } 3195894Sgblack@eecs.umich.edu } 3205894Sgblack@eecs.umich.edu} 3215894Sgblack@eecs.umich.edu 3225894Sgblack@eecs.umich.eduvoid 3236973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3246973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3255894Sgblack@eecs.umich.edu{ 3265894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3275894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3285894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3295894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3305894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3315894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3325894Sgblack@eecs.umich.edu } else if (read) { 3337911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3347911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3355894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3365894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3377911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3387911Shestness@cs.utexas.edu pkt2->senderState); 3395894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3405894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3415894Sgblack@eecs.umich.edu } 3425894Sgblack@eecs.umich.edu } 3435894Sgblack@eecs.umich.edu } else { 3445894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3457911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3467911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3475894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3485894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3495894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3507911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3517911Shestness@cs.utexas.edu pkt2->senderState); 3525894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3535894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3545894Sgblack@eecs.umich.edu } 3555894Sgblack@eecs.umich.edu } 3565894Sgblack@eecs.umich.edu } 3575894Sgblack@eecs.umich.edu} 3585894Sgblack@eecs.umich.edu 3595894Sgblack@eecs.umich.eduvoid 3605894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3615894Sgblack@eecs.umich.edu{ 3626739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3636739Sgblack@eecs.umich.edu // for instance prefetches. 3647823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 3657823Ssteve.reinhardt@amd.com previousTick = curTick(); 3665894Sgblack@eecs.umich.edu 3675894Sgblack@eecs.umich.edu if (traceData) { 3685894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3695894Sgblack@eecs.umich.edu delete traceData; 3705894Sgblack@eecs.umich.edu traceData = NULL; 3715744Sgblack@eecs.umich.edu } 3725744Sgblack@eecs.umich.edu 3735894Sgblack@eecs.umich.edu postExecute(); 3745894Sgblack@eecs.umich.edu 3755894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3765894Sgblack@eecs.umich.edu advancePC(fault); 3775894Sgblack@eecs.umich.edu completeDrain(); 3785894Sgblack@eecs.umich.edu } else { 3795894Sgblack@eecs.umich.edu advanceInst(fault); 3805894Sgblack@eecs.umich.edu } 3815894Sgblack@eecs.umich.edu} 3825894Sgblack@eecs.umich.edu 3835894Sgblack@eecs.umich.eduvoid 3845894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3855894Sgblack@eecs.umich.edu{ 3865894Sgblack@eecs.umich.edu MemCmd cmd; 3875894Sgblack@eecs.umich.edu if (read) { 3885894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3896102Sgblack@eecs.umich.edu if (req->isLLSC()) 3905894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3915894Sgblack@eecs.umich.edu } else { 3925894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3936102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3945894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3955894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3965894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3975894Sgblack@eecs.umich.edu } 3985894Sgblack@eecs.umich.edu } 3995894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 4005894Sgblack@eecs.umich.edu} 4015894Sgblack@eecs.umich.edu 4025894Sgblack@eecs.umich.eduvoid 4035894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 4045894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 4055894Sgblack@eecs.umich.edu uint8_t *data, bool read) 4065894Sgblack@eecs.umich.edu{ 4075894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 4085894Sgblack@eecs.umich.edu 4098105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 4105744Sgblack@eecs.umich.edu 4115894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 4125894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 4135894Sgblack@eecs.umich.edu return; 4145894Sgblack@eecs.umich.edu } 4155894Sgblack@eecs.umich.edu 4165894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 4175894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 4185894Sgblack@eecs.umich.edu 4195744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 4205744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 4215744Sgblack@eecs.umich.edu Packet::Broadcast); 4225744Sgblack@eecs.umich.edu 4237691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 4245744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4255744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4265744Sgblack@eecs.umich.edu 4275744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4285744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4295744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4305744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4315744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4325744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4335744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4345744Sgblack@eecs.umich.edu} 4355744Sgblack@eecs.umich.edu 4362623SN/AFault 4378444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4388444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4392623SN/A{ 4405728Sgblack@eecs.umich.edu Fault fault; 4415728Sgblack@eecs.umich.edu const int asid = 0; 4426221Snate@binkert.org const ThreadID tid = 0; 4437720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4446227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4456973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4462623SN/A 4477045Ssteve.reinhardt@amd.com if (traceData) { 4487045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4497045Ssteve.reinhardt@amd.com } 4507045Ssteve.reinhardt@amd.com 4517520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4526221Snate@binkert.org flags, pc, _cpuId, tid); 4535728Sgblack@eecs.umich.edu 4547520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4555744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4565728Sgblack@eecs.umich.edu 4575894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4585744Sgblack@eecs.umich.edu if (split_addr > addr) { 4595894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4606102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4615894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4625894Sgblack@eecs.umich.edu 4636973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4647520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4656973Stjones1@inf.ed.ac.uk NULL, mode); 4668486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4678486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4688486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4698486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4706973Stjones1@inf.ed.ac.uk 4716973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4726973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4735744Sgblack@eecs.umich.edu } else { 4746973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4757520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4768486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4778486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4786973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4792623SN/A } 4802623SN/A 4815728Sgblack@eecs.umich.edu return NoFault; 4822623SN/A} 4832623SN/A 4845728Sgblack@eecs.umich.edubool 4855728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4865728Sgblack@eecs.umich.edu{ 4875728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4888105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4895728Sgblack@eecs.umich.edu Tick delay; 4905728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4917823Ssteve.reinhardt@amd.com new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 4925728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4935728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4945728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4955728Sgblack@eecs.umich.edu _status = DcacheRetry; 4965728Sgblack@eecs.umich.edu } else { 4975728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4985728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4995728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5005728Sgblack@eecs.umich.edu } 5015728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 5025728Sgblack@eecs.umich.edu} 5032623SN/A 5042623SN/AFault 5058444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 5068444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 5072623SN/A{ 5088443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 5098443Sgblack@eecs.umich.edu memcpy(newData, data, size); 5108443Sgblack@eecs.umich.edu 5115728Sgblack@eecs.umich.edu const int asid = 0; 5126221Snate@binkert.org const ThreadID tid = 0; 5137720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5146227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 5156973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5163169Sstever@eecs.umich.edu 5177045Ssteve.reinhardt@amd.com if (traceData) { 5187045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 5197045Ssteve.reinhardt@amd.com } 5207045Ssteve.reinhardt@amd.com 5217520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 5226221Snate@binkert.org flags, pc, _cpuId, tid); 5235728Sgblack@eecs.umich.edu 5247520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5255744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5265728Sgblack@eecs.umich.edu 5275894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5285744Sgblack@eecs.umich.edu if (split_addr > addr) { 5295894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5306102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5315894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5325894Sgblack@eecs.umich.edu 5336973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5348443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5358486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5368486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5378486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5388486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5396973Stjones1@inf.ed.ac.uk 5406973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5416973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5425744Sgblack@eecs.umich.edu } else { 5436973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5448443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5458486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5468486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5476973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5482623SN/A } 5492623SN/A 5507045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5515728Sgblack@eecs.umich.edu return NoFault; 5522623SN/A} 5532623SN/A 5542623SN/A 5552623SN/Avoid 5566973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5576973Stjones1@inf.ed.ac.uk{ 5586973Stjones1@inf.ed.ac.uk _status = Running; 5596973Stjones1@inf.ed.ac.uk 5606973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5616973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5626973Stjones1@inf.ed.ac.uk state->setNoFault(); 5636973Stjones1@inf.ed.ac.uk } 5647691SAli.Saidi@ARM.com delete [] state->data; 5656973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5666973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5676973Stjones1@inf.ed.ac.uk } else { 5686973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5696973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5706973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5716973Stjones1@inf.ed.ac.uk } else { 5726973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5736973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5746973Stjones1@inf.ed.ac.uk } 5756973Stjones1@inf.ed.ac.uk } 5766973Stjones1@inf.ed.ac.uk 5776973Stjones1@inf.ed.ac.uk delete state; 5786973Stjones1@inf.ed.ac.uk} 5796973Stjones1@inf.ed.ac.uk 5806973Stjones1@inf.ed.ac.uk 5816973Stjones1@inf.ed.ac.ukvoid 5822623SN/ATimingSimpleCPU::fetch() 5832623SN/A{ 5845221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5855221Ssaidi@eecs.umich.edu 5863387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5873387Sgblack@eecs.umich.edu checkForInterrupts(); 5882631SN/A 5895348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5905348Ssaidi@eecs.umich.edu 5918143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5928143SAli.Saidi@ARM.com if (_status == Idle) 5938143SAli.Saidi@ARM.com return; 5948143SAli.Saidi@ARM.com 5957720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5967720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5972623SN/A 5987720Sgblack@eecs.umich.edu if (needToFetch) { 5998276SAli.Saidi@ARM.com _status = Running; 6005669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 6015712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 6025894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6038277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 6046023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 6056023Snate@binkert.org BaseTLB::Execute); 6062623SN/A } else { 6075669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6085669Sgblack@eecs.umich.edu completeIfetch(NULL); 6095894Sgblack@eecs.umich.edu 6107823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6117823Ssteve.reinhardt@amd.com previousTick = curTick(); 6125894Sgblack@eecs.umich.edu } 6135894Sgblack@eecs.umich.edu} 6145894Sgblack@eecs.umich.edu 6155894Sgblack@eecs.umich.edu 6165894Sgblack@eecs.umich.eduvoid 6175894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 6185894Sgblack@eecs.umich.edu{ 6195894Sgblack@eecs.umich.edu if (fault == NoFault) { 6208277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6218277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 6225894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 6235894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6248277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6255894Sgblack@eecs.umich.edu 6265894Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 6275894Sgblack@eecs.umich.edu // Need to wait for retry 6285894Sgblack@eecs.umich.edu _status = IcacheRetry; 6295894Sgblack@eecs.umich.edu } else { 6305894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6315894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6325894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6335894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6345894Sgblack@eecs.umich.edu } 6355894Sgblack@eecs.umich.edu } else { 6368277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6375894Sgblack@eecs.umich.edu delete req; 6385894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6397945SAli.Saidi@ARM.com _status = Running; 6405894Sgblack@eecs.umich.edu advanceInst(fault); 6412623SN/A } 6423222Sktlim@umich.edu 6437823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6447823Ssteve.reinhardt@amd.com previousTick = curTick(); 6452623SN/A} 6462623SN/A 6472623SN/A 6482623SN/Avoid 6492644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6502623SN/A{ 6518276SAli.Saidi@ARM.com 6528276SAli.Saidi@ARM.com if (_status == Faulting) 6538276SAli.Saidi@ARM.com return; 6548276SAli.Saidi@ARM.com 6558276SAli.Saidi@ARM.com if (fault != NoFault) { 6568276SAli.Saidi@ARM.com advancePC(fault); 6578276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6588276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 6598276SAli.Saidi@ARM.com _status = Faulting; 6608276SAli.Saidi@ARM.com return; 6618276SAli.Saidi@ARM.com } 6628276SAli.Saidi@ARM.com 6638276SAli.Saidi@ARM.com 6648276SAli.Saidi@ARM.com if (!stayAtPC) 6655726Sgblack@eecs.umich.edu advancePC(fault); 6662623SN/A 6672631SN/A if (_status == Running) { 6682631SN/A // kick off fetch of next instruction... callback from icache 6692631SN/A // response will cause that instruction to be executed, 6702631SN/A // keeping the CPU running. 6712631SN/A fetch(); 6722631SN/A } 6732623SN/A} 6742623SN/A 6752623SN/A 6762623SN/Avoid 6773349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6782623SN/A{ 6798277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6808277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6818277SAli.Saidi@ARM.com 6822623SN/A // received a response from the icache: execute the received 6832623SN/A // instruction 6845669Sgblack@eecs.umich.edu 6855669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6862623SN/A assert(_status == IcacheWaitResponse); 6872798Sktlim@umich.edu 6882623SN/A _status = Running; 6892644Sstever@eecs.umich.edu 6907823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6917823Ssteve.reinhardt@amd.com previousTick = curTick(); 6923222Sktlim@umich.edu 6932839Sktlim@umich.edu if (getState() == SimObject::Draining) { 6945669Sgblack@eecs.umich.edu if (pkt) { 6955669Sgblack@eecs.umich.edu delete pkt->req; 6965669Sgblack@eecs.umich.edu delete pkt; 6975669Sgblack@eecs.umich.edu } 6983658Sktlim@umich.edu 6992839Sktlim@umich.edu completeDrain(); 7002798Sktlim@umich.edu return; 7012798Sktlim@umich.edu } 7022798Sktlim@umich.edu 7032623SN/A preExecute(); 7047725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 7052623SN/A // load or store: just send to dcache 7062623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 7077945SAli.Saidi@ARM.com 7087945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 7097945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 7107945SAli.Saidi@ARM.com // ifetch 7117945SAli.Saidi@ARM.com if (_status == Running) { 7125894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7135001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7145001Sgblack@eecs.umich.edu delete traceData; 7155001Sgblack@eecs.umich.edu traceData = NULL; 7163170Sstever@eecs.umich.edu } 7174998Sgblack@eecs.umich.edu 7182644Sstever@eecs.umich.edu postExecute(); 7195103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7205103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7215103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7225103Ssaidi@eecs.umich.edu instCnt++; 7232644Sstever@eecs.umich.edu advanceInst(fault); 7242644Sstever@eecs.umich.edu } 7255726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7262623SN/A // non-memory instruction: execute completely now 7272623SN/A Fault fault = curStaticInst->execute(this, traceData); 7284998Sgblack@eecs.umich.edu 7294998Sgblack@eecs.umich.edu // keep an instruction count 7304998Sgblack@eecs.umich.edu if (fault == NoFault) 7314998Sgblack@eecs.umich.edu countInst(); 7327655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7335001Sgblack@eecs.umich.edu delete traceData; 7345001Sgblack@eecs.umich.edu traceData = NULL; 7355001Sgblack@eecs.umich.edu } 7364998Sgblack@eecs.umich.edu 7372644Sstever@eecs.umich.edu postExecute(); 7385103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7395103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7405103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7415103Ssaidi@eecs.umich.edu instCnt++; 7422644Sstever@eecs.umich.edu advanceInst(fault); 7435726Sgblack@eecs.umich.edu } else { 7445726Sgblack@eecs.umich.edu advanceInst(NoFault); 7452623SN/A } 7463658Sktlim@umich.edu 7475669Sgblack@eecs.umich.edu if (pkt) { 7485669Sgblack@eecs.umich.edu delete pkt->req; 7495669Sgblack@eecs.umich.edu delete pkt; 7505669Sgblack@eecs.umich.edu } 7512623SN/A} 7522623SN/A 7532948Ssaidi@eecs.umich.eduvoid 7542948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7552948Ssaidi@eecs.umich.edu{ 7562948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7572948Ssaidi@eecs.umich.edu} 7582623SN/A 7592623SN/Abool 7603349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 7612623SN/A{ 7624986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7638277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7643310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7657823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 7662948Ssaidi@eecs.umich.edu 7677823Ssteve.reinhardt@amd.com if (next_tick == curTick()) 7683310Srdreslin@umich.edu cpu->completeIfetch(pkt); 7693310Srdreslin@umich.edu else 7703495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7712948Ssaidi@eecs.umich.edu 7723310Srdreslin@umich.edu return true; 7738276SAli.Saidi@ARM.com } else if (pkt->wasNacked()) { 7744433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 7754433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7764433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7774433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 7784433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 7794433Ssaidi@eecs.umich.edu } 7803310Srdreslin@umich.edu } 7814433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7824433Ssaidi@eecs.umich.edu return true; 7832623SN/A} 7842623SN/A 7852657Ssaidi@eecs.umich.eduvoid 7862623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7872623SN/A{ 7882623SN/A // we shouldn't get a retry unless we have a packet that we're 7892623SN/A // waiting to transmit 7902623SN/A assert(cpu->ifetch_pkt != NULL); 7912623SN/A assert(cpu->_status == IcacheRetry); 7923349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7932657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7942657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7952657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7962657Ssaidi@eecs.umich.edu } 7972623SN/A} 7982623SN/A 7992623SN/Avoid 8003349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8012623SN/A{ 8022623SN/A // received a response from the dcache: complete the load or store 8032623SN/A // instruction 8044870Sstever@eecs.umich.edu assert(!pkt->isError()); 8057516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 8067516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8072623SN/A 8087823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 8097823Ssteve.reinhardt@amd.com previousTick = curTick(); 8103184Srdreslin@umich.edu 8115728Sgblack@eecs.umich.edu if (pkt->senderState) { 8125728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8135728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8145728Sgblack@eecs.umich.edu assert(send_state); 8155728Sgblack@eecs.umich.edu delete pkt->req; 8165728Sgblack@eecs.umich.edu delete pkt; 8175728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8185728Sgblack@eecs.umich.edu delete send_state; 8195728Sgblack@eecs.umich.edu 8205728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8215728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8225728Sgblack@eecs.umich.edu assert(main_send_state); 8235728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8245728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8255728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8265728Sgblack@eecs.umich.edu 8275728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8285728Sgblack@eecs.umich.edu return; 8295728Sgblack@eecs.umich.edu } else { 8305728Sgblack@eecs.umich.edu delete main_send_state; 8315728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8325728Sgblack@eecs.umich.edu pkt = big_pkt; 8335728Sgblack@eecs.umich.edu } 8345728Sgblack@eecs.umich.edu } 8355728Sgblack@eecs.umich.edu 8365728Sgblack@eecs.umich.edu _status = Running; 8375728Sgblack@eecs.umich.edu 8382623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 8392623SN/A 8404998Sgblack@eecs.umich.edu // keep an instruction count 8414998Sgblack@eecs.umich.edu if (fault == NoFault) 8424998Sgblack@eecs.umich.edu countInst(); 8435001Sgblack@eecs.umich.edu else if (traceData) { 8445001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8455001Sgblack@eecs.umich.edu delete traceData; 8465001Sgblack@eecs.umich.edu traceData = NULL; 8475001Sgblack@eecs.umich.edu } 8484998Sgblack@eecs.umich.edu 8495507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 8505507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 8516102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8523170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8533170Sstever@eecs.umich.edu } 8543170Sstever@eecs.umich.edu 8552644Sstever@eecs.umich.edu delete pkt->req; 8562644Sstever@eecs.umich.edu delete pkt; 8572644Sstever@eecs.umich.edu 8583184Srdreslin@umich.edu postExecute(); 8593227Sktlim@umich.edu 8603201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 8613201Shsul@eecs.umich.edu advancePC(fault); 8623201Shsul@eecs.umich.edu completeDrain(); 8633201Shsul@eecs.umich.edu 8643201Shsul@eecs.umich.edu return; 8653201Shsul@eecs.umich.edu } 8663201Shsul@eecs.umich.edu 8672644Sstever@eecs.umich.edu advanceInst(fault); 8682623SN/A} 8692623SN/A 8702623SN/A 8712798Sktlim@umich.eduvoid 8722839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 8732798Sktlim@umich.edu{ 8742839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 8752901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 8762839Sktlim@umich.edu drainEvent->process(); 8772798Sktlim@umich.edu} 8782623SN/A 8794192Sktlim@umich.eduvoid 8804192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 8814192Sktlim@umich.edu{ 8824192Sktlim@umich.edu Port::setPeer(port); 8834192Sktlim@umich.edu 8848779Sgblack@eecs.umich.edu if (FullSystem) { 8858779Sgblack@eecs.umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 8868779Sgblack@eecs.umich.edu // Ports) 8878779Sgblack@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 8888779Sgblack@eecs.umich.edu } 8894192Sktlim@umich.edu} 8904192Sktlim@umich.edu 8912623SN/Abool 8923349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 8932623SN/A{ 8944986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8953310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8967823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 8972948Ssaidi@eecs.umich.edu 8987823Ssteve.reinhardt@amd.com if (next_tick == curTick()) { 8993310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 9005728Sgblack@eecs.umich.edu } else { 9017745SAli.Saidi@ARM.com if (!tickEvent.scheduled()) { 9027745SAli.Saidi@ARM.com tickEvent.schedule(pkt, next_tick); 9037745SAli.Saidi@ARM.com } else { 9047745SAli.Saidi@ARM.com // In the case of a split transaction and a cache that is 9057745SAli.Saidi@ARM.com // faster than a CPU we could get two responses before 9067745SAli.Saidi@ARM.com // next_tick expires 9077745SAli.Saidi@ARM.com if (!retryEvent.scheduled()) 9087745SAli.Saidi@ARM.com schedule(retryEvent, next_tick); 9097745SAli.Saidi@ARM.com return false; 9107745SAli.Saidi@ARM.com } 9115728Sgblack@eecs.umich.edu } 9122948Ssaidi@eecs.umich.edu 9133310Srdreslin@umich.edu return true; 9143310Srdreslin@umich.edu } 9154870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 9164433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 9174433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 9184433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 9194433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 9204433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 9214433Ssaidi@eecs.umich.edu } 9223310Srdreslin@umich.edu } 9234433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 9244433Ssaidi@eecs.umich.edu return true; 9252948Ssaidi@eecs.umich.edu} 9262948Ssaidi@eecs.umich.edu 9272948Ssaidi@eecs.umich.eduvoid 9282948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9292948Ssaidi@eecs.umich.edu{ 9302630SN/A cpu->completeDataAccess(pkt); 9312623SN/A} 9322623SN/A 9332657Ssaidi@eecs.umich.eduvoid 9342623SN/ATimingSimpleCPU::DcachePort::recvRetry() 9352623SN/A{ 9362623SN/A // we shouldn't get a retry unless we have a packet that we're 9372623SN/A // waiting to transmit 9382623SN/A assert(cpu->dcache_pkt != NULL); 9392623SN/A assert(cpu->_status == DcacheRetry); 9403349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9415728Sgblack@eecs.umich.edu if (tmp->senderState) { 9425728Sgblack@eecs.umich.edu // This is a packet from a split access. 9435728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9445728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9455728Sgblack@eecs.umich.edu assert(send_state); 9465728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9475728Sgblack@eecs.umich.edu 9485728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9495728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9505728Sgblack@eecs.umich.edu assert(main_send_state); 9515728Sgblack@eecs.umich.edu 9525728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 9535728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9545728Sgblack@eecs.umich.edu // and try sending the other fragment. 9555728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9565728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9575728Sgblack@eecs.umich.edu if (other_index > 0) { 9585728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9595728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9605728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9615728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9625728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9635728Sgblack@eecs.umich.edu } 9645728Sgblack@eecs.umich.edu } else { 9655728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9665728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9675728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9685728Sgblack@eecs.umich.edu } 9695728Sgblack@eecs.umich.edu } 9705728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 9712657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9723170Sstever@eecs.umich.edu // memory system takes ownership of packet 9732657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9742657Ssaidi@eecs.umich.edu } 9752623SN/A} 9762623SN/A 9775606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9785606Snate@binkert.org Tick t) 9795606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9805103Ssaidi@eecs.umich.edu{ 9815606Snate@binkert.org cpu->schedule(this, t); 9825103Ssaidi@eecs.umich.edu} 9835103Ssaidi@eecs.umich.edu 9845103Ssaidi@eecs.umich.eduvoid 9855103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9865103Ssaidi@eecs.umich.edu{ 9875103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9885103Ssaidi@eecs.umich.edu} 9895103Ssaidi@eecs.umich.edu 9905103Ssaidi@eecs.umich.educonst char * 9915336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9925103Ssaidi@eecs.umich.edu{ 9935103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9945103Ssaidi@eecs.umich.edu} 9955103Ssaidi@eecs.umich.edu 9962623SN/A 9975315Sstever@gmail.comvoid 9985315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9995315Sstever@gmail.com{ 10005315Sstever@gmail.com dcachePort.printAddr(a); 10015315Sstever@gmail.com} 10025315Sstever@gmail.com 10035315Sstever@gmail.com 10042623SN/A//////////////////////////////////////////////////////////////////////// 10052623SN/A// 10062623SN/A// TimingSimpleCPU Simulation Object 10072623SN/A// 10084762Snate@binkert.orgTimingSimpleCPU * 10094762Snate@binkert.orgTimingSimpleCPUParams::create() 10102623SN/A{ 10115529Snate@binkert.org numThreads = 1; 10125529Snate@binkert.org#if !FULL_SYSTEM 10138779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 10144762Snate@binkert.org panic("only one workload allowed"); 10152623SN/A#endif 10165529Snate@binkert.org return new TimingSimpleCPU(this); 10172623SN/A} 1018