timing.cc revision 8276
12623SN/A/* 27725SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 518232Snate@binkert.org#include "debug/ExecFaulting.hh" 528232Snate@binkert.org#include "debug/SimpleCPU.hh" 533348Sbinkertn@umich.edu#include "mem/packet.hh" 543348Sbinkertn@umich.edu#include "mem/packet_access.hh" 554762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 567678Sgblack@eecs.umich.edu#include "sim/faults.hh" 572901Ssaidi@eecs.umich.edu#include "sim/system.hh" 582623SN/A 592623SN/Ausing namespace std; 602623SN/Ausing namespace TheISA; 612623SN/A 622856Srdreslin@umich.eduPort * 632856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 642856Srdreslin@umich.edu{ 652856Srdreslin@umich.edu if (if_name == "dcache_port") 662856Srdreslin@umich.edu return &dcachePort; 672856Srdreslin@umich.edu else if (if_name == "icache_port") 682856Srdreslin@umich.edu return &icachePort; 692856Srdreslin@umich.edu else 702856Srdreslin@umich.edu panic("No Such Port\n"); 712856Srdreslin@umich.edu} 722623SN/A 732623SN/Avoid 742623SN/ATimingSimpleCPU::init() 752623SN/A{ 762623SN/A BaseCPU::init(); 772623SN/A#if FULL_SYSTEM 782680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 792680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 802623SN/A 812623SN/A // initialize CPU, including PC 825712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 832623SN/A } 842623SN/A#endif 852623SN/A} 862623SN/A 872623SN/ATick 883349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 892623SN/A{ 902623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 917823Ssteve.reinhardt@amd.com return curTick(); 922623SN/A} 932623SN/A 942623SN/Avoid 953349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 962623SN/A{ 973184Srdreslin@umich.edu //No internal storage to update, jusst return 983184Srdreslin@umich.edu return; 992623SN/A} 1002623SN/A 1012623SN/Avoid 1022623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 1032623SN/A{ 1043647Srdreslin@umich.edu if (status == RangeChange) { 1053647Srdreslin@umich.edu if (!snoopRangeSent) { 1063647Srdreslin@umich.edu snoopRangeSent = true; 1073647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1083647Srdreslin@umich.edu } 1092631SN/A return; 1103647Srdreslin@umich.edu } 1112631SN/A 1122623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 1132623SN/A} 1142623SN/A 1152948Ssaidi@eecs.umich.edu 1162948Ssaidi@eecs.umich.eduvoid 1173349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1182948Ssaidi@eecs.umich.edu{ 1192948Ssaidi@eecs.umich.edu pkt = _pkt; 1205606Snate@binkert.org cpu->schedule(this, t); 1212948Ssaidi@eecs.umich.edu} 1222948Ssaidi@eecs.umich.edu 1235529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1245894Sgblack@eecs.umich.edu : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 1255894Sgblack@eecs.umich.edu dcachePort(this, p->clock), fetchEvent(this) 1262623SN/A{ 1272623SN/A _status = Idle; 1283647Srdreslin@umich.edu 1293647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1303647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1313647Srdreslin@umich.edu 1322623SN/A ifetch_pkt = dcache_pkt = NULL; 1332839Sktlim@umich.edu drainEvent = NULL; 1343222Sktlim@umich.edu previousTick = 0; 1352901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1367897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1372623SN/A} 1382623SN/A 1392623SN/A 1402623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1412623SN/A{ 1422623SN/A} 1432623SN/A 1442623SN/Avoid 1452623SN/ATimingSimpleCPU::serialize(ostream &os) 1462623SN/A{ 1472915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1482915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1492623SN/A BaseSimpleCPU::serialize(os); 1502623SN/A} 1512623SN/A 1522623SN/Avoid 1532623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1542623SN/A{ 1552915Sktlim@umich.edu SimObject::State so_state; 1562915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1572623SN/A BaseSimpleCPU::unserialize(cp, section); 1582798Sktlim@umich.edu} 1592798Sktlim@umich.edu 1602901Ssaidi@eecs.umich.eduunsigned int 1612839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1622798Sktlim@umich.edu{ 1632839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1642798Sktlim@umich.edu // an access to complete. 1655496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1662901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1672901Ssaidi@eecs.umich.edu return 0; 1682798Sktlim@umich.edu } else { 1692839Sktlim@umich.edu changeState(SimObject::Draining); 1702839Sktlim@umich.edu drainEvent = drain_event; 1712901Ssaidi@eecs.umich.edu return 1; 1722798Sktlim@umich.edu } 1732623SN/A} 1742623SN/A 1752623SN/Avoid 1762798Sktlim@umich.eduTimingSimpleCPU::resume() 1772623SN/A{ 1785221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1792798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1804762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1813201Shsul@eecs.umich.edu 1825710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1835710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1842915Sktlim@umich.edu 1855710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1862623SN/A } 1872798Sktlim@umich.edu 1882901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1892798Sktlim@umich.edu} 1902798Sktlim@umich.edu 1912798Sktlim@umich.eduvoid 1922798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1932798Sktlim@umich.edu{ 1945496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1952798Sktlim@umich.edu _status = SwitchedOut; 1967823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 1972867Sktlim@umich.edu 1982867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1992867Sktlim@umich.edu // we'll need to cancel it. 2005710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 2015606Snate@binkert.org deschedule(fetchEvent); 2022623SN/A} 2032623SN/A 2042623SN/A 2052623SN/Avoid 2062623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2072623SN/A{ 2084192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2092623SN/A 2102680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2112623SN/A // running and schedule its tick event. 2122680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2132680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2142680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2152623SN/A _status = Running; 2162623SN/A break; 2172623SN/A } 2182623SN/A } 2193201Shsul@eecs.umich.edu 2203201Shsul@eecs.umich.edu if (_status != Running) { 2213201Shsul@eecs.umich.edu _status = Idle; 2223201Shsul@eecs.umich.edu } 2235169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2247823Ssteve.reinhardt@amd.com previousTick = curTick(); 2252623SN/A} 2262623SN/A 2272623SN/A 2282623SN/Avoid 2292623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2302623SN/A{ 2315221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2325221Ssaidi@eecs.umich.edu 2332623SN/A assert(thread_num == 0); 2342683Sktlim@umich.edu assert(thread); 2352623SN/A 2362623SN/A assert(_status == Idle); 2372623SN/A 2382623SN/A notIdleFraction++; 2392623SN/A _status = Running; 2403686Sktlim@umich.edu 2412623SN/A // kick things off by initiating the fetch of the next instruction 2427823Ssteve.reinhardt@amd.com schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 2432623SN/A} 2442623SN/A 2452623SN/A 2462623SN/Avoid 2472623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2482623SN/A{ 2495221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2505221Ssaidi@eecs.umich.edu 2512623SN/A assert(thread_num == 0); 2522683Sktlim@umich.edu assert(thread); 2532623SN/A 2546043Sgblack@eecs.umich.edu if (_status == Idle) 2556043Sgblack@eecs.umich.edu return; 2566043Sgblack@eecs.umich.edu 2572644Sstever@eecs.umich.edu assert(_status == Running); 2582623SN/A 2592644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2602644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2612623SN/A 2622623SN/A notIdleFraction--; 2632623SN/A _status = Idle; 2642623SN/A} 2652623SN/A 2665728Sgblack@eecs.umich.edubool 2675728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2685728Sgblack@eecs.umich.edu{ 2695728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2708105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2715728Sgblack@eecs.umich.edu Tick delay; 2725728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2737823Ssteve.reinhardt@amd.com new IprEvent(pkt, this, nextCycle(curTick() + delay)); 2745728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2755728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2765728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2775728Sgblack@eecs.umich.edu _status = DcacheRetry; 2785728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2795728Sgblack@eecs.umich.edu } else { 2805728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2815728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2825728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2835728Sgblack@eecs.umich.edu } 2845728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2855728Sgblack@eecs.umich.edu} 2862623SN/A 2875894Sgblack@eecs.umich.eduvoid 2886973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2896973Stjones1@inf.ed.ac.uk bool read) 2905744Sgblack@eecs.umich.edu{ 2915894Sgblack@eecs.umich.edu PacketPtr pkt; 2925894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2937691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2945894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2955894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2965894Sgblack@eecs.umich.edu pkt->makeResponse(); 2975894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2985894Sgblack@eecs.umich.edu } else if (read) { 2995894Sgblack@eecs.umich.edu handleReadPacket(pkt); 3005894Sgblack@eecs.umich.edu } else { 3015894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3025894Sgblack@eecs.umich.edu 3036102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3045894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3055894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3065894Sgblack@eecs.umich.edu assert(res); 3075894Sgblack@eecs.umich.edu req->setExtraData(*res); 3085894Sgblack@eecs.umich.edu } 3095894Sgblack@eecs.umich.edu 3105894Sgblack@eecs.umich.edu if (do_access) { 3115894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3125894Sgblack@eecs.umich.edu handleWritePacket(); 3135894Sgblack@eecs.umich.edu } else { 3145894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3155894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3165894Sgblack@eecs.umich.edu } 3175894Sgblack@eecs.umich.edu } 3185894Sgblack@eecs.umich.edu} 3195894Sgblack@eecs.umich.edu 3205894Sgblack@eecs.umich.eduvoid 3216973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3226973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3235894Sgblack@eecs.umich.edu{ 3245894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3255894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3265894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3275894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3285894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3295894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3305894Sgblack@eecs.umich.edu } else if (read) { 3317911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3327911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3335894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3345894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3357911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3367911Shestness@cs.utexas.edu pkt2->senderState); 3375894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3385894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3395894Sgblack@eecs.umich.edu } 3405894Sgblack@eecs.umich.edu } 3415894Sgblack@eecs.umich.edu } else { 3425894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3437911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3447911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3455894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3465894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3475894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3487911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3497911Shestness@cs.utexas.edu pkt2->senderState); 3505894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3515894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3525894Sgblack@eecs.umich.edu } 3535894Sgblack@eecs.umich.edu } 3545894Sgblack@eecs.umich.edu } 3555894Sgblack@eecs.umich.edu} 3565894Sgblack@eecs.umich.edu 3575894Sgblack@eecs.umich.eduvoid 3585894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3595894Sgblack@eecs.umich.edu{ 3606739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3616739Sgblack@eecs.umich.edu // for instance prefetches. 3627823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 3637823Ssteve.reinhardt@amd.com previousTick = curTick(); 3645894Sgblack@eecs.umich.edu 3655894Sgblack@eecs.umich.edu if (traceData) { 3665894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3675894Sgblack@eecs.umich.edu delete traceData; 3685894Sgblack@eecs.umich.edu traceData = NULL; 3695744Sgblack@eecs.umich.edu } 3705744Sgblack@eecs.umich.edu 3715894Sgblack@eecs.umich.edu postExecute(); 3725894Sgblack@eecs.umich.edu 3735894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3745894Sgblack@eecs.umich.edu advancePC(fault); 3755894Sgblack@eecs.umich.edu completeDrain(); 3765894Sgblack@eecs.umich.edu } else { 3775894Sgblack@eecs.umich.edu advanceInst(fault); 3785894Sgblack@eecs.umich.edu } 3795894Sgblack@eecs.umich.edu} 3805894Sgblack@eecs.umich.edu 3815894Sgblack@eecs.umich.eduvoid 3825894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3835894Sgblack@eecs.umich.edu{ 3845894Sgblack@eecs.umich.edu MemCmd cmd; 3855894Sgblack@eecs.umich.edu if (read) { 3865894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3876102Sgblack@eecs.umich.edu if (req->isLLSC()) 3885894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3895894Sgblack@eecs.umich.edu } else { 3905894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3916102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3925894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3935894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3945894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3955894Sgblack@eecs.umich.edu } 3965894Sgblack@eecs.umich.edu } 3975894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 3985894Sgblack@eecs.umich.edu} 3995894Sgblack@eecs.umich.edu 4005894Sgblack@eecs.umich.eduvoid 4015894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 4025894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 4035894Sgblack@eecs.umich.edu uint8_t *data, bool read) 4045894Sgblack@eecs.umich.edu{ 4055894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 4065894Sgblack@eecs.umich.edu 4078105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 4085744Sgblack@eecs.umich.edu 4095894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 4105894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 4115894Sgblack@eecs.umich.edu return; 4125894Sgblack@eecs.umich.edu } 4135894Sgblack@eecs.umich.edu 4145894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 4155894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 4165894Sgblack@eecs.umich.edu 4175744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 4185744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 4195744Sgblack@eecs.umich.edu Packet::Broadcast); 4205744Sgblack@eecs.umich.edu 4217691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 4225744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4235744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4245744Sgblack@eecs.umich.edu 4255744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4265744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4275744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4285744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4295744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4305744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4315744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4325744Sgblack@eecs.umich.edu} 4335744Sgblack@eecs.umich.edu 4342623SN/AFault 4357520Sgblack@eecs.umich.eduTimingSimpleCPU::readBytes(Addr addr, uint8_t *data, 4367520Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4372623SN/A{ 4385728Sgblack@eecs.umich.edu Fault fault; 4395728Sgblack@eecs.umich.edu const int asid = 0; 4406221Snate@binkert.org const ThreadID tid = 0; 4417720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4426227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4436973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4442623SN/A 4457045Ssteve.reinhardt@amd.com if (traceData) { 4467045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4477045Ssteve.reinhardt@amd.com } 4487045Ssteve.reinhardt@amd.com 4497520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4506221Snate@binkert.org flags, pc, _cpuId, tid); 4515728Sgblack@eecs.umich.edu 4527520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4535744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4545728Sgblack@eecs.umich.edu 4555894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4565744Sgblack@eecs.umich.edu if (split_addr > addr) { 4575894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4586102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4595894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4605894Sgblack@eecs.umich.edu 4616973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4627520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4636973Stjones1@inf.ed.ac.uk NULL, mode); 4646973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 4656973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 4666973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 4676973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 4686973Stjones1@inf.ed.ac.uk 4696973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4706973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4715744Sgblack@eecs.umich.edu } else { 4726973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4737520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4746973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation 4756973Stjones1@inf.ed.ac.uk = new DataTranslation<TimingSimpleCPU>(this, state); 4766973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4772623SN/A } 4782623SN/A 4795728Sgblack@eecs.umich.edu return NoFault; 4802623SN/A} 4812623SN/A 4827520Sgblack@eecs.umich.edutemplate <class T> 4837520Sgblack@eecs.umich.eduFault 4847520Sgblack@eecs.umich.eduTimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 4857520Sgblack@eecs.umich.edu{ 4867520Sgblack@eecs.umich.edu return readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 4877520Sgblack@eecs.umich.edu} 4887520Sgblack@eecs.umich.edu 4892623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4902623SN/A 4912623SN/Atemplate 4922623SN/AFault 4934040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 4944040Ssaidi@eecs.umich.edu 4954040Ssaidi@eecs.umich.edutemplate 4964040Ssaidi@eecs.umich.eduFault 4974115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 4984115Ssaidi@eecs.umich.edu 4994115Ssaidi@eecs.umich.edutemplate 5004115Ssaidi@eecs.umich.eduFault 5012623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 5022623SN/A 5032623SN/Atemplate 5042623SN/AFault 5052623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 5062623SN/A 5072623SN/Atemplate 5082623SN/AFault 5092623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 5102623SN/A 5112623SN/Atemplate 5122623SN/AFault 5132623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 5142623SN/A 5152623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5162623SN/A 5172623SN/Atemplate<> 5182623SN/AFault 5192623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 5202623SN/A{ 5212623SN/A return read(addr, *(uint64_t*)&data, flags); 5222623SN/A} 5232623SN/A 5242623SN/Atemplate<> 5252623SN/AFault 5262623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 5272623SN/A{ 5282623SN/A return read(addr, *(uint32_t*)&data, flags); 5292623SN/A} 5302623SN/A 5312623SN/Atemplate<> 5322623SN/AFault 5332623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 5342623SN/A{ 5352623SN/A return read(addr, (uint32_t&)data, flags); 5362623SN/A} 5372623SN/A 5385728Sgblack@eecs.umich.edubool 5395728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 5405728Sgblack@eecs.umich.edu{ 5415728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 5428105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 5435728Sgblack@eecs.umich.edu Tick delay; 5445728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 5457823Ssteve.reinhardt@amd.com new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 5465728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5475728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5485728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 5495728Sgblack@eecs.umich.edu _status = DcacheRetry; 5505728Sgblack@eecs.umich.edu } else { 5515728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5525728Sgblack@eecs.umich.edu // memory system takes ownership of packet 5535728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5545728Sgblack@eecs.umich.edu } 5555728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 5565728Sgblack@eecs.umich.edu} 5572623SN/A 5582623SN/AFault 5597520Sgblack@eecs.umich.eduTimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size, 5607520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 5612623SN/A{ 5625728Sgblack@eecs.umich.edu const int asid = 0; 5636221Snate@binkert.org const ThreadID tid = 0; 5647720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5656227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 5666973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5673169Sstever@eecs.umich.edu 5687045Ssteve.reinhardt@amd.com if (traceData) { 5697045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 5707045Ssteve.reinhardt@amd.com } 5717045Ssteve.reinhardt@amd.com 5727520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 5736221Snate@binkert.org flags, pc, _cpuId, tid); 5745728Sgblack@eecs.umich.edu 5757520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5765744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5775728Sgblack@eecs.umich.edu 5785894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5795744Sgblack@eecs.umich.edu if (split_addr > addr) { 5805894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5816102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5825894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5835894Sgblack@eecs.umich.edu 5846973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5857520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, data, res, mode); 5866973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 5876973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 5886973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 5896973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 5906973Stjones1@inf.ed.ac.uk 5916973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5926973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5935744Sgblack@eecs.umich.edu } else { 5946973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5957520Sgblack@eecs.umich.edu new WholeTranslationState(req, data, res, mode); 5966973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation = 5976973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state); 5986973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5992623SN/A } 6002623SN/A 6017045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 6025728Sgblack@eecs.umich.edu return NoFault; 6032623SN/A} 6042623SN/A 6057520Sgblack@eecs.umich.eduFault 6067520Sgblack@eecs.umich.eduTimingSimpleCPU::writeBytes(uint8_t *data, unsigned size, 6077520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 6087520Sgblack@eecs.umich.edu{ 6097520Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 6107520Sgblack@eecs.umich.edu memcpy(newData, data, size); 6117520Sgblack@eecs.umich.edu return writeTheseBytes(newData, size, addr, flags, res); 6127520Sgblack@eecs.umich.edu} 6137520Sgblack@eecs.umich.edu 6147520Sgblack@eecs.umich.edutemplate <class T> 6157520Sgblack@eecs.umich.eduFault 6167520Sgblack@eecs.umich.eduTimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 6177520Sgblack@eecs.umich.edu{ 6187520Sgblack@eecs.umich.edu if (traceData) { 6197520Sgblack@eecs.umich.edu traceData->setData(data); 6207520Sgblack@eecs.umich.edu } 6217691SAli.Saidi@ARM.com T *dataP = (T*) new uint8_t[sizeof(T)]; 6227520Sgblack@eecs.umich.edu *dataP = TheISA::htog(data); 6237520Sgblack@eecs.umich.edu 6247520Sgblack@eecs.umich.edu return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res); 6257520Sgblack@eecs.umich.edu} 6267520Sgblack@eecs.umich.edu 6272623SN/A 6282623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 6292623SN/Atemplate 6302623SN/AFault 6314224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 6324224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6334224Sgblack@eecs.umich.edu 6344224Sgblack@eecs.umich.edutemplate 6354224Sgblack@eecs.umich.eduFault 6364224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 6374224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6384224Sgblack@eecs.umich.edu 6394224Sgblack@eecs.umich.edutemplate 6404224Sgblack@eecs.umich.eduFault 6412623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 6422623SN/A unsigned flags, uint64_t *res); 6432623SN/A 6442623SN/Atemplate 6452623SN/AFault 6462623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 6472623SN/A unsigned flags, uint64_t *res); 6482623SN/A 6492623SN/Atemplate 6502623SN/AFault 6512623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 6522623SN/A unsigned flags, uint64_t *res); 6532623SN/A 6542623SN/Atemplate 6552623SN/AFault 6562623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 6572623SN/A unsigned flags, uint64_t *res); 6582623SN/A 6592623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 6602623SN/A 6612623SN/Atemplate<> 6622623SN/AFault 6632623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 6642623SN/A{ 6652623SN/A return write(*(uint64_t*)&data, addr, flags, res); 6662623SN/A} 6672623SN/A 6682623SN/Atemplate<> 6692623SN/AFault 6702623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 6712623SN/A{ 6722623SN/A return write(*(uint32_t*)&data, addr, flags, res); 6732623SN/A} 6742623SN/A 6752623SN/A 6762623SN/Atemplate<> 6772623SN/AFault 6782623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6792623SN/A{ 6802623SN/A return write((uint32_t)data, addr, flags, res); 6812623SN/A} 6822623SN/A 6832623SN/A 6842623SN/Avoid 6856973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 6866973Stjones1@inf.ed.ac.uk{ 6876973Stjones1@inf.ed.ac.uk _status = Running; 6886973Stjones1@inf.ed.ac.uk 6896973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 6906973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 6916973Stjones1@inf.ed.ac.uk state->setNoFault(); 6926973Stjones1@inf.ed.ac.uk } 6937691SAli.Saidi@ARM.com delete [] state->data; 6946973Stjones1@inf.ed.ac.uk state->deleteReqs(); 6956973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 6966973Stjones1@inf.ed.ac.uk } else { 6976973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 6986973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 6996973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 7006973Stjones1@inf.ed.ac.uk } else { 7016973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 7026973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 7036973Stjones1@inf.ed.ac.uk } 7046973Stjones1@inf.ed.ac.uk } 7056973Stjones1@inf.ed.ac.uk 7066973Stjones1@inf.ed.ac.uk delete state; 7076973Stjones1@inf.ed.ac.uk} 7086973Stjones1@inf.ed.ac.uk 7096973Stjones1@inf.ed.ac.uk 7106973Stjones1@inf.ed.ac.ukvoid 7112623SN/ATimingSimpleCPU::fetch() 7122623SN/A{ 7135221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 7145221Ssaidi@eecs.umich.edu 7153387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 7163387Sgblack@eecs.umich.edu checkForInterrupts(); 7172631SN/A 7185348Ssaidi@eecs.umich.edu checkPcEventQueue(); 7195348Ssaidi@eecs.umich.edu 7208143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 7218143SAli.Saidi@ARM.com if (_status == Idle) 7228143SAli.Saidi@ARM.com return; 7238143SAli.Saidi@ARM.com 7247720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 7257720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 7262623SN/A 7277720Sgblack@eecs.umich.edu if (needToFetch) { 7288276SAli.Saidi@ARM.com _status = Running; 7295669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 7305712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 7315894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 7326023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 7336023Snate@binkert.org BaseTLB::Execute); 7342623SN/A } else { 7355669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7365669Sgblack@eecs.umich.edu completeIfetch(NULL); 7375894Sgblack@eecs.umich.edu 7387823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 7397823Ssteve.reinhardt@amd.com previousTick = curTick(); 7405894Sgblack@eecs.umich.edu } 7415894Sgblack@eecs.umich.edu} 7425894Sgblack@eecs.umich.edu 7435894Sgblack@eecs.umich.edu 7445894Sgblack@eecs.umich.eduvoid 7455894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 7465894Sgblack@eecs.umich.edu{ 7475894Sgblack@eecs.umich.edu if (fault == NoFault) { 7485894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 7495894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 7505894Sgblack@eecs.umich.edu 7515894Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 7525894Sgblack@eecs.umich.edu // Need to wait for retry 7535894Sgblack@eecs.umich.edu _status = IcacheRetry; 7545894Sgblack@eecs.umich.edu } else { 7555894Sgblack@eecs.umich.edu // Need to wait for cache to respond 7565894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7575894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 7585894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 7595894Sgblack@eecs.umich.edu } 7605894Sgblack@eecs.umich.edu } else { 7615894Sgblack@eecs.umich.edu delete req; 7625894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 7637945SAli.Saidi@ARM.com _status = Running; 7645894Sgblack@eecs.umich.edu advanceInst(fault); 7652623SN/A } 7663222Sktlim@umich.edu 7677823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 7687823Ssteve.reinhardt@amd.com previousTick = curTick(); 7692623SN/A} 7702623SN/A 7712623SN/A 7722623SN/Avoid 7732644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 7742623SN/A{ 7758276SAli.Saidi@ARM.com 7768276SAli.Saidi@ARM.com if (_status == Faulting) 7778276SAli.Saidi@ARM.com return; 7788276SAli.Saidi@ARM.com 7798276SAli.Saidi@ARM.com if (fault != NoFault) { 7808276SAli.Saidi@ARM.com advancePC(fault); 7818276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 7828276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 7838276SAli.Saidi@ARM.com _status = Faulting; 7848276SAli.Saidi@ARM.com return; 7858276SAli.Saidi@ARM.com } 7868276SAli.Saidi@ARM.com 7878276SAli.Saidi@ARM.com 7888276SAli.Saidi@ARM.com if (!stayAtPC) 7895726Sgblack@eecs.umich.edu advancePC(fault); 7902623SN/A 7912631SN/A if (_status == Running) { 7922631SN/A // kick off fetch of next instruction... callback from icache 7932631SN/A // response will cause that instruction to be executed, 7942631SN/A // keeping the CPU running. 7952631SN/A fetch(); 7962631SN/A } 7972623SN/A} 7982623SN/A 7992623SN/A 8002623SN/Avoid 8013349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 8022623SN/A{ 8032623SN/A // received a response from the icache: execute the received 8042623SN/A // instruction 8055669Sgblack@eecs.umich.edu 8065669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 8072623SN/A assert(_status == IcacheWaitResponse); 8082798Sktlim@umich.edu 8092623SN/A _status = Running; 8102644Sstever@eecs.umich.edu 8117823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 8127823Ssteve.reinhardt@amd.com previousTick = curTick(); 8133222Sktlim@umich.edu 8142839Sktlim@umich.edu if (getState() == SimObject::Draining) { 8155669Sgblack@eecs.umich.edu if (pkt) { 8165669Sgblack@eecs.umich.edu delete pkt->req; 8175669Sgblack@eecs.umich.edu delete pkt; 8185669Sgblack@eecs.umich.edu } 8193658Sktlim@umich.edu 8202839Sktlim@umich.edu completeDrain(); 8212798Sktlim@umich.edu return; 8222798Sktlim@umich.edu } 8232798Sktlim@umich.edu 8242623SN/A preExecute(); 8257725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 8262623SN/A // load or store: just send to dcache 8272623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 8287945SAli.Saidi@ARM.com 8297945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 8307945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 8317945SAli.Saidi@ARM.com // ifetch 8327945SAli.Saidi@ARM.com if (_status == Running) { 8335894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 8345001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8355001Sgblack@eecs.umich.edu delete traceData; 8365001Sgblack@eecs.umich.edu traceData = NULL; 8373170Sstever@eecs.umich.edu } 8384998Sgblack@eecs.umich.edu 8392644Sstever@eecs.umich.edu postExecute(); 8405103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8415103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8425103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8435103Ssaidi@eecs.umich.edu instCnt++; 8442644Sstever@eecs.umich.edu advanceInst(fault); 8452644Sstever@eecs.umich.edu } 8465726Sgblack@eecs.umich.edu } else if (curStaticInst) { 8472623SN/A // non-memory instruction: execute completely now 8482623SN/A Fault fault = curStaticInst->execute(this, traceData); 8494998Sgblack@eecs.umich.edu 8504998Sgblack@eecs.umich.edu // keep an instruction count 8514998Sgblack@eecs.umich.edu if (fault == NoFault) 8524998Sgblack@eecs.umich.edu countInst(); 8537655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 8545001Sgblack@eecs.umich.edu delete traceData; 8555001Sgblack@eecs.umich.edu traceData = NULL; 8565001Sgblack@eecs.umich.edu } 8574998Sgblack@eecs.umich.edu 8582644Sstever@eecs.umich.edu postExecute(); 8595103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8605103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8615103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8625103Ssaidi@eecs.umich.edu instCnt++; 8632644Sstever@eecs.umich.edu advanceInst(fault); 8645726Sgblack@eecs.umich.edu } else { 8655726Sgblack@eecs.umich.edu advanceInst(NoFault); 8662623SN/A } 8673658Sktlim@umich.edu 8685669Sgblack@eecs.umich.edu if (pkt) { 8695669Sgblack@eecs.umich.edu delete pkt->req; 8705669Sgblack@eecs.umich.edu delete pkt; 8715669Sgblack@eecs.umich.edu } 8722623SN/A} 8732623SN/A 8742948Ssaidi@eecs.umich.eduvoid 8752948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 8762948Ssaidi@eecs.umich.edu{ 8772948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 8782948Ssaidi@eecs.umich.edu} 8792623SN/A 8802623SN/Abool 8813349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 8822623SN/A{ 8834986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8843310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8857823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 8862948Ssaidi@eecs.umich.edu 8877823Ssteve.reinhardt@amd.com if (next_tick == curTick()) 8883310Srdreslin@umich.edu cpu->completeIfetch(pkt); 8893310Srdreslin@umich.edu else 8903495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 8912948Ssaidi@eecs.umich.edu 8923310Srdreslin@umich.edu return true; 8938276SAli.Saidi@ARM.com } else if (pkt->wasNacked()) { 8944433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 8954433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8964433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 8974433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 8984433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 8994433Ssaidi@eecs.umich.edu } 9003310Srdreslin@umich.edu } 9014433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 9024433Ssaidi@eecs.umich.edu return true; 9032623SN/A} 9042623SN/A 9052657Ssaidi@eecs.umich.eduvoid 9062623SN/ATimingSimpleCPU::IcachePort::recvRetry() 9072623SN/A{ 9082623SN/A // we shouldn't get a retry unless we have a packet that we're 9092623SN/A // waiting to transmit 9102623SN/A assert(cpu->ifetch_pkt != NULL); 9112623SN/A assert(cpu->_status == IcacheRetry); 9123349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 9132657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 9142657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 9152657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 9162657Ssaidi@eecs.umich.edu } 9172623SN/A} 9182623SN/A 9192623SN/Avoid 9203349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 9212623SN/A{ 9222623SN/A // received a response from the dcache: complete the load or store 9232623SN/A // instruction 9244870Sstever@eecs.umich.edu assert(!pkt->isError()); 9257516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 9267516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 9272623SN/A 9287823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 9297823Ssteve.reinhardt@amd.com previousTick = curTick(); 9303184Srdreslin@umich.edu 9315728Sgblack@eecs.umich.edu if (pkt->senderState) { 9325728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9335728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 9345728Sgblack@eecs.umich.edu assert(send_state); 9355728Sgblack@eecs.umich.edu delete pkt->req; 9365728Sgblack@eecs.umich.edu delete pkt; 9375728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9385728Sgblack@eecs.umich.edu delete send_state; 9395728Sgblack@eecs.umich.edu 9405728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9415728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9425728Sgblack@eecs.umich.edu assert(main_send_state); 9435728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 9445728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 9455728Sgblack@eecs.umich.edu main_send_state->outstanding--; 9465728Sgblack@eecs.umich.edu 9475728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 9485728Sgblack@eecs.umich.edu return; 9495728Sgblack@eecs.umich.edu } else { 9505728Sgblack@eecs.umich.edu delete main_send_state; 9515728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 9525728Sgblack@eecs.umich.edu pkt = big_pkt; 9535728Sgblack@eecs.umich.edu } 9545728Sgblack@eecs.umich.edu } 9555728Sgblack@eecs.umich.edu 9565728Sgblack@eecs.umich.edu _status = Running; 9575728Sgblack@eecs.umich.edu 9582623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 9592623SN/A 9604998Sgblack@eecs.umich.edu // keep an instruction count 9614998Sgblack@eecs.umich.edu if (fault == NoFault) 9624998Sgblack@eecs.umich.edu countInst(); 9635001Sgblack@eecs.umich.edu else if (traceData) { 9645001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 9655001Sgblack@eecs.umich.edu delete traceData; 9665001Sgblack@eecs.umich.edu traceData = NULL; 9675001Sgblack@eecs.umich.edu } 9684998Sgblack@eecs.umich.edu 9695507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 9705507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 9716102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 9723170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 9733170Sstever@eecs.umich.edu } 9743170Sstever@eecs.umich.edu 9752644Sstever@eecs.umich.edu delete pkt->req; 9762644Sstever@eecs.umich.edu delete pkt; 9772644Sstever@eecs.umich.edu 9783184Srdreslin@umich.edu postExecute(); 9793227Sktlim@umich.edu 9803201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 9813201Shsul@eecs.umich.edu advancePC(fault); 9823201Shsul@eecs.umich.edu completeDrain(); 9833201Shsul@eecs.umich.edu 9843201Shsul@eecs.umich.edu return; 9853201Shsul@eecs.umich.edu } 9863201Shsul@eecs.umich.edu 9872644Sstever@eecs.umich.edu advanceInst(fault); 9882623SN/A} 9892623SN/A 9902623SN/A 9912798Sktlim@umich.eduvoid 9922839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 9932798Sktlim@umich.edu{ 9942839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 9952901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 9962839Sktlim@umich.edu drainEvent->process(); 9972798Sktlim@umich.edu} 9982623SN/A 9994192Sktlim@umich.eduvoid 10004192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 10014192Sktlim@umich.edu{ 10024192Sktlim@umich.edu Port::setPeer(port); 10034192Sktlim@umich.edu 10044192Sktlim@umich.edu#if FULL_SYSTEM 10054192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 10064192Sktlim@umich.edu // Ports) 10075497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 10084192Sktlim@umich.edu#endif 10094192Sktlim@umich.edu} 10104192Sktlim@umich.edu 10112623SN/Abool 10123349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 10132623SN/A{ 10144986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 10153310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 10167823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 10172948Ssaidi@eecs.umich.edu 10187823Ssteve.reinhardt@amd.com if (next_tick == curTick()) { 10193310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 10205728Sgblack@eecs.umich.edu } else { 10217745SAli.Saidi@ARM.com if (!tickEvent.scheduled()) { 10227745SAli.Saidi@ARM.com tickEvent.schedule(pkt, next_tick); 10237745SAli.Saidi@ARM.com } else { 10247745SAli.Saidi@ARM.com // In the case of a split transaction and a cache that is 10257745SAli.Saidi@ARM.com // faster than a CPU we could get two responses before 10267745SAli.Saidi@ARM.com // next_tick expires 10277745SAli.Saidi@ARM.com if (!retryEvent.scheduled()) 10287745SAli.Saidi@ARM.com schedule(retryEvent, next_tick); 10297745SAli.Saidi@ARM.com return false; 10307745SAli.Saidi@ARM.com } 10315728Sgblack@eecs.umich.edu } 10322948Ssaidi@eecs.umich.edu 10333310Srdreslin@umich.edu return true; 10343310Srdreslin@umich.edu } 10354870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 10364433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 10374433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 10384433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 10394433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 10404433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 10414433Ssaidi@eecs.umich.edu } 10423310Srdreslin@umich.edu } 10434433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 10444433Ssaidi@eecs.umich.edu return true; 10452948Ssaidi@eecs.umich.edu} 10462948Ssaidi@eecs.umich.edu 10472948Ssaidi@eecs.umich.eduvoid 10482948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 10492948Ssaidi@eecs.umich.edu{ 10502630SN/A cpu->completeDataAccess(pkt); 10512623SN/A} 10522623SN/A 10532657Ssaidi@eecs.umich.eduvoid 10542623SN/ATimingSimpleCPU::DcachePort::recvRetry() 10552623SN/A{ 10562623SN/A // we shouldn't get a retry unless we have a packet that we're 10572623SN/A // waiting to transmit 10582623SN/A assert(cpu->dcache_pkt != NULL); 10592623SN/A assert(cpu->_status == DcacheRetry); 10603349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 10615728Sgblack@eecs.umich.edu if (tmp->senderState) { 10625728Sgblack@eecs.umich.edu // This is a packet from a split access. 10635728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 10645728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 10655728Sgblack@eecs.umich.edu assert(send_state); 10665728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 10675728Sgblack@eecs.umich.edu 10685728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 10695728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 10705728Sgblack@eecs.umich.edu assert(main_send_state); 10715728Sgblack@eecs.umich.edu 10725728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 10735728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 10745728Sgblack@eecs.umich.edu // and try sending the other fragment. 10755728Sgblack@eecs.umich.edu send_state->clearFromParent(); 10765728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 10775728Sgblack@eecs.umich.edu if (other_index > 0) { 10785728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 10795728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 10805728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 10815728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 10825728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 10835728Sgblack@eecs.umich.edu } 10845728Sgblack@eecs.umich.edu } else { 10855728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10865728Sgblack@eecs.umich.edu // memory system takes ownership of packet 10875728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 10885728Sgblack@eecs.umich.edu } 10895728Sgblack@eecs.umich.edu } 10905728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 10912657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10923170Sstever@eecs.umich.edu // memory system takes ownership of packet 10932657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 10942657Ssaidi@eecs.umich.edu } 10952623SN/A} 10962623SN/A 10975606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 10985606Snate@binkert.org Tick t) 10995606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 11005103Ssaidi@eecs.umich.edu{ 11015606Snate@binkert.org cpu->schedule(this, t); 11025103Ssaidi@eecs.umich.edu} 11035103Ssaidi@eecs.umich.edu 11045103Ssaidi@eecs.umich.eduvoid 11055103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 11065103Ssaidi@eecs.umich.edu{ 11075103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 11085103Ssaidi@eecs.umich.edu} 11095103Ssaidi@eecs.umich.edu 11105103Ssaidi@eecs.umich.educonst char * 11115336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 11125103Ssaidi@eecs.umich.edu{ 11135103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 11145103Ssaidi@eecs.umich.edu} 11155103Ssaidi@eecs.umich.edu 11162623SN/A 11175315Sstever@gmail.comvoid 11185315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 11195315Sstever@gmail.com{ 11205315Sstever@gmail.com dcachePort.printAddr(a); 11215315Sstever@gmail.com} 11225315Sstever@gmail.com 11235315Sstever@gmail.com 11242623SN/A//////////////////////////////////////////////////////////////////////// 11252623SN/A// 11262623SN/A// TimingSimpleCPU Simulation Object 11272623SN/A// 11284762Snate@binkert.orgTimingSimpleCPU * 11294762Snate@binkert.orgTimingSimpleCPUParams::create() 11302623SN/A{ 11315529Snate@binkert.org numThreads = 1; 11325529Snate@binkert.org#if !FULL_SYSTEM 11334762Snate@binkert.org if (workload.size() != 1) 11344762Snate@binkert.org panic("only one workload allowed"); 11352623SN/A#endif 11365529Snate@binkert.org return new TimingSimpleCPU(this); 11372623SN/A} 1138