timing.cc revision 8105
12623SN/A/* 22623SN/A * Copyright (c) 2010 ARM Limited 32623SN/A * All rights reserved 42623SN/A * 52623SN/A * The license below extends only to copyright in the software and shall 62623SN/A * not be construed as granting a license to any other intellectual 72623SN/A * property including but not limited to intellectual property relating 82623SN/A * to a hardware implementation of the functionality of the software 92623SN/A * licensed hereunder. You may use the software subject to the license 102623SN/A * terms below provided that you ensure that this notice is replicated 112623SN/A * unmodified and in its entirety in all distributions of the software, 122623SN/A * modified or unmodified, in source code or in binary form. 132623SN/A * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313170Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325103Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344040Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356658Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383348Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393348Sbinkertn@umich.edu * 404762Snate@binkert.org * Authors: Steve Reinhardt 417678Sgblack@eecs.umich.edu */ 422901Ssaidi@eecs.umich.edu 432623SN/A#include "arch/locked_mem.hh" 442623SN/A#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 462623SN/A#include "base/bigint.hh" 472856Srdreslin@umich.edu#include "config/the_isa.hh" 482856Srdreslin@umich.edu#include "cpu/exetrace.hh" 492856Srdreslin@umich.edu#include "cpu/simple/timing.hh" 502856Srdreslin@umich.edu#include "mem/packet.hh" 512856Srdreslin@umich.edu#include "mem/packet_access.hh" 522856Srdreslin@umich.edu#include "params/TimingSimpleCPU.hh" 532856Srdreslin@umich.edu#include "sim/faults.hh" 542856Srdreslin@umich.edu#include "sim/system.hh" 552856Srdreslin@umich.edu 562856Srdreslin@umich.eduusing namespace std; 572623SN/Ausing namespace TheISA; 582623SN/A 592623SN/APort * 602623SN/ATimingSimpleCPU::getPort(const std::string &if_name, int idx) 612623SN/A{ 622623SN/A if (if_name == "dcache_port") 632680Sktlim@umich.edu return &dcachePort; 642680Sktlim@umich.edu else if (if_name == "icache_port") 652623SN/A return &icachePort; 662623SN/A else 675712Shsul@eecs.umich.edu panic("No Such Port\n"); 682623SN/A} 692623SN/A 702623SN/Avoid 712623SN/ATimingSimpleCPU::init() 722623SN/A{ 733349Sbinkertn@umich.edu BaseCPU::init(); 742623SN/A#if FULL_SYSTEM 752623SN/A for (int i = 0; i < threadContexts.size(); ++i) { 762623SN/A ThreadContext *tc = threadContexts[i]; 772623SN/A 782623SN/A // initialize CPU, including PC 792623SN/A TheISA::initCPU(tc, _cpuId); 803349Sbinkertn@umich.edu } 812623SN/A#endif 823184Srdreslin@umich.edu} 833184Srdreslin@umich.edu 842623SN/ATick 852623SN/ATimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 862623SN/A{ 872623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 882623SN/A return curTick(); 893647Srdreslin@umich.edu} 903647Srdreslin@umich.edu 913647Srdreslin@umich.eduvoid 923647Srdreslin@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 933647Srdreslin@umich.edu{ 942631SN/A //No internal storage to update, jusst return 953647Srdreslin@umich.edu return; 962631SN/A} 972623SN/A 982623SN/Avoid 992623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 1002948Ssaidi@eecs.umich.edu{ 1012948Ssaidi@eecs.umich.edu if (status == RangeChange) { 1023349Sbinkertn@umich.edu if (!snoopRangeSent) { 1032948Ssaidi@eecs.umich.edu snoopRangeSent = true; 1042948Ssaidi@eecs.umich.edu sendStatusChange(Port::RangeChange); 1055606Snate@binkert.org } 1062948Ssaidi@eecs.umich.edu return; 1072948Ssaidi@eecs.umich.edu } 1085529Snate@binkert.org 1095894Sgblack@eecs.umich.edu panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 1105894Sgblack@eecs.umich.edu} 1112623SN/A 1122623SN/A 1133647Srdreslin@umich.eduvoid 1143647Srdreslin@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1153647Srdreslin@umich.edu{ 1163647Srdreslin@umich.edu pkt = _pkt; 1172623SN/A cpu->schedule(this, t); 1182839Sktlim@umich.edu} 1193222Sktlim@umich.edu 1202901Ssaidi@eecs.umich.eduTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1212623SN/A : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 1222623SN/A dcachePort(this, p->clock), fetchEvent(this) 1232623SN/A{ 1242623SN/A _status = Idle; 1252623SN/A 1262623SN/A icachePort.snoopRangeSent = false; 1272623SN/A dcachePort.snoopRangeSent = false; 1282623SN/A 1292623SN/A ifetch_pkt = dcache_pkt = NULL; 1302623SN/A drainEvent = NULL; 1312915Sktlim@umich.edu previousTick = 0; 1322915Sktlim@umich.edu changeState(SimObject::Running); 1332623SN/A system->totalNumInsts = 0; 1342623SN/A} 1352623SN/A 1362623SN/A 1372623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1382623SN/A{ 1392915Sktlim@umich.edu} 1402915Sktlim@umich.edu 1412623SN/Avoid 1422798Sktlim@umich.eduTimingSimpleCPU::serialize(ostream &os) 1432798Sktlim@umich.edu{ 1442901Ssaidi@eecs.umich.edu SimObject::State so_state = SimObject::getState(); 1452839Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1462798Sktlim@umich.edu BaseSimpleCPU::serialize(os); 1472839Sktlim@umich.edu} 1482798Sktlim@umich.edu 1495496Ssaidi@eecs.umich.eduvoid 1502901Ssaidi@eecs.umich.eduTimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1512901Ssaidi@eecs.umich.edu{ 1522798Sktlim@umich.edu SimObject::State so_state; 1532839Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1542839Sktlim@umich.edu BaseSimpleCPU::unserialize(cp, section); 1552901Ssaidi@eecs.umich.edu} 1562798Sktlim@umich.edu 1572623SN/Aunsigned int 1582623SN/ATimingSimpleCPU::drain(Event *drain_event) 1592623SN/A{ 1602798Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1612623SN/A // an access to complete. 1625221Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1632798Sktlim@umich.edu changeState(SimObject::Drained); 1644762Snate@binkert.org return 0; 1653201Shsul@eecs.umich.edu } else { 1665710Scws3k@cs.virginia.edu changeState(SimObject::Draining); 1675710Scws3k@cs.virginia.edu drainEvent = drain_event; 1682915Sktlim@umich.edu return 1; 1695710Scws3k@cs.virginia.edu } 1702623SN/A} 1712798Sktlim@umich.edu 1722901Ssaidi@eecs.umich.eduvoid 1732798Sktlim@umich.eduTimingSimpleCPU::resume() 1742798Sktlim@umich.edu{ 1752798Sktlim@umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1762798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1772798Sktlim@umich.edu assert(system->getMemoryMode() == Enums::timing); 1785496Ssaidi@eecs.umich.edu 1792798Sktlim@umich.edu if (fetchEvent.scheduled()) 1805099Ssaidi@eecs.umich.edu deschedule(fetchEvent); 1812867Sktlim@umich.edu 1822867Sktlim@umich.edu schedule(fetchEvent, nextCycle()); 1832867Sktlim@umich.edu } 1845710Scws3k@cs.virginia.edu 1855606Snate@binkert.org changeState(SimObject::Running); 1862623SN/A} 1872623SN/A 1882623SN/Avoid 1892623SN/ATimingSimpleCPU::switchOut() 1902623SN/A{ 1912623SN/A assert(_status == Running || _status == Idle); 1924192Sktlim@umich.edu _status = SwitchedOut; 1932623SN/A numCycles += tickToCycles(curTick() - previousTick); 1942680Sktlim@umich.edu 1952623SN/A // If we've been scheduled to resume but are then told to switch out, 1962680Sktlim@umich.edu // we'll need to cancel it. 1972680Sktlim@umich.edu if (fetchEvent.scheduled()) 1982680Sktlim@umich.edu deschedule(fetchEvent); 1992623SN/A} 2002623SN/A 2012623SN/A 2022623SN/Avoid 2033201Shsul@eecs.umich.eduTimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2043201Shsul@eecs.umich.edu{ 2053201Shsul@eecs.umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2063201Shsul@eecs.umich.edu 2075169Ssaidi@eecs.umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2085101Ssaidi@eecs.umich.edu // running and schedule its tick event. 2092623SN/A for (int i = 0; i < threadContexts.size(); ++i) { 2102623SN/A ThreadContext *tc = threadContexts[i]; 2112623SN/A if (tc->status() == ThreadContext::Active && _status != Running) { 2122623SN/A _status = Running; 2132623SN/A break; 2142623SN/A } 2155221Ssaidi@eecs.umich.edu } 2165221Ssaidi@eecs.umich.edu 2172623SN/A if (_status != Running) { 2182683Sktlim@umich.edu _status = Idle; 2192623SN/A } 2202623SN/A assert(threadContexts.size() == 1); 2212623SN/A previousTick = curTick(); 2222623SN/A} 2232623SN/A 2243686Sktlim@umich.edu 2252623SN/Avoid 2265606Snate@binkert.orgTimingSimpleCPU::activateContext(int thread_num, int delay) 2272623SN/A{ 2282623SN/A DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2292623SN/A 2302623SN/A assert(thread_num == 0); 2312623SN/A assert(thread); 2322623SN/A 2335221Ssaidi@eecs.umich.edu assert(_status == Idle); 2345221Ssaidi@eecs.umich.edu 2352623SN/A notIdleFraction++; 2362683Sktlim@umich.edu _status = Running; 2372623SN/A 2386043Sgblack@eecs.umich.edu // kick things off by initiating the fetch of the next instruction 2396043Sgblack@eecs.umich.edu schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 2406043Sgblack@eecs.umich.edu} 2412644Sstever@eecs.umich.edu 2422623SN/A 2432644Sstever@eecs.umich.eduvoid 2442644Sstever@eecs.umich.eduTimingSimpleCPU::suspendContext(int thread_num) 2452623SN/A{ 2462623SN/A DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2472623SN/A 2482623SN/A assert(thread_num == 0); 2492623SN/A assert(thread); 2505728Sgblack@eecs.umich.edu 2515728Sgblack@eecs.umich.edu if (_status == Idle) 2525728Sgblack@eecs.umich.edu return; 2535728Sgblack@eecs.umich.edu 2545728Sgblack@eecs.umich.edu assert(_status == Running); 2555728Sgblack@eecs.umich.edu 2565728Sgblack@eecs.umich.edu // just change status to Idle... if status != Running, 2575728Sgblack@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2585728Sgblack@eecs.umich.edu 2595728Sgblack@eecs.umich.edu notIdleFraction--; 2605728Sgblack@eecs.umich.edu _status = Idle; 2615728Sgblack@eecs.umich.edu} 2625728Sgblack@eecs.umich.edu 2635728Sgblack@eecs.umich.edubool 2645728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2655728Sgblack@eecs.umich.edu{ 2665728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2675728Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2685728Sgblack@eecs.umich.edu Tick delay; 2695728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2702623SN/A new IprEvent(pkt, this, nextCycle(curTick() + delay)); 2715894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2726973Stjones1@inf.ed.ac.uk dcache_pkt = NULL; 2736973Stjones1@inf.ed.ac.uk } else if (!dcachePort.sendTiming(pkt)) { 2745744Sgblack@eecs.umich.edu _status = DcacheRetry; 2755894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2765894Sgblack@eecs.umich.edu } else { 2777691SAli.Saidi@ARM.com _status = DcacheWaitResponse; 2785894Sgblack@eecs.umich.edu // memory system takes ownership of packet 2795894Sgblack@eecs.umich.edu dcache_pkt = NULL; 2805894Sgblack@eecs.umich.edu } 2815894Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2825894Sgblack@eecs.umich.edu} 2835894Sgblack@eecs.umich.edu 2845894Sgblack@eecs.umich.eduvoid 2855894Sgblack@eecs.umich.eduTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2865894Sgblack@eecs.umich.edu bool read) 2876102Sgblack@eecs.umich.edu{ 2885894Sgblack@eecs.umich.edu PacketPtr pkt; 2895894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2905894Sgblack@eecs.umich.edu pkt->dataDynamicArray<uint8_t>(data); 2915894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2925894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2935894Sgblack@eecs.umich.edu pkt->makeResponse(); 2945894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2955894Sgblack@eecs.umich.edu } else if (read) { 2965894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2975894Sgblack@eecs.umich.edu } else { 2985894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2995894Sgblack@eecs.umich.edu 3005894Sgblack@eecs.umich.edu if (req->isLLSC()) { 3015894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3025894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3035894Sgblack@eecs.umich.edu assert(res); 3045894Sgblack@eecs.umich.edu req->setExtraData(*res); 3056973Stjones1@inf.ed.ac.uk } 3066973Stjones1@inf.ed.ac.uk 3075894Sgblack@eecs.umich.edu if (do_access) { 3085894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3095894Sgblack@eecs.umich.edu handleWritePacket(); 3105894Sgblack@eecs.umich.edu } else { 3115894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3125894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3135894Sgblack@eecs.umich.edu } 3145894Sgblack@eecs.umich.edu } 3155894Sgblack@eecs.umich.edu} 3165894Sgblack@eecs.umich.edu 3175894Sgblack@eecs.umich.eduvoid 3185894Sgblack@eecs.umich.eduTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3195894Sgblack@eecs.umich.edu RequestPtr req, uint8_t *data, bool read) 3205894Sgblack@eecs.umich.edu{ 3215894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3225894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3235894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3245894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3255894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3265894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3275894Sgblack@eecs.umich.edu } else if (read) { 3285894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3295894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3305894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3315894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3325894Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3335894Sgblack@eecs.umich.edu pkt2->senderState); 3345894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3355894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3365894Sgblack@eecs.umich.edu } 3375894Sgblack@eecs.umich.edu } 3385894Sgblack@eecs.umich.edu } else { 3395894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3405894Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3415894Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3425894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3435894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3446739Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3456739Sgblack@eecs.umich.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3465894Sgblack@eecs.umich.edu pkt2->senderState); 3475894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3485894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3495894Sgblack@eecs.umich.edu } 3505894Sgblack@eecs.umich.edu } 3515894Sgblack@eecs.umich.edu } 3525894Sgblack@eecs.umich.edu} 3535744Sgblack@eecs.umich.edu 3545744Sgblack@eecs.umich.eduvoid 3555894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3565894Sgblack@eecs.umich.edu{ 3575894Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3585894Sgblack@eecs.umich.edu // for instance prefetches. 3595894Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick() - previousTick); 3605894Sgblack@eecs.umich.edu previousTick = curTick(); 3615894Sgblack@eecs.umich.edu 3625894Sgblack@eecs.umich.edu if (traceData) { 3635894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3645894Sgblack@eecs.umich.edu delete traceData; 3655894Sgblack@eecs.umich.edu traceData = NULL; 3665894Sgblack@eecs.umich.edu } 3675894Sgblack@eecs.umich.edu 3685894Sgblack@eecs.umich.edu postExecute(); 3695894Sgblack@eecs.umich.edu 3705894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3716102Sgblack@eecs.umich.edu advancePC(fault); 3725894Sgblack@eecs.umich.edu completeDrain(); 3735894Sgblack@eecs.umich.edu } else { 3745894Sgblack@eecs.umich.edu advanceInst(fault); 3756102Sgblack@eecs.umich.edu } 3765894Sgblack@eecs.umich.edu} 3775894Sgblack@eecs.umich.edu 3785894Sgblack@eecs.umich.eduvoid 3795894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3805894Sgblack@eecs.umich.edu{ 3815894Sgblack@eecs.umich.edu MemCmd cmd; 3825894Sgblack@eecs.umich.edu if (read) { 3835894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3845894Sgblack@eecs.umich.edu if (req->isLLSC()) 3855894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3865894Sgblack@eecs.umich.edu } else { 3875894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3885894Sgblack@eecs.umich.edu if (req->isLLSC()) { 3895894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3905894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3915744Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3925744Sgblack@eecs.umich.edu } 3935894Sgblack@eecs.umich.edu } 3945894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 3955894Sgblack@eecs.umich.edu} 3965894Sgblack@eecs.umich.edu 3975894Sgblack@eecs.umich.eduvoid 3985894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3995894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 4005894Sgblack@eecs.umich.edu uint8_t *data, bool read) 4015744Sgblack@eecs.umich.edu{ 4025744Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 4035744Sgblack@eecs.umich.edu 4045744Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 4057691SAli.Saidi@ARM.com 4065744Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 4075744Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 4085744Sgblack@eecs.umich.edu return; 4095744Sgblack@eecs.umich.edu } 4105744Sgblack@eecs.umich.edu 4115744Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 4125744Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 4135744Sgblack@eecs.umich.edu 4145744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 4155744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 4165744Sgblack@eecs.umich.edu Packet::Broadcast); 4175744Sgblack@eecs.umich.edu 4182623SN/A pkt->dataDynamicArray<uint8_t>(data); 4197520Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4207520Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4212623SN/A 4225728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4235728Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4246221Snate@binkert.org main_send_state->fragments[0] = pkt1; 4255728Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4266227Snate@binkert.org main_send_state->outstanding = 2; 4276973Stjones1@inf.ed.ac.uk pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4282623SN/A pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4297045Ssteve.reinhardt@amd.com} 4307045Ssteve.reinhardt@amd.com 4317045Ssteve.reinhardt@amd.comFault 4327045Ssteve.reinhardt@amd.comTimingSimpleCPU::readBytes(Addr addr, uint8_t *data, 4337520Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4346221Snate@binkert.org{ 4355728Sgblack@eecs.umich.edu Fault fault; 4367520Sgblack@eecs.umich.edu const int asid = 0; 4375744Sgblack@eecs.umich.edu const ThreadID tid = 0; 4385728Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4395894Sgblack@eecs.umich.edu unsigned block_size = dcachePort.peerBlockSize(); 4405744Sgblack@eecs.umich.edu BaseTLB::Mode mode = BaseTLB::Read; 4415894Sgblack@eecs.umich.edu 4426102Sgblack@eecs.umich.edu if (traceData) { 4435894Sgblack@eecs.umich.edu traceData->setAddr(addr); 4445894Sgblack@eecs.umich.edu } 4456973Stjones1@inf.ed.ac.uk 4467520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4476973Stjones1@inf.ed.ac.uk flags, pc, _cpuId, tid); 4486973Stjones1@inf.ed.ac.uk 4496973Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + size - 1, block_size); 4506973Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 4516973Stjones1@inf.ed.ac.uk 4526973Stjones1@inf.ed.ac.uk _status = DTBWaitResponse; 4536973Stjones1@inf.ed.ac.uk if (split_addr > addr) { 4546973Stjones1@inf.ed.ac.uk RequestPtr req1, req2; 4555744Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4566973Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, req1, req2); 4577520Sgblack@eecs.umich.edu 4586973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4596973Stjones1@inf.ed.ac.uk new WholeTranslationState(req, req1, req2, new uint8_t[size], 4606973Stjones1@inf.ed.ac.uk NULL, mode); 4612623SN/A DataTranslation<TimingSimpleCPU> *trans1 = 4622623SN/A new DataTranslation<TimingSimpleCPU>(this, state, 0); 4635728Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU> *trans2 = 4642623SN/A new DataTranslation<TimingSimpleCPU>(this, state, 1); 4652623SN/A 4667520Sgblack@eecs.umich.edu thread->dtb->translateTiming(req1, tc, trans1, mode); 4677520Sgblack@eecs.umich.edu thread->dtb->translateTiming(req2, tc, trans2, mode); 4687520Sgblack@eecs.umich.edu } else { 4697520Sgblack@eecs.umich.edu WholeTranslationState *state = 4707520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4717520Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU> *translation 4727520Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU>(this, state); 4732623SN/A thread->dtb->translateTiming(req, tc, translation, mode); 4742623SN/A } 4752623SN/A 4762623SN/A return NoFault; 4774040Ssaidi@eecs.umich.edu} 4784040Ssaidi@eecs.umich.edu 4794040Ssaidi@eecs.umich.edutemplate <class T> 4804040Ssaidi@eecs.umich.eduFault 4814115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 4824115Ssaidi@eecs.umich.edu{ 4834115Ssaidi@eecs.umich.edu return readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 4844115Ssaidi@eecs.umich.edu} 4852623SN/A 4862623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4872623SN/A 4882623SN/Atemplate 4892623SN/AFault 4902623SN/ATimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 4912623SN/A 4922623SN/Atemplate 4932623SN/AFault 4942623SN/ATimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 4952623SN/A 4962623SN/Atemplate 4972623SN/AFault 4982623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 4992623SN/A 5002623SN/Atemplate 5012623SN/AFault 5022623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 5032623SN/A 5042623SN/Atemplate 5052623SN/AFault 5062623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 5072623SN/A 5082623SN/Atemplate 5092623SN/AFault 5102623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 5112623SN/A 5122623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5132623SN/A 5142623SN/Atemplate<> 5152623SN/AFault 5162623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 5172623SN/A{ 5182623SN/A return read(addr, *(uint64_t*)&data, flags); 5192623SN/A} 5202623SN/A 5212623SN/Atemplate<> 5225728Sgblack@eecs.umich.eduFault 5235728Sgblack@eecs.umich.eduTimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 5245728Sgblack@eecs.umich.edu{ 5255728Sgblack@eecs.umich.edu return read(addr, *(uint32_t*)&data, flags); 5265728Sgblack@eecs.umich.edu} 5275728Sgblack@eecs.umich.edu 5285728Sgblack@eecs.umich.edutemplate<> 5295728Sgblack@eecs.umich.eduFault 5305728Sgblack@eecs.umich.eduTimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 5315728Sgblack@eecs.umich.edu{ 5325728Sgblack@eecs.umich.edu return read(addr, (uint32_t&)data, flags); 5335728Sgblack@eecs.umich.edu} 5345728Sgblack@eecs.umich.edu 5355728Sgblack@eecs.umich.edubool 5365728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 5375728Sgblack@eecs.umich.edu{ 5385728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 5395728Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 5405728Sgblack@eecs.umich.edu Tick delay; 5412623SN/A delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 5422623SN/A new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 5437520Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5447520Sgblack@eecs.umich.edu dcache_pkt = NULL; 5452623SN/A } else if (!dcachePort.sendTiming(dcache_pkt)) { 5465728Sgblack@eecs.umich.edu _status = DcacheRetry; 5476221Snate@binkert.org } else { 5485728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5496227Snate@binkert.org // memory system takes ownership of packet 5506973Stjones1@inf.ed.ac.uk dcache_pkt = NULL; 5513169Sstever@eecs.umich.edu } 5527045Ssteve.reinhardt@amd.com return dcache_pkt == NULL; 5537045Ssteve.reinhardt@amd.com} 5547045Ssteve.reinhardt@amd.com 5557045Ssteve.reinhardt@amd.comFault 5567520Sgblack@eecs.umich.eduTimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size, 5576221Snate@binkert.org Addr addr, unsigned flags, uint64_t *res) 5585728Sgblack@eecs.umich.edu{ 5597520Sgblack@eecs.umich.edu const int asid = 0; 5605744Sgblack@eecs.umich.edu const ThreadID tid = 0; 5615728Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5625894Sgblack@eecs.umich.edu unsigned block_size = dcachePort.peerBlockSize(); 5635744Sgblack@eecs.umich.edu BaseTLB::Mode mode = BaseTLB::Write; 5645894Sgblack@eecs.umich.edu 5656102Sgblack@eecs.umich.edu if (traceData) { 5665894Sgblack@eecs.umich.edu traceData->setAddr(addr); 5675894Sgblack@eecs.umich.edu } 5686973Stjones1@inf.ed.ac.uk 5697520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 5706973Stjones1@inf.ed.ac.uk flags, pc, _cpuId, tid); 5716973Stjones1@inf.ed.ac.uk 5726973Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + size - 1, block_size); 5736973Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 5746973Stjones1@inf.ed.ac.uk 5756973Stjones1@inf.ed.ac.uk _status = DTBWaitResponse; 5766973Stjones1@inf.ed.ac.uk if (split_addr > addr) { 5775744Sgblack@eecs.umich.edu RequestPtr req1, req2; 5786973Stjones1@inf.ed.ac.uk assert(!req->isLLSC() && !req->isSwap()); 5797520Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5806973Stjones1@inf.ed.ac.uk 5816973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5826973Stjones1@inf.ed.ac.uk new WholeTranslationState(req, req1, req2, data, res, mode); 5832623SN/A DataTranslation<TimingSimpleCPU> *trans1 = 5842623SN/A new DataTranslation<TimingSimpleCPU>(this, state, 0); 5857045Ssteve.reinhardt@amd.com DataTranslation<TimingSimpleCPU> *trans2 = 5865728Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU>(this, state, 1); 5872623SN/A 5882623SN/A thread->dtb->translateTiming(req1, tc, trans1, mode); 5897520Sgblack@eecs.umich.edu thread->dtb->translateTiming(req2, tc, trans2, mode); 5907520Sgblack@eecs.umich.edu } else { 5917520Sgblack@eecs.umich.edu WholeTranslationState *state = 5927520Sgblack@eecs.umich.edu new WholeTranslationState(req, data, res, mode); 5937520Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU> *translation = 5947520Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU>(this, state); 5957520Sgblack@eecs.umich.edu thread->dtb->translateTiming(req, tc, translation, mode); 5967520Sgblack@eecs.umich.edu } 5977520Sgblack@eecs.umich.edu 5987520Sgblack@eecs.umich.edu // Translation faults will be returned via finishTranslation() 5997520Sgblack@eecs.umich.edu return NoFault; 6007520Sgblack@eecs.umich.edu} 6017520Sgblack@eecs.umich.edu 6027520Sgblack@eecs.umich.eduFault 6037520Sgblack@eecs.umich.eduTimingSimpleCPU::writeBytes(uint8_t *data, unsigned size, 6047520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 6057691SAli.Saidi@ARM.com{ 6067520Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 6077520Sgblack@eecs.umich.edu memcpy(newData, data, size); 6087520Sgblack@eecs.umich.edu return writeTheseBytes(newData, size, addr, flags, res); 6097520Sgblack@eecs.umich.edu} 6107520Sgblack@eecs.umich.edu 6112623SN/Atemplate <class T> 6122623SN/AFault 6132623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 6142623SN/A{ 6154224Sgblack@eecs.umich.edu if (traceData) { 6164224Sgblack@eecs.umich.edu traceData->setData(data); 6174224Sgblack@eecs.umich.edu } 6184224Sgblack@eecs.umich.edu T *dataP = (T*) new uint8_t[sizeof(T)]; 6194224Sgblack@eecs.umich.edu *dataP = TheISA::htog(data); 6204224Sgblack@eecs.umich.edu 6214224Sgblack@eecs.umich.edu return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res); 6224224Sgblack@eecs.umich.edu} 6234224Sgblack@eecs.umich.edu 6244224Sgblack@eecs.umich.edu 6252623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 6262623SN/Atemplate 6272623SN/AFault 6282623SN/ATimingSimpleCPU::write(Twin32_t data, Addr addr, 6292623SN/A unsigned flags, uint64_t *res); 6302623SN/A 6312623SN/Atemplate 6322623SN/AFault 6332623SN/ATimingSimpleCPU::write(Twin64_t data, Addr addr, 6342623SN/A unsigned flags, uint64_t *res); 6352623SN/A 6362623SN/Atemplate 6372623SN/AFault 6382623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 6392623SN/A unsigned flags, uint64_t *res); 6402623SN/A 6412623SN/Atemplate 6422623SN/AFault 6432623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 6442623SN/A unsigned flags, uint64_t *res); 6452623SN/A 6462623SN/Atemplate 6472623SN/AFault 6482623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 6492623SN/A unsigned flags, uint64_t *res); 6502623SN/A 6512623SN/Atemplate 6522623SN/AFault 6532623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 6542623SN/A unsigned flags, uint64_t *res); 6552623SN/A 6562623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 6572623SN/A 6582623SN/Atemplate<> 6592623SN/AFault 6602623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 6612623SN/A{ 6622623SN/A return write(*(uint64_t*)&data, addr, flags, res); 6632623SN/A} 6642623SN/A 6652623SN/Atemplate<> 6662623SN/AFault 6672623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 6682623SN/A{ 6696973Stjones1@inf.ed.ac.uk return write(*(uint32_t*)&data, addr, flags, res); 6706973Stjones1@inf.ed.ac.uk} 6716973Stjones1@inf.ed.ac.uk 6726973Stjones1@inf.ed.ac.uk 6736973Stjones1@inf.ed.ac.uktemplate<> 6746973Stjones1@inf.ed.ac.ukFault 6756973Stjones1@inf.ed.ac.ukTimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6766973Stjones1@inf.ed.ac.uk{ 6777691SAli.Saidi@ARM.com return write((uint32_t)data, addr, flags, res); 6786973Stjones1@inf.ed.ac.uk} 6796973Stjones1@inf.ed.ac.uk 6806973Stjones1@inf.ed.ac.uk 6816973Stjones1@inf.ed.ac.ukvoid 6826973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 6836973Stjones1@inf.ed.ac.uk{ 6846973Stjones1@inf.ed.ac.uk _status = Running; 6856973Stjones1@inf.ed.ac.uk 6866973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 6876973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 6886973Stjones1@inf.ed.ac.uk state->setNoFault(); 6896973Stjones1@inf.ed.ac.uk } 6906973Stjones1@inf.ed.ac.uk delete [] state->data; 6916973Stjones1@inf.ed.ac.uk state->deleteReqs(); 6926973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 6936973Stjones1@inf.ed.ac.uk } else { 6946973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 6952623SN/A sendData(state->mainReq, state->data, state->res, 6962623SN/A state->mode == BaseTLB::Read); 6975221Ssaidi@eecs.umich.edu } else { 6985221Ssaidi@eecs.umich.edu sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 6993387Sgblack@eecs.umich.edu state->data, state->mode == BaseTLB::Read); 7003387Sgblack@eecs.umich.edu } 7012631SN/A } 7025348Ssaidi@eecs.umich.edu 7035348Ssaidi@eecs.umich.edu delete state; 7045669Sgblack@eecs.umich.edu} 7052623SN/A 7065914Sgblack@eecs.umich.edu 7075669Sgblack@eecs.umich.eduvoid 7085712Shsul@eecs.umich.eduTimingSimpleCPU::fetch() 7095894Sgblack@eecs.umich.edu{ 7106023Snate@binkert.org DPRINTF(SimpleCPU, "Fetch\n"); 7116023Snate@binkert.org 7122623SN/A if (!curStaticInst || !curStaticInst->isDelayedCommit()) 7135669Sgblack@eecs.umich.edu checkForInterrupts(); 7145669Sgblack@eecs.umich.edu 7155894Sgblack@eecs.umich.edu checkPcEventQueue(); 7165894Sgblack@eecs.umich.edu 7175894Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 7185894Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 7195894Sgblack@eecs.umich.edu 7205894Sgblack@eecs.umich.edu if (needToFetch) { 7215894Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 7225894Sgblack@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 7235894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 7245894Sgblack@eecs.umich.edu thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 7255894Sgblack@eecs.umich.edu BaseTLB::Execute); 7265894Sgblack@eecs.umich.edu } else { 7275894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7285894Sgblack@eecs.umich.edu completeIfetch(NULL); 7295894Sgblack@eecs.umich.edu 7305894Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick() - previousTick); 7315894Sgblack@eecs.umich.edu previousTick = curTick(); 7325894Sgblack@eecs.umich.edu } 7335894Sgblack@eecs.umich.edu} 7345894Sgblack@eecs.umich.edu 7355894Sgblack@eecs.umich.edu 7365894Sgblack@eecs.umich.eduvoid 7375894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 7385894Sgblack@eecs.umich.edu{ 7395894Sgblack@eecs.umich.edu if (fault == NoFault) { 7405894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 7415894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 7422623SN/A 7433222Sktlim@umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 7445099Ssaidi@eecs.umich.edu // Need to wait for retry 7453222Sktlim@umich.edu _status = IcacheRetry; 7462623SN/A } else { 7472623SN/A // Need to wait for cache to respond 7482623SN/A _status = IcacheWaitResponse; 7492623SN/A // ownership of packet transferred to memory system 7502644Sstever@eecs.umich.edu ifetch_pkt = NULL; 7512623SN/A } 7525726Sgblack@eecs.umich.edu } else { 7535726Sgblack@eecs.umich.edu delete req; 7542623SN/A // fetch fault: advance directly to next instruction (fault handler) 7552631SN/A _status = Running; 7562631SN/A advanceInst(fault); 7572631SN/A } 7582631SN/A 7592631SN/A numCycles += tickToCycles(curTick() - previousTick); 7602631SN/A previousTick = curTick(); 7612623SN/A} 7622623SN/A 7632623SN/A 7642623SN/Avoid 7653349Sbinkertn@umich.eduTimingSimpleCPU::advanceInst(Fault fault) 7662623SN/A{ 7675221Ssaidi@eecs.umich.edu if (fault != NoFault || !stayAtPC) 7685221Ssaidi@eecs.umich.edu advancePC(fault); 7692623SN/A 7702623SN/A if (_status == Running) { 7715669Sgblack@eecs.umich.edu // kick off fetch of next instruction... callback from icache 7725669Sgblack@eecs.umich.edu // response will cause that instruction to be executed, 7732623SN/A // keeping the CPU running. 7742798Sktlim@umich.edu fetch(); 7752623SN/A } 7762644Sstever@eecs.umich.edu} 7775099Ssaidi@eecs.umich.edu 7783222Sktlim@umich.edu 7793222Sktlim@umich.eduvoid 7802839Sktlim@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7815669Sgblack@eecs.umich.edu{ 7825669Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 7835669Sgblack@eecs.umich.edu 7845669Sgblack@eecs.umich.edu // received a response from the icache: execute the received 7853658Sktlim@umich.edu // instruction 7862839Sktlim@umich.edu 7872798Sktlim@umich.edu assert(!pkt || !pkt->isError()); 7882798Sktlim@umich.edu assert(_status == IcacheWaitResponse); 7892798Sktlim@umich.edu 7902623SN/A _status = Running; 7915726Sgblack@eecs.umich.edu 7925726Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick() - previousTick); 7932623SN/A previousTick = curTick(); 7942623SN/A 7953170Sstever@eecs.umich.edu if (getState() == SimObject::Draining) { 7963170Sstever@eecs.umich.edu if (pkt) { 7975894Sgblack@eecs.umich.edu delete pkt->req; 7985894Sgblack@eecs.umich.edu delete pkt; 7993170Sstever@eecs.umich.edu } 8002644Sstever@eecs.umich.edu 8015894Sgblack@eecs.umich.edu completeDrain(); 8025001Sgblack@eecs.umich.edu return; 8035001Sgblack@eecs.umich.edu } 8045001Sgblack@eecs.umich.edu 8053170Sstever@eecs.umich.edu preExecute(); 8064998Sgblack@eecs.umich.edu if (curStaticInst && curStaticInst->isMemRef()) { 8072644Sstever@eecs.umich.edu // load or store: just send to dcache 8085103Ssaidi@eecs.umich.edu Fault fault = curStaticInst->initiateAcc(this, traceData); 8095103Ssaidi@eecs.umich.edu 8105103Ssaidi@eecs.umich.edu // If we're not running now the instruction will complete in a dcache 8115103Ssaidi@eecs.umich.edu // response callback or the instruction faulted and has started an 8122644Sstever@eecs.umich.edu // ifetch 8132644Sstever@eecs.umich.edu if (_status == Running) { 8145726Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 8152623SN/A // If there was a fault, we shouldn't trace this instruction. 8162623SN/A delete traceData; 8174998Sgblack@eecs.umich.edu traceData = NULL; 8184998Sgblack@eecs.umich.edu } 8194998Sgblack@eecs.umich.edu 8204998Sgblack@eecs.umich.edu postExecute(); 8217655Sali.saidi@arm.com // @todo remove me after debugging with legion done 8225001Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8235001Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 8245001Sgblack@eecs.umich.edu instCnt++; 8254998Sgblack@eecs.umich.edu advanceInst(fault); 8262644Sstever@eecs.umich.edu } 8275103Ssaidi@eecs.umich.edu } else if (curStaticInst) { 8285103Ssaidi@eecs.umich.edu // non-memory instruction: execute completely now 8295103Ssaidi@eecs.umich.edu Fault fault = curStaticInst->execute(this, traceData); 8305103Ssaidi@eecs.umich.edu 8312644Sstever@eecs.umich.edu // keep an instruction count 8325726Sgblack@eecs.umich.edu if (fault == NoFault) 8335726Sgblack@eecs.umich.edu countInst(); 8342623SN/A else if (traceData && !DTRACE(ExecFaulting)) { 8353658Sktlim@umich.edu delete traceData; 8365669Sgblack@eecs.umich.edu traceData = NULL; 8375669Sgblack@eecs.umich.edu } 8385669Sgblack@eecs.umich.edu 8395669Sgblack@eecs.umich.edu postExecute(); 8402623SN/A // @todo remove me after debugging with legion done 8412623SN/A if (curStaticInst && (!curStaticInst->isMicroop() || 8422948Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8432948Ssaidi@eecs.umich.edu instCnt++; 8442948Ssaidi@eecs.umich.edu advanceInst(fault); 8452948Ssaidi@eecs.umich.edu } else { 8462948Ssaidi@eecs.umich.edu advanceInst(NoFault); 8472623SN/A } 8482623SN/A 8493349Sbinkertn@umich.edu if (pkt) { 8502623SN/A delete pkt->req; 8514986Ssaidi@eecs.umich.edu delete pkt; 8523310Srdreslin@umich.edu } 8534584Ssaidi@eecs.umich.edu} 8542948Ssaidi@eecs.umich.edu 8553495Sktlim@umich.eduvoid 8563310Srdreslin@umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 8573310Srdreslin@umich.edu{ 8583495Sktlim@umich.edu cpu->completeIfetch(pkt); 8592948Ssaidi@eecs.umich.edu} 8603310Srdreslin@umich.edu 8613310Srdreslin@umich.edubool 8624870Sstever@eecs.umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 8634433Ssaidi@eecs.umich.edu{ 8644433Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8654433Ssaidi@eecs.umich.edu // delay processing of returned data until next CPU clock edge 8664433Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick()); 8674433Ssaidi@eecs.umich.edu 8684433Ssaidi@eecs.umich.edu if (next_tick == curTick()) 8693310Srdreslin@umich.edu cpu->completeIfetch(pkt); 8704433Ssaidi@eecs.umich.edu else 8714433Ssaidi@eecs.umich.edu tickEvent.schedule(pkt, next_tick); 8722623SN/A 8732623SN/A return true; 8742657Ssaidi@eecs.umich.edu } 8752623SN/A else if (pkt->wasNacked()) { 8762623SN/A assert(cpu->_status == IcacheWaitResponse); 8772623SN/A pkt->reinitNacked(); 8782623SN/A if (!sendTiming(pkt)) { 8792623SN/A cpu->_status = IcacheRetry; 8802623SN/A cpu->ifetch_pkt = pkt; 8813349Sbinkertn@umich.edu } 8822657Ssaidi@eecs.umich.edu } 8832657Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8842657Ssaidi@eecs.umich.edu return true; 8852657Ssaidi@eecs.umich.edu} 8862623SN/A 8872623SN/Avoid 8882623SN/ATimingSimpleCPU::IcachePort::recvRetry() 8893349Sbinkertn@umich.edu{ 8902623SN/A // we shouldn't get a retry unless we have a packet that we're 8912623SN/A // waiting to transmit 8922623SN/A assert(cpu->ifetch_pkt != NULL); 8934870Sstever@eecs.umich.edu assert(cpu->_status == IcacheRetry); 8947516Shestness@cs.utexas.edu PacketPtr tmp = cpu->ifetch_pkt; 8957516Shestness@cs.utexas.edu if (sendTiming(tmp)) { 8962623SN/A cpu->_status = IcacheWaitResponse; 8975099Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8983222Sktlim@umich.edu } 8993184Srdreslin@umich.edu} 9005728Sgblack@eecs.umich.edu 9015728Sgblack@eecs.umich.eduvoid 9025728Sgblack@eecs.umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 9035728Sgblack@eecs.umich.edu{ 9045728Sgblack@eecs.umich.edu // received a response from the dcache: complete the load or store 9055728Sgblack@eecs.umich.edu // instruction 9065728Sgblack@eecs.umich.edu assert(!pkt->isError()); 9075728Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 9085728Sgblack@eecs.umich.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 9095728Sgblack@eecs.umich.edu 9105728Sgblack@eecs.umich.edu numCycles += tickToCycles(curTick() - previousTick); 9115728Sgblack@eecs.umich.edu previousTick = curTick(); 9125728Sgblack@eecs.umich.edu 9135728Sgblack@eecs.umich.edu if (pkt->senderState) { 9145728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9155728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 9165728Sgblack@eecs.umich.edu assert(send_state); 9175728Sgblack@eecs.umich.edu delete pkt->req; 9185728Sgblack@eecs.umich.edu delete pkt; 9195728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9205728Sgblack@eecs.umich.edu delete send_state; 9215728Sgblack@eecs.umich.edu 9225728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9235728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9245728Sgblack@eecs.umich.edu assert(main_send_state); 9255728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 9265728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 9272623SN/A main_send_state->outstanding--; 9282623SN/A 9294998Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 9304998Sgblack@eecs.umich.edu return; 9314998Sgblack@eecs.umich.edu } else { 9325001Sgblack@eecs.umich.edu delete main_send_state; 9335001Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 9345001Sgblack@eecs.umich.edu pkt = big_pkt; 9355001Sgblack@eecs.umich.edu } 9365001Sgblack@eecs.umich.edu } 9374998Sgblack@eecs.umich.edu 9385507Sstever@gmail.com _status = Running; 9395507Sstever@gmail.com 9406102Sgblack@eecs.umich.edu Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 9413170Sstever@eecs.umich.edu 9423170Sstever@eecs.umich.edu // keep an instruction count 9433170Sstever@eecs.umich.edu if (fault == NoFault) 9442644Sstever@eecs.umich.edu countInst(); 9452644Sstever@eecs.umich.edu else if (traceData) { 9462644Sstever@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 9473184Srdreslin@umich.edu delete traceData; 9483227Sktlim@umich.edu traceData = NULL; 9493201Shsul@eecs.umich.edu } 9503201Shsul@eecs.umich.edu 9513201Shsul@eecs.umich.edu // the locked flag may be cleared on the response packet, so check 9523201Shsul@eecs.umich.edu // pkt->req and not pkt to see if it was a load-locked 9533201Shsul@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 9543201Shsul@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 9553201Shsul@eecs.umich.edu } 9562644Sstever@eecs.umich.edu 9572623SN/A delete pkt->req; 9582623SN/A delete pkt; 9592623SN/A 9602798Sktlim@umich.edu postExecute(); 9612839Sktlim@umich.edu 9622798Sktlim@umich.edu if (getState() == SimObject::Draining) { 9632839Sktlim@umich.edu advancePC(fault); 9642901Ssaidi@eecs.umich.edu completeDrain(); 9652839Sktlim@umich.edu 9662798Sktlim@umich.edu return; 9672623SN/A } 9684192Sktlim@umich.edu 9694192Sktlim@umich.edu advanceInst(fault); 9704192Sktlim@umich.edu} 9714192Sktlim@umich.edu 9724192Sktlim@umich.edu 9734192Sktlim@umich.eduvoid 9744192Sktlim@umich.eduTimingSimpleCPU::completeDrain() 9754192Sktlim@umich.edu{ 9765497Ssaidi@eecs.umich.edu DPRINTF(Config, "Done draining\n"); 9774192Sktlim@umich.edu changeState(SimObject::Drained); 9784192Sktlim@umich.edu drainEvent->process(); 9794192Sktlim@umich.edu} 9802623SN/A 9813349Sbinkertn@umich.eduvoid 9822623SN/ATimingSimpleCPU::DcachePort::setPeer(Port *port) 9834986Ssaidi@eecs.umich.edu{ 9843310Srdreslin@umich.edu Port::setPeer(port); 9854584Ssaidi@eecs.umich.edu 9862948Ssaidi@eecs.umich.edu#if FULL_SYSTEM 9875728Sgblack@eecs.umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 9883310Srdreslin@umich.edu // Ports) 9895728Sgblack@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 9903495Sktlim@umich.edu#endif 9915728Sgblack@eecs.umich.edu} 9922948Ssaidi@eecs.umich.edu 9933310Srdreslin@umich.edubool 9943310Srdreslin@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 9954870Sstever@eecs.umich.edu{ 9964433Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 9974433Ssaidi@eecs.umich.edu // delay processing of returned data until next CPU clock edge 9984433Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick()); 9994433Ssaidi@eecs.umich.edu 10004433Ssaidi@eecs.umich.edu if (next_tick == curTick()) { 10014433Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 10023310Srdreslin@umich.edu } else { 10034433Ssaidi@eecs.umich.edu if (!tickEvent.scheduled()) { 10044433Ssaidi@eecs.umich.edu tickEvent.schedule(pkt, next_tick); 10052948Ssaidi@eecs.umich.edu } else { 10062948Ssaidi@eecs.umich.edu // In the case of a split transaction and a cache that is 10072948Ssaidi@eecs.umich.edu // faster than a CPU we could get two responses before 10082948Ssaidi@eecs.umich.edu // next_tick expires 10092948Ssaidi@eecs.umich.edu if (!retryEvent.scheduled()) 10102630SN/A schedule(retryEvent, next_tick); 10112623SN/A return false; 10122623SN/A } 10132657Ssaidi@eecs.umich.edu } 10142623SN/A 10152623SN/A return true; 10162623SN/A } 10172623SN/A else if (pkt->wasNacked()) { 10182623SN/A assert(cpu->_status == DcacheWaitResponse); 10192623SN/A pkt->reinitNacked(); 10203349Sbinkertn@umich.edu if (!sendTiming(pkt)) { 10215728Sgblack@eecs.umich.edu cpu->_status = DcacheRetry; 10225728Sgblack@eecs.umich.edu cpu->dcache_pkt = pkt; 10235728Sgblack@eecs.umich.edu } 10245728Sgblack@eecs.umich.edu } 10255728Sgblack@eecs.umich.edu //Snooping a Coherence Request, do nothing 10265728Sgblack@eecs.umich.edu return true; 10275728Sgblack@eecs.umich.edu} 10285728Sgblack@eecs.umich.edu 10295728Sgblack@eecs.umich.eduvoid 10305728Sgblack@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 10315728Sgblack@eecs.umich.edu{ 10325728Sgblack@eecs.umich.edu cpu->completeDataAccess(pkt); 10335728Sgblack@eecs.umich.edu} 10345728Sgblack@eecs.umich.edu 10355728Sgblack@eecs.umich.eduvoid 10365728Sgblack@eecs.umich.eduTimingSimpleCPU::DcachePort::recvRetry() 10375728Sgblack@eecs.umich.edu{ 10385728Sgblack@eecs.umich.edu // we shouldn't get a retry unless we have a packet that we're 10395728Sgblack@eecs.umich.edu // waiting to transmit 10405728Sgblack@eecs.umich.edu assert(cpu->dcache_pkt != NULL); 10415728Sgblack@eecs.umich.edu assert(cpu->_status == DcacheRetry); 10425728Sgblack@eecs.umich.edu PacketPtr tmp = cpu->dcache_pkt; 10435728Sgblack@eecs.umich.edu if (tmp->senderState) { 10445728Sgblack@eecs.umich.edu // This is a packet from a split access. 10455728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 10465728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 10475728Sgblack@eecs.umich.edu assert(send_state); 10485728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 10495728Sgblack@eecs.umich.edu 10505728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 10512657Ssaidi@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 10523170Sstever@eecs.umich.edu assert(main_send_state); 10532657Ssaidi@eecs.umich.edu 10542657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 10552623SN/A // If we were able to send without retrying, record that fact 10562623SN/A // and try sending the other fragment. 10575606Snate@binkert.org send_state->clearFromParent(); 10585606Snate@binkert.org int other_index = main_send_state->getPendingFragment(); 10595606Snate@binkert.org if (other_index > 0) { 10605103Ssaidi@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 10615606Snate@binkert.org cpu->dcache_pkt = tmp; 10625103Ssaidi@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 10635103Ssaidi@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 10645103Ssaidi@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 10655103Ssaidi@eecs.umich.edu } 10665103Ssaidi@eecs.umich.edu } else { 10675103Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10685103Ssaidi@eecs.umich.edu // memory system takes ownership of packet 10695103Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 10705103Ssaidi@eecs.umich.edu } 10715336Shines@cs.fsu.edu } 10725103Ssaidi@eecs.umich.edu } else if (sendTiming(tmp)) { 10735103Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10745103Ssaidi@eecs.umich.edu // memory system takes ownership of packet 10755103Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 10762623SN/A } 10775315Sstever@gmail.com} 10785315Sstever@gmail.com 10795315Sstever@gmail.comTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 10805315Sstever@gmail.com Tick t) 10815315Sstever@gmail.com : pkt(_pkt), cpu(_cpu) 10825315Sstever@gmail.com{ 10835315Sstever@gmail.com cpu->schedule(this, t); 10842623SN/A} 10852623SN/A 10862623SN/Avoid 10872623SN/ATimingSimpleCPU::IprEvent::process() 10884762Snate@binkert.org{ 10894762Snate@binkert.org cpu->completeDataAccess(pkt); 10902623SN/A} 10915529Snate@binkert.org 10925529Snate@binkert.orgconst char * 10934762Snate@binkert.orgTimingSimpleCPU::IprEvent::description() const 10944762Snate@binkert.org{ 10952623SN/A return "Timing Simple CPU Delay IPR event"; 10965529Snate@binkert.org} 10972623SN/A 1098 1099void 1100TimingSimpleCPU::printAddr(Addr a) 1101{ 1102 dcachePort.printAddr(a); 1103} 1104 1105 1106//////////////////////////////////////////////////////////////////////// 1107// 1108// TimingSimpleCPU Simulation Object 1109// 1110TimingSimpleCPU * 1111TimingSimpleCPUParams::create() 1112{ 1113 numThreads = 1; 1114#if !FULL_SYSTEM 1115 if (workload.size() != 1) 1116 panic("only one workload allowed"); 1117#endif 1118 return new TimingSimpleCPU(this); 1119} 1120