timing.cc revision 7911
12623SN/A/* 27725SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 445103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 482623SN/A#include "cpu/exetrace.hh" 492623SN/A#include "cpu/simple/timing.hh" 503348Sbinkertn@umich.edu#include "mem/packet.hh" 513348Sbinkertn@umich.edu#include "mem/packet_access.hh" 524762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 537678Sgblack@eecs.umich.edu#include "sim/faults.hh" 542901Ssaidi@eecs.umich.edu#include "sim/system.hh" 552623SN/A 562623SN/Ausing namespace std; 572623SN/Ausing namespace TheISA; 582623SN/A 592856Srdreslin@umich.eduPort * 602856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 612856Srdreslin@umich.edu{ 622856Srdreslin@umich.edu if (if_name == "dcache_port") 632856Srdreslin@umich.edu return &dcachePort; 642856Srdreslin@umich.edu else if (if_name == "icache_port") 652856Srdreslin@umich.edu return &icachePort; 662856Srdreslin@umich.edu else 672856Srdreslin@umich.edu panic("No Such Port\n"); 682856Srdreslin@umich.edu} 692623SN/A 702623SN/Avoid 712623SN/ATimingSimpleCPU::init() 722623SN/A{ 732623SN/A BaseCPU::init(); 742623SN/A#if FULL_SYSTEM 752680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 762680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 772623SN/A 782623SN/A // initialize CPU, including PC 795712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 802623SN/A } 812623SN/A#endif 822623SN/A} 832623SN/A 842623SN/ATick 853349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 862623SN/A{ 872623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 887823Ssteve.reinhardt@amd.com return curTick(); 892623SN/A} 902623SN/A 912623SN/Avoid 923349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 932623SN/A{ 943184Srdreslin@umich.edu //No internal storage to update, jusst return 953184Srdreslin@umich.edu return; 962623SN/A} 972623SN/A 982623SN/Avoid 992623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 1002623SN/A{ 1013647Srdreslin@umich.edu if (status == RangeChange) { 1023647Srdreslin@umich.edu if (!snoopRangeSent) { 1033647Srdreslin@umich.edu snoopRangeSent = true; 1043647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1053647Srdreslin@umich.edu } 1062631SN/A return; 1073647Srdreslin@umich.edu } 1082631SN/A 1092623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 1102623SN/A} 1112623SN/A 1122948Ssaidi@eecs.umich.edu 1132948Ssaidi@eecs.umich.eduvoid 1143349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1152948Ssaidi@eecs.umich.edu{ 1162948Ssaidi@eecs.umich.edu pkt = _pkt; 1175606Snate@binkert.org cpu->schedule(this, t); 1182948Ssaidi@eecs.umich.edu} 1192948Ssaidi@eecs.umich.edu 1205529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1215894Sgblack@eecs.umich.edu : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 1225894Sgblack@eecs.umich.edu dcachePort(this, p->clock), fetchEvent(this) 1232623SN/A{ 1242623SN/A _status = Idle; 1253647Srdreslin@umich.edu 1263647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1273647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1283647Srdreslin@umich.edu 1292623SN/A ifetch_pkt = dcache_pkt = NULL; 1302839Sktlim@umich.edu drainEvent = NULL; 1313222Sktlim@umich.edu previousTick = 0; 1322901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1337897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1342623SN/A} 1352623SN/A 1362623SN/A 1372623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1382623SN/A{ 1392623SN/A} 1402623SN/A 1412623SN/Avoid 1422623SN/ATimingSimpleCPU::serialize(ostream &os) 1432623SN/A{ 1442915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1452915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1462623SN/A BaseSimpleCPU::serialize(os); 1472623SN/A} 1482623SN/A 1492623SN/Avoid 1502623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1512623SN/A{ 1522915Sktlim@umich.edu SimObject::State so_state; 1532915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1542623SN/A BaseSimpleCPU::unserialize(cp, section); 1552798Sktlim@umich.edu} 1562798Sktlim@umich.edu 1572901Ssaidi@eecs.umich.eduunsigned int 1582839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1592798Sktlim@umich.edu{ 1602839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1612798Sktlim@umich.edu // an access to complete. 1625496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1632901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1642901Ssaidi@eecs.umich.edu return 0; 1652798Sktlim@umich.edu } else { 1662839Sktlim@umich.edu changeState(SimObject::Draining); 1672839Sktlim@umich.edu drainEvent = drain_event; 1682901Ssaidi@eecs.umich.edu return 1; 1692798Sktlim@umich.edu } 1702623SN/A} 1712623SN/A 1722623SN/Avoid 1732798Sktlim@umich.eduTimingSimpleCPU::resume() 1742623SN/A{ 1755221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1762798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1774762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1783201Shsul@eecs.umich.edu 1795710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1805710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1812915Sktlim@umich.edu 1825710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1832623SN/A } 1842798Sktlim@umich.edu 1852901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1862798Sktlim@umich.edu} 1872798Sktlim@umich.edu 1882798Sktlim@umich.eduvoid 1892798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1902798Sktlim@umich.edu{ 1915496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1922798Sktlim@umich.edu _status = SwitchedOut; 1937823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 1942867Sktlim@umich.edu 1952867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1962867Sktlim@umich.edu // we'll need to cancel it. 1975710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1985606Snate@binkert.org deschedule(fetchEvent); 1992623SN/A} 2002623SN/A 2012623SN/A 2022623SN/Avoid 2032623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2042623SN/A{ 2054192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2062623SN/A 2072680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2082623SN/A // running and schedule its tick event. 2092680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2102680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2112680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2122623SN/A _status = Running; 2132623SN/A break; 2142623SN/A } 2152623SN/A } 2163201Shsul@eecs.umich.edu 2173201Shsul@eecs.umich.edu if (_status != Running) { 2183201Shsul@eecs.umich.edu _status = Idle; 2193201Shsul@eecs.umich.edu } 2205169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2217823Ssteve.reinhardt@amd.com previousTick = curTick(); 2222623SN/A} 2232623SN/A 2242623SN/A 2252623SN/Avoid 2262623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2272623SN/A{ 2285221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2295221Ssaidi@eecs.umich.edu 2302623SN/A assert(thread_num == 0); 2312683Sktlim@umich.edu assert(thread); 2322623SN/A 2332623SN/A assert(_status == Idle); 2342623SN/A 2352623SN/A notIdleFraction++; 2362623SN/A _status = Running; 2373686Sktlim@umich.edu 2382623SN/A // kick things off by initiating the fetch of the next instruction 2397823Ssteve.reinhardt@amd.com schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 2402623SN/A} 2412623SN/A 2422623SN/A 2432623SN/Avoid 2442623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2452623SN/A{ 2465221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2475221Ssaidi@eecs.umich.edu 2482623SN/A assert(thread_num == 0); 2492683Sktlim@umich.edu assert(thread); 2502623SN/A 2516043Sgblack@eecs.umich.edu if (_status == Idle) 2526043Sgblack@eecs.umich.edu return; 2536043Sgblack@eecs.umich.edu 2542644Sstever@eecs.umich.edu assert(_status == Running); 2552623SN/A 2562644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2572644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2582623SN/A 2592623SN/A notIdleFraction--; 2602623SN/A _status = Idle; 2612623SN/A} 2622623SN/A 2635728Sgblack@eecs.umich.edubool 2645728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2655728Sgblack@eecs.umich.edu{ 2665728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2675728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 2685728Sgblack@eecs.umich.edu Tick delay; 2695728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2707823Ssteve.reinhardt@amd.com new IprEvent(pkt, this, nextCycle(curTick() + delay)); 2715728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2725728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2735728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2745728Sgblack@eecs.umich.edu _status = DcacheRetry; 2755728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2765728Sgblack@eecs.umich.edu } else { 2775728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2785728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2795728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2805728Sgblack@eecs.umich.edu } 2815728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2825728Sgblack@eecs.umich.edu} 2832623SN/A 2845894Sgblack@eecs.umich.eduvoid 2856973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2866973Stjones1@inf.ed.ac.uk bool read) 2875744Sgblack@eecs.umich.edu{ 2885894Sgblack@eecs.umich.edu PacketPtr pkt; 2895894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2907691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2915894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2925894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2935894Sgblack@eecs.umich.edu pkt->makeResponse(); 2945894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2955894Sgblack@eecs.umich.edu } else if (read) { 2965894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2975894Sgblack@eecs.umich.edu } else { 2985894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2995894Sgblack@eecs.umich.edu 3006102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3015894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3025894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3035894Sgblack@eecs.umich.edu assert(res); 3045894Sgblack@eecs.umich.edu req->setExtraData(*res); 3055894Sgblack@eecs.umich.edu } 3065894Sgblack@eecs.umich.edu 3075894Sgblack@eecs.umich.edu if (do_access) { 3085894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3095894Sgblack@eecs.umich.edu handleWritePacket(); 3105894Sgblack@eecs.umich.edu } else { 3115894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3125894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3135894Sgblack@eecs.umich.edu } 3145894Sgblack@eecs.umich.edu } 3155894Sgblack@eecs.umich.edu} 3165894Sgblack@eecs.umich.edu 3175894Sgblack@eecs.umich.eduvoid 3186973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3196973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3205894Sgblack@eecs.umich.edu{ 3215894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3225894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3235894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3245894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3255894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3265894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3275894Sgblack@eecs.umich.edu } else if (read) { 3287911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3297911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3305894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3315894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3327911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3337911Shestness@cs.utexas.edu pkt2->senderState); 3345894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3355894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3365894Sgblack@eecs.umich.edu } 3375894Sgblack@eecs.umich.edu } 3385894Sgblack@eecs.umich.edu } else { 3395894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3407911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3417911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3425894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3435894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3445894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3457911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3467911Shestness@cs.utexas.edu pkt2->senderState); 3475894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3485894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3495894Sgblack@eecs.umich.edu } 3505894Sgblack@eecs.umich.edu } 3515894Sgblack@eecs.umich.edu } 3525894Sgblack@eecs.umich.edu} 3535894Sgblack@eecs.umich.edu 3545894Sgblack@eecs.umich.eduvoid 3555894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3565894Sgblack@eecs.umich.edu{ 3576739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3586739Sgblack@eecs.umich.edu // for instance prefetches. 3597823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 3607823Ssteve.reinhardt@amd.com previousTick = curTick(); 3615894Sgblack@eecs.umich.edu 3625894Sgblack@eecs.umich.edu if (traceData) { 3635894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3645894Sgblack@eecs.umich.edu delete traceData; 3655894Sgblack@eecs.umich.edu traceData = NULL; 3665744Sgblack@eecs.umich.edu } 3675744Sgblack@eecs.umich.edu 3685894Sgblack@eecs.umich.edu postExecute(); 3695894Sgblack@eecs.umich.edu 3705894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3715894Sgblack@eecs.umich.edu advancePC(fault); 3725894Sgblack@eecs.umich.edu completeDrain(); 3735894Sgblack@eecs.umich.edu } else { 3745894Sgblack@eecs.umich.edu advanceInst(fault); 3755894Sgblack@eecs.umich.edu } 3765894Sgblack@eecs.umich.edu} 3775894Sgblack@eecs.umich.edu 3785894Sgblack@eecs.umich.eduvoid 3795894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3805894Sgblack@eecs.umich.edu{ 3815894Sgblack@eecs.umich.edu MemCmd cmd; 3825894Sgblack@eecs.umich.edu if (read) { 3835894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3846102Sgblack@eecs.umich.edu if (req->isLLSC()) 3855894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3865894Sgblack@eecs.umich.edu } else { 3875894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3886102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3895894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3905894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3915894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3925894Sgblack@eecs.umich.edu } 3935894Sgblack@eecs.umich.edu } 3945894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 3955894Sgblack@eecs.umich.edu} 3965894Sgblack@eecs.umich.edu 3975894Sgblack@eecs.umich.eduvoid 3985894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3995894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 4005894Sgblack@eecs.umich.edu uint8_t *data, bool read) 4015894Sgblack@eecs.umich.edu{ 4025894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 4035894Sgblack@eecs.umich.edu 4045744Sgblack@eecs.umich.edu assert(!req1->isMmapedIpr() && !req2->isMmapedIpr()); 4055744Sgblack@eecs.umich.edu 4065894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 4075894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 4085894Sgblack@eecs.umich.edu return; 4095894Sgblack@eecs.umich.edu } 4105894Sgblack@eecs.umich.edu 4115894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 4125894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 4135894Sgblack@eecs.umich.edu 4145744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 4155744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 4165744Sgblack@eecs.umich.edu Packet::Broadcast); 4175744Sgblack@eecs.umich.edu 4187691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 4195744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4205744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4215744Sgblack@eecs.umich.edu 4225744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4235744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4245744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4255744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4265744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4275744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4285744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4295744Sgblack@eecs.umich.edu} 4305744Sgblack@eecs.umich.edu 4312623SN/AFault 4327520Sgblack@eecs.umich.eduTimingSimpleCPU::readBytes(Addr addr, uint8_t *data, 4337520Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4342623SN/A{ 4355728Sgblack@eecs.umich.edu Fault fault; 4365728Sgblack@eecs.umich.edu const int asid = 0; 4376221Snate@binkert.org const ThreadID tid = 0; 4387720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4396227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4406973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4412623SN/A 4427045Ssteve.reinhardt@amd.com if (traceData) { 4437045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4447045Ssteve.reinhardt@amd.com } 4457045Ssteve.reinhardt@amd.com 4467520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4476221Snate@binkert.org flags, pc, _cpuId, tid); 4485728Sgblack@eecs.umich.edu 4497520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4505744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4515728Sgblack@eecs.umich.edu 4525894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4535744Sgblack@eecs.umich.edu if (split_addr > addr) { 4545894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4556102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4565894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4575894Sgblack@eecs.umich.edu 4586973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4597520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4606973Stjones1@inf.ed.ac.uk NULL, mode); 4616973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 4626973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 4636973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 4646973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 4656973Stjones1@inf.ed.ac.uk 4666973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4676973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4685744Sgblack@eecs.umich.edu } else { 4696973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4707520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4716973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation 4726973Stjones1@inf.ed.ac.uk = new DataTranslation<TimingSimpleCPU>(this, state); 4736973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4742623SN/A } 4752623SN/A 4765728Sgblack@eecs.umich.edu return NoFault; 4772623SN/A} 4782623SN/A 4797520Sgblack@eecs.umich.edutemplate <class T> 4807520Sgblack@eecs.umich.eduFault 4817520Sgblack@eecs.umich.eduTimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 4827520Sgblack@eecs.umich.edu{ 4837520Sgblack@eecs.umich.edu return readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 4847520Sgblack@eecs.umich.edu} 4857520Sgblack@eecs.umich.edu 4862623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4872623SN/A 4882623SN/Atemplate 4892623SN/AFault 4904040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 4914040Ssaidi@eecs.umich.edu 4924040Ssaidi@eecs.umich.edutemplate 4934040Ssaidi@eecs.umich.eduFault 4944115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 4954115Ssaidi@eecs.umich.edu 4964115Ssaidi@eecs.umich.edutemplate 4974115Ssaidi@eecs.umich.eduFault 4982623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 4992623SN/A 5002623SN/Atemplate 5012623SN/AFault 5022623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 5032623SN/A 5042623SN/Atemplate 5052623SN/AFault 5062623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 5072623SN/A 5082623SN/Atemplate 5092623SN/AFault 5102623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 5112623SN/A 5122623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5132623SN/A 5142623SN/Atemplate<> 5152623SN/AFault 5162623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 5172623SN/A{ 5182623SN/A return read(addr, *(uint64_t*)&data, flags); 5192623SN/A} 5202623SN/A 5212623SN/Atemplate<> 5222623SN/AFault 5232623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 5242623SN/A{ 5252623SN/A return read(addr, *(uint32_t*)&data, flags); 5262623SN/A} 5272623SN/A 5282623SN/Atemplate<> 5292623SN/AFault 5302623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 5312623SN/A{ 5322623SN/A return read(addr, (uint32_t&)data, flags); 5332623SN/A} 5342623SN/A 5355728Sgblack@eecs.umich.edubool 5365728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 5375728Sgblack@eecs.umich.edu{ 5385728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 5395728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 5405728Sgblack@eecs.umich.edu Tick delay; 5415728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 5427823Ssteve.reinhardt@amd.com new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 5435728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5445728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5455728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 5465728Sgblack@eecs.umich.edu _status = DcacheRetry; 5475728Sgblack@eecs.umich.edu } else { 5485728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 5495728Sgblack@eecs.umich.edu // memory system takes ownership of packet 5505728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5515728Sgblack@eecs.umich.edu } 5525728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 5535728Sgblack@eecs.umich.edu} 5542623SN/A 5552623SN/AFault 5567520Sgblack@eecs.umich.eduTimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size, 5577520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 5582623SN/A{ 5595728Sgblack@eecs.umich.edu const int asid = 0; 5606221Snate@binkert.org const ThreadID tid = 0; 5617720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5626227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 5636973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5643169Sstever@eecs.umich.edu 5657045Ssteve.reinhardt@amd.com if (traceData) { 5667045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 5677045Ssteve.reinhardt@amd.com } 5687045Ssteve.reinhardt@amd.com 5697520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 5706221Snate@binkert.org flags, pc, _cpuId, tid); 5715728Sgblack@eecs.umich.edu 5727520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5735744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5745728Sgblack@eecs.umich.edu 5755894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5765744Sgblack@eecs.umich.edu if (split_addr > addr) { 5775894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5786102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5795894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5805894Sgblack@eecs.umich.edu 5816973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5827520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, data, res, mode); 5836973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 5846973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 5856973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 5866973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 5876973Stjones1@inf.ed.ac.uk 5886973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5896973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5905744Sgblack@eecs.umich.edu } else { 5916973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5927520Sgblack@eecs.umich.edu new WholeTranslationState(req, data, res, mode); 5936973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation = 5946973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state); 5956973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5962623SN/A } 5972623SN/A 5987045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5995728Sgblack@eecs.umich.edu return NoFault; 6002623SN/A} 6012623SN/A 6027520Sgblack@eecs.umich.eduFault 6037520Sgblack@eecs.umich.eduTimingSimpleCPU::writeBytes(uint8_t *data, unsigned size, 6047520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 6057520Sgblack@eecs.umich.edu{ 6067520Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 6077520Sgblack@eecs.umich.edu memcpy(newData, data, size); 6087520Sgblack@eecs.umich.edu return writeTheseBytes(newData, size, addr, flags, res); 6097520Sgblack@eecs.umich.edu} 6107520Sgblack@eecs.umich.edu 6117520Sgblack@eecs.umich.edutemplate <class T> 6127520Sgblack@eecs.umich.eduFault 6137520Sgblack@eecs.umich.eduTimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 6147520Sgblack@eecs.umich.edu{ 6157520Sgblack@eecs.umich.edu if (traceData) { 6167520Sgblack@eecs.umich.edu traceData->setData(data); 6177520Sgblack@eecs.umich.edu } 6187691SAli.Saidi@ARM.com T *dataP = (T*) new uint8_t[sizeof(T)]; 6197520Sgblack@eecs.umich.edu *dataP = TheISA::htog(data); 6207520Sgblack@eecs.umich.edu 6217520Sgblack@eecs.umich.edu return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res); 6227520Sgblack@eecs.umich.edu} 6237520Sgblack@eecs.umich.edu 6242623SN/A 6252623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 6262623SN/Atemplate 6272623SN/AFault 6284224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 6294224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6304224Sgblack@eecs.umich.edu 6314224Sgblack@eecs.umich.edutemplate 6324224Sgblack@eecs.umich.eduFault 6334224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 6344224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6354224Sgblack@eecs.umich.edu 6364224Sgblack@eecs.umich.edutemplate 6374224Sgblack@eecs.umich.eduFault 6382623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 6392623SN/A unsigned flags, uint64_t *res); 6402623SN/A 6412623SN/Atemplate 6422623SN/AFault 6432623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 6442623SN/A unsigned flags, uint64_t *res); 6452623SN/A 6462623SN/Atemplate 6472623SN/AFault 6482623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 6492623SN/A unsigned flags, uint64_t *res); 6502623SN/A 6512623SN/Atemplate 6522623SN/AFault 6532623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 6542623SN/A unsigned flags, uint64_t *res); 6552623SN/A 6562623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 6572623SN/A 6582623SN/Atemplate<> 6592623SN/AFault 6602623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 6612623SN/A{ 6622623SN/A return write(*(uint64_t*)&data, addr, flags, res); 6632623SN/A} 6642623SN/A 6652623SN/Atemplate<> 6662623SN/AFault 6672623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 6682623SN/A{ 6692623SN/A return write(*(uint32_t*)&data, addr, flags, res); 6702623SN/A} 6712623SN/A 6722623SN/A 6732623SN/Atemplate<> 6742623SN/AFault 6752623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6762623SN/A{ 6772623SN/A return write((uint32_t)data, addr, flags, res); 6782623SN/A} 6792623SN/A 6802623SN/A 6812623SN/Avoid 6826973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 6836973Stjones1@inf.ed.ac.uk{ 6846973Stjones1@inf.ed.ac.uk _status = Running; 6856973Stjones1@inf.ed.ac.uk 6866973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 6876973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 6886973Stjones1@inf.ed.ac.uk state->setNoFault(); 6896973Stjones1@inf.ed.ac.uk } 6907691SAli.Saidi@ARM.com delete [] state->data; 6916973Stjones1@inf.ed.ac.uk state->deleteReqs(); 6926973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 6936973Stjones1@inf.ed.ac.uk } else { 6946973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 6956973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 6966973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 6976973Stjones1@inf.ed.ac.uk } else { 6986973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 6996973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 7006973Stjones1@inf.ed.ac.uk } 7016973Stjones1@inf.ed.ac.uk } 7026973Stjones1@inf.ed.ac.uk 7036973Stjones1@inf.ed.ac.uk delete state; 7046973Stjones1@inf.ed.ac.uk} 7056973Stjones1@inf.ed.ac.uk 7066973Stjones1@inf.ed.ac.uk 7076973Stjones1@inf.ed.ac.ukvoid 7082623SN/ATimingSimpleCPU::fetch() 7092623SN/A{ 7105221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 7115221Ssaidi@eecs.umich.edu 7123387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 7133387Sgblack@eecs.umich.edu checkForInterrupts(); 7142631SN/A 7155348Ssaidi@eecs.umich.edu checkPcEventQueue(); 7165348Ssaidi@eecs.umich.edu 7177720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 7187720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 7192623SN/A 7207720Sgblack@eecs.umich.edu if (needToFetch) { 7215669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 7225712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 7235894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 7246023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 7256023Snate@binkert.org BaseTLB::Execute); 7262623SN/A } else { 7275669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7285669Sgblack@eecs.umich.edu completeIfetch(NULL); 7295894Sgblack@eecs.umich.edu 7307823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 7317823Ssteve.reinhardt@amd.com previousTick = curTick(); 7325894Sgblack@eecs.umich.edu } 7335894Sgblack@eecs.umich.edu} 7345894Sgblack@eecs.umich.edu 7355894Sgblack@eecs.umich.edu 7365894Sgblack@eecs.umich.eduvoid 7375894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 7385894Sgblack@eecs.umich.edu{ 7395894Sgblack@eecs.umich.edu if (fault == NoFault) { 7405894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 7415894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 7425894Sgblack@eecs.umich.edu 7435894Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 7445894Sgblack@eecs.umich.edu // Need to wait for retry 7455894Sgblack@eecs.umich.edu _status = IcacheRetry; 7465894Sgblack@eecs.umich.edu } else { 7475894Sgblack@eecs.umich.edu // Need to wait for cache to respond 7485894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7495894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 7505894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 7515894Sgblack@eecs.umich.edu } 7525894Sgblack@eecs.umich.edu } else { 7535894Sgblack@eecs.umich.edu delete req; 7545894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 7555894Sgblack@eecs.umich.edu advanceInst(fault); 7562623SN/A } 7573222Sktlim@umich.edu 7587823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 7597823Ssteve.reinhardt@amd.com previousTick = curTick(); 7602623SN/A} 7612623SN/A 7622623SN/A 7632623SN/Avoid 7642644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 7652623SN/A{ 7665726Sgblack@eecs.umich.edu if (fault != NoFault || !stayAtPC) 7675726Sgblack@eecs.umich.edu advancePC(fault); 7682623SN/A 7692631SN/A if (_status == Running) { 7702631SN/A // kick off fetch of next instruction... callback from icache 7712631SN/A // response will cause that instruction to be executed, 7722631SN/A // keeping the CPU running. 7732631SN/A fetch(); 7742631SN/A } 7752623SN/A} 7762623SN/A 7772623SN/A 7782623SN/Avoid 7793349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7802623SN/A{ 7815221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 7825221Ssaidi@eecs.umich.edu 7832623SN/A // received a response from the icache: execute the received 7842623SN/A // instruction 7855669Sgblack@eecs.umich.edu 7865669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 7872623SN/A assert(_status == IcacheWaitResponse); 7882798Sktlim@umich.edu 7892623SN/A _status = Running; 7902644Sstever@eecs.umich.edu 7917823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 7927823Ssteve.reinhardt@amd.com previousTick = curTick(); 7933222Sktlim@umich.edu 7942839Sktlim@umich.edu if (getState() == SimObject::Draining) { 7955669Sgblack@eecs.umich.edu if (pkt) { 7965669Sgblack@eecs.umich.edu delete pkt->req; 7975669Sgblack@eecs.umich.edu delete pkt; 7985669Sgblack@eecs.umich.edu } 7993658Sktlim@umich.edu 8002839Sktlim@umich.edu completeDrain(); 8012798Sktlim@umich.edu return; 8022798Sktlim@umich.edu } 8032798Sktlim@umich.edu 8042623SN/A preExecute(); 8057725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 8062623SN/A // load or store: just send to dcache 8072623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 8083170Sstever@eecs.umich.edu if (_status != Running) { 8093170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 8105894Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse || 8115894Sgblack@eecs.umich.edu _status == DcacheRetry || DTBWaitResponse); 8123170Sstever@eecs.umich.edu assert(fault == NoFault); 8132644Sstever@eecs.umich.edu } else { 8145894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 8155001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8165001Sgblack@eecs.umich.edu delete traceData; 8175001Sgblack@eecs.umich.edu traceData = NULL; 8183170Sstever@eecs.umich.edu } 8194998Sgblack@eecs.umich.edu 8202644Sstever@eecs.umich.edu postExecute(); 8215103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8225103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8235103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8245103Ssaidi@eecs.umich.edu instCnt++; 8252644Sstever@eecs.umich.edu advanceInst(fault); 8262644Sstever@eecs.umich.edu } 8275726Sgblack@eecs.umich.edu } else if (curStaticInst) { 8282623SN/A // non-memory instruction: execute completely now 8292623SN/A Fault fault = curStaticInst->execute(this, traceData); 8304998Sgblack@eecs.umich.edu 8314998Sgblack@eecs.umich.edu // keep an instruction count 8324998Sgblack@eecs.umich.edu if (fault == NoFault) 8334998Sgblack@eecs.umich.edu countInst(); 8347655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 8355001Sgblack@eecs.umich.edu delete traceData; 8365001Sgblack@eecs.umich.edu traceData = NULL; 8375001Sgblack@eecs.umich.edu } 8384998Sgblack@eecs.umich.edu 8392644Sstever@eecs.umich.edu postExecute(); 8405103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8415103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8425103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8435103Ssaidi@eecs.umich.edu instCnt++; 8442644Sstever@eecs.umich.edu advanceInst(fault); 8455726Sgblack@eecs.umich.edu } else { 8465726Sgblack@eecs.umich.edu advanceInst(NoFault); 8472623SN/A } 8483658Sktlim@umich.edu 8495669Sgblack@eecs.umich.edu if (pkt) { 8505669Sgblack@eecs.umich.edu delete pkt->req; 8515669Sgblack@eecs.umich.edu delete pkt; 8525669Sgblack@eecs.umich.edu } 8532623SN/A} 8542623SN/A 8552948Ssaidi@eecs.umich.eduvoid 8562948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 8572948Ssaidi@eecs.umich.edu{ 8582948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 8592948Ssaidi@eecs.umich.edu} 8602623SN/A 8612623SN/Abool 8623349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 8632623SN/A{ 8644986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8653310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8667823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 8672948Ssaidi@eecs.umich.edu 8687823Ssteve.reinhardt@amd.com if (next_tick == curTick()) 8693310Srdreslin@umich.edu cpu->completeIfetch(pkt); 8703310Srdreslin@umich.edu else 8713495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 8722948Ssaidi@eecs.umich.edu 8733310Srdreslin@umich.edu return true; 8743310Srdreslin@umich.edu } 8754870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 8764433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 8774433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8784433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 8794433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 8804433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 8814433Ssaidi@eecs.umich.edu } 8823310Srdreslin@umich.edu } 8834433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8844433Ssaidi@eecs.umich.edu return true; 8852623SN/A} 8862623SN/A 8872657Ssaidi@eecs.umich.eduvoid 8882623SN/ATimingSimpleCPU::IcachePort::recvRetry() 8892623SN/A{ 8902623SN/A // we shouldn't get a retry unless we have a packet that we're 8912623SN/A // waiting to transmit 8922623SN/A assert(cpu->ifetch_pkt != NULL); 8932623SN/A assert(cpu->_status == IcacheRetry); 8943349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8952657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8962657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8972657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8982657Ssaidi@eecs.umich.edu } 8992623SN/A} 9002623SN/A 9012623SN/Avoid 9023349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 9032623SN/A{ 9042623SN/A // received a response from the dcache: complete the load or store 9052623SN/A // instruction 9064870Sstever@eecs.umich.edu assert(!pkt->isError()); 9077516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 9087516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 9092623SN/A 9107823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 9117823Ssteve.reinhardt@amd.com previousTick = curTick(); 9123184Srdreslin@umich.edu 9135728Sgblack@eecs.umich.edu if (pkt->senderState) { 9145728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9155728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 9165728Sgblack@eecs.umich.edu assert(send_state); 9175728Sgblack@eecs.umich.edu delete pkt->req; 9185728Sgblack@eecs.umich.edu delete pkt; 9195728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9205728Sgblack@eecs.umich.edu delete send_state; 9215728Sgblack@eecs.umich.edu 9225728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9235728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9245728Sgblack@eecs.umich.edu assert(main_send_state); 9255728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 9265728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 9275728Sgblack@eecs.umich.edu main_send_state->outstanding--; 9285728Sgblack@eecs.umich.edu 9295728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 9305728Sgblack@eecs.umich.edu return; 9315728Sgblack@eecs.umich.edu } else { 9325728Sgblack@eecs.umich.edu delete main_send_state; 9335728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 9345728Sgblack@eecs.umich.edu pkt = big_pkt; 9355728Sgblack@eecs.umich.edu } 9365728Sgblack@eecs.umich.edu } 9375728Sgblack@eecs.umich.edu 9385728Sgblack@eecs.umich.edu _status = Running; 9395728Sgblack@eecs.umich.edu 9402623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 9412623SN/A 9424998Sgblack@eecs.umich.edu // keep an instruction count 9434998Sgblack@eecs.umich.edu if (fault == NoFault) 9444998Sgblack@eecs.umich.edu countInst(); 9455001Sgblack@eecs.umich.edu else if (traceData) { 9465001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 9475001Sgblack@eecs.umich.edu delete traceData; 9485001Sgblack@eecs.umich.edu traceData = NULL; 9495001Sgblack@eecs.umich.edu } 9504998Sgblack@eecs.umich.edu 9515507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 9525507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 9536102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 9543170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 9553170Sstever@eecs.umich.edu } 9563170Sstever@eecs.umich.edu 9572644Sstever@eecs.umich.edu delete pkt->req; 9582644Sstever@eecs.umich.edu delete pkt; 9592644Sstever@eecs.umich.edu 9603184Srdreslin@umich.edu postExecute(); 9613227Sktlim@umich.edu 9623201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 9633201Shsul@eecs.umich.edu advancePC(fault); 9643201Shsul@eecs.umich.edu completeDrain(); 9653201Shsul@eecs.umich.edu 9663201Shsul@eecs.umich.edu return; 9673201Shsul@eecs.umich.edu } 9683201Shsul@eecs.umich.edu 9692644Sstever@eecs.umich.edu advanceInst(fault); 9702623SN/A} 9712623SN/A 9722623SN/A 9732798Sktlim@umich.eduvoid 9742839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 9752798Sktlim@umich.edu{ 9762839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 9772901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 9782839Sktlim@umich.edu drainEvent->process(); 9792798Sktlim@umich.edu} 9802623SN/A 9814192Sktlim@umich.eduvoid 9824192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 9834192Sktlim@umich.edu{ 9844192Sktlim@umich.edu Port::setPeer(port); 9854192Sktlim@umich.edu 9864192Sktlim@umich.edu#if FULL_SYSTEM 9874192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 9884192Sktlim@umich.edu // Ports) 9895497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 9904192Sktlim@umich.edu#endif 9914192Sktlim@umich.edu} 9924192Sktlim@umich.edu 9932623SN/Abool 9943349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 9952623SN/A{ 9964986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 9973310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 9987823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 9992948Ssaidi@eecs.umich.edu 10007823Ssteve.reinhardt@amd.com if (next_tick == curTick()) { 10013310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 10025728Sgblack@eecs.umich.edu } else { 10037745SAli.Saidi@ARM.com if (!tickEvent.scheduled()) { 10047745SAli.Saidi@ARM.com tickEvent.schedule(pkt, next_tick); 10057745SAli.Saidi@ARM.com } else { 10067745SAli.Saidi@ARM.com // In the case of a split transaction and a cache that is 10077745SAli.Saidi@ARM.com // faster than a CPU we could get two responses before 10087745SAli.Saidi@ARM.com // next_tick expires 10097745SAli.Saidi@ARM.com if (!retryEvent.scheduled()) 10107745SAli.Saidi@ARM.com schedule(retryEvent, next_tick); 10117745SAli.Saidi@ARM.com return false; 10127745SAli.Saidi@ARM.com } 10135728Sgblack@eecs.umich.edu } 10142948Ssaidi@eecs.umich.edu 10153310Srdreslin@umich.edu return true; 10163310Srdreslin@umich.edu } 10174870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 10184433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 10194433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 10204433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 10214433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 10224433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 10234433Ssaidi@eecs.umich.edu } 10243310Srdreslin@umich.edu } 10254433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 10264433Ssaidi@eecs.umich.edu return true; 10272948Ssaidi@eecs.umich.edu} 10282948Ssaidi@eecs.umich.edu 10292948Ssaidi@eecs.umich.eduvoid 10302948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 10312948Ssaidi@eecs.umich.edu{ 10322630SN/A cpu->completeDataAccess(pkt); 10332623SN/A} 10342623SN/A 10352657Ssaidi@eecs.umich.eduvoid 10362623SN/ATimingSimpleCPU::DcachePort::recvRetry() 10372623SN/A{ 10382623SN/A // we shouldn't get a retry unless we have a packet that we're 10392623SN/A // waiting to transmit 10402623SN/A assert(cpu->dcache_pkt != NULL); 10412623SN/A assert(cpu->_status == DcacheRetry); 10423349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 10435728Sgblack@eecs.umich.edu if (tmp->senderState) { 10445728Sgblack@eecs.umich.edu // This is a packet from a split access. 10455728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 10465728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 10475728Sgblack@eecs.umich.edu assert(send_state); 10485728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 10495728Sgblack@eecs.umich.edu 10505728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 10515728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 10525728Sgblack@eecs.umich.edu assert(main_send_state); 10535728Sgblack@eecs.umich.edu 10545728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 10555728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 10565728Sgblack@eecs.umich.edu // and try sending the other fragment. 10575728Sgblack@eecs.umich.edu send_state->clearFromParent(); 10585728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 10595728Sgblack@eecs.umich.edu if (other_index > 0) { 10605728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 10615728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 10625728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 10635728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 10645728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 10655728Sgblack@eecs.umich.edu } 10665728Sgblack@eecs.umich.edu } else { 10675728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10685728Sgblack@eecs.umich.edu // memory system takes ownership of packet 10695728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 10705728Sgblack@eecs.umich.edu } 10715728Sgblack@eecs.umich.edu } 10725728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 10732657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10743170Sstever@eecs.umich.edu // memory system takes ownership of packet 10752657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 10762657Ssaidi@eecs.umich.edu } 10772623SN/A} 10782623SN/A 10795606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 10805606Snate@binkert.org Tick t) 10815606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 10825103Ssaidi@eecs.umich.edu{ 10835606Snate@binkert.org cpu->schedule(this, t); 10845103Ssaidi@eecs.umich.edu} 10855103Ssaidi@eecs.umich.edu 10865103Ssaidi@eecs.umich.eduvoid 10875103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 10885103Ssaidi@eecs.umich.edu{ 10895103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 10905103Ssaidi@eecs.umich.edu} 10915103Ssaidi@eecs.umich.edu 10925103Ssaidi@eecs.umich.educonst char * 10935336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 10945103Ssaidi@eecs.umich.edu{ 10955103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10965103Ssaidi@eecs.umich.edu} 10975103Ssaidi@eecs.umich.edu 10982623SN/A 10995315Sstever@gmail.comvoid 11005315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 11015315Sstever@gmail.com{ 11025315Sstever@gmail.com dcachePort.printAddr(a); 11035315Sstever@gmail.com} 11045315Sstever@gmail.com 11055315Sstever@gmail.com 11062623SN/A//////////////////////////////////////////////////////////////////////// 11072623SN/A// 11082623SN/A// TimingSimpleCPU Simulation Object 11092623SN/A// 11104762Snate@binkert.orgTimingSimpleCPU * 11114762Snate@binkert.orgTimingSimpleCPUParams::create() 11122623SN/A{ 11135529Snate@binkert.org numThreads = 1; 11145529Snate@binkert.org#if !FULL_SYSTEM 11154762Snate@binkert.org if (workload.size() != 1) 11164762Snate@binkert.org panic("only one workload allowed"); 11172623SN/A#endif 11185529Snate@binkert.org return new TimingSimpleCPU(this); 11192623SN/A} 1120